1 /*
2 * Based on arch/arm/kernel/asm-offsets.c
3 *
4 * Copyright (C) 1995-2003 Russell King
5 * 2001-2002 Keith Owens
6 * Copyright (C) 2012 ARM Ltd.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program. If not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include <linux/sched.h>
22 #include <linux/mm.h>
23 #include <linux/dma-mapping.h>
24 #include <linux/kvm_host.h>
25 #include <asm/fixmap.h>
26 #include <asm/thread_info.h>
27 #include <asm/memory.h>
28 #include <asm/smp_plat.h>
29 #include <asm/suspend.h>
30 #include <asm/vdso_datapage.h>
31 #include <linux/kbuild.h>
32
main(void)33 int main(void)
34 {
35 DEFINE(TSK_ACTIVE_MM, offsetof(struct task_struct, active_mm));
36 BLANK();
37 DEFINE(TI_FLAGS, offsetof(struct thread_info, flags));
38 DEFINE(TI_PREEMPT, offsetof(struct thread_info, preempt_count));
39 DEFINE(TI_ADDR_LIMIT, offsetof(struct thread_info, addr_limit));
40 DEFINE(TI_TASK, offsetof(struct thread_info, task));
41 DEFINE(TI_EXEC_DOMAIN, offsetof(struct thread_info, exec_domain));
42 DEFINE(TI_CPU, offsetof(struct thread_info, cpu));
43 #ifdef CONFIG_ARM64_SW_TTBR0_PAN
44 DEFINE(TSK_TI_TTBR0, offsetof(struct thread_info, ttbr0));
45 #endif
46 BLANK();
47 DEFINE(THREAD_CPU_CONTEXT, offsetof(struct task_struct, thread.cpu_context));
48 BLANK();
49 DEFINE(S_X0, offsetof(struct pt_regs, regs[0]));
50 DEFINE(S_X1, offsetof(struct pt_regs, regs[1]));
51 DEFINE(S_X2, offsetof(struct pt_regs, regs[2]));
52 DEFINE(S_X3, offsetof(struct pt_regs, regs[3]));
53 DEFINE(S_X4, offsetof(struct pt_regs, regs[4]));
54 DEFINE(S_X5, offsetof(struct pt_regs, regs[5]));
55 DEFINE(S_X6, offsetof(struct pt_regs, regs[6]));
56 DEFINE(S_X7, offsetof(struct pt_regs, regs[7]));
57 DEFINE(S_LR, offsetof(struct pt_regs, regs[30]));
58 DEFINE(S_SP, offsetof(struct pt_regs, sp));
59 #ifdef CONFIG_COMPAT
60 DEFINE(S_COMPAT_SP, offsetof(struct pt_regs, compat_sp));
61 #endif
62 DEFINE(S_PSTATE, offsetof(struct pt_regs, pstate));
63 DEFINE(S_PC, offsetof(struct pt_regs, pc));
64 DEFINE(S_ORIG_X0, offsetof(struct pt_regs, orig_x0));
65 DEFINE(S_SYSCALLNO, offsetof(struct pt_regs, syscallno));
66 DEFINE(S_ORIG_ADDR_LIMIT, offsetof(struct pt_regs, orig_addr_limit));
67 DEFINE(S_FRAME_SIZE, sizeof(struct pt_regs));
68 BLANK();
69 DEFINE(MM_CONTEXT_ID, offsetof(struct mm_struct, context.id.counter));
70 BLANK();
71 DEFINE(VMA_VM_MM, offsetof(struct vm_area_struct, vm_mm));
72 DEFINE(VMA_VM_FLAGS, offsetof(struct vm_area_struct, vm_flags));
73 BLANK();
74 DEFINE(VM_EXEC, VM_EXEC);
75 BLANK();
76 DEFINE(PAGE_SZ, PAGE_SIZE);
77 BLANK();
78 DEFINE(DMA_BIDIRECTIONAL, DMA_BIDIRECTIONAL);
79 DEFINE(DMA_TO_DEVICE, DMA_TO_DEVICE);
80 DEFINE(DMA_FROM_DEVICE, DMA_FROM_DEVICE);
81 BLANK();
82 DEFINE(CLOCK_REALTIME, CLOCK_REALTIME);
83 DEFINE(CLOCK_MONOTONIC, CLOCK_MONOTONIC);
84 DEFINE(CLOCK_MONOTONIC_RAW, CLOCK_MONOTONIC_RAW);
85 DEFINE(CLOCK_REALTIME_RES, MONOTONIC_RES_NSEC);
86 DEFINE(CLOCK_REALTIME_COARSE, CLOCK_REALTIME_COARSE);
87 DEFINE(CLOCK_MONOTONIC_COARSE,CLOCK_MONOTONIC_COARSE);
88 DEFINE(CLOCK_COARSE_RES, LOW_RES_NSEC);
89 DEFINE(NSEC_PER_SEC, NSEC_PER_SEC);
90 BLANK();
91 DEFINE(VDSO_CS_CYCLE_LAST, offsetof(struct vdso_data, cs_cycle_last));
92 DEFINE(VDSO_RAW_TIME_SEC, offsetof(struct vdso_data, raw_time_sec));
93 DEFINE(VDSO_RAW_TIME_NSEC, offsetof(struct vdso_data, raw_time_nsec));
94 DEFINE(VDSO_XTIME_CLK_SEC, offsetof(struct vdso_data, xtime_clock_sec));
95 DEFINE(VDSO_XTIME_CLK_NSEC, offsetof(struct vdso_data, xtime_clock_nsec));
96 DEFINE(VDSO_XTIME_CRS_SEC, offsetof(struct vdso_data, xtime_coarse_sec));
97 DEFINE(VDSO_XTIME_CRS_NSEC, offsetof(struct vdso_data, xtime_coarse_nsec));
98 DEFINE(VDSO_WTM_CLK_SEC, offsetof(struct vdso_data, wtm_clock_sec));
99 DEFINE(VDSO_WTM_CLK_NSEC, offsetof(struct vdso_data, wtm_clock_nsec));
100 DEFINE(VDSO_TB_SEQ_COUNT, offsetof(struct vdso_data, tb_seq_count));
101 DEFINE(VDSO_CS_MONO_MULT, offsetof(struct vdso_data, cs_mono_mult));
102 DEFINE(VDSO_CS_RAW_MULT, offsetof(struct vdso_data, cs_raw_mult));
103 DEFINE(VDSO_CS_SHIFT, offsetof(struct vdso_data, cs_shift));
104 DEFINE(VDSO_TZ_MINWEST, offsetof(struct vdso_data, tz_minuteswest));
105 DEFINE(VDSO_TZ_DSTTIME, offsetof(struct vdso_data, tz_dsttime));
106 DEFINE(VDSO_USE_SYSCALL, offsetof(struct vdso_data, use_syscall));
107 BLANK();
108 DEFINE(TVAL_TV_SEC, offsetof(struct timeval, tv_sec));
109 DEFINE(TVAL_TV_USEC, offsetof(struct timeval, tv_usec));
110 DEFINE(TSPEC_TV_SEC, offsetof(struct timespec, tv_sec));
111 DEFINE(TSPEC_TV_NSEC, offsetof(struct timespec, tv_nsec));
112 BLANK();
113 DEFINE(TZ_MINWEST, offsetof(struct timezone, tz_minuteswest));
114 DEFINE(TZ_DSTTIME, offsetof(struct timezone, tz_dsttime));
115 BLANK();
116 #ifdef CONFIG_KVM_ARM_HOST
117 DEFINE(VCPU_CONTEXT, offsetof(struct kvm_vcpu, arch.ctxt));
118 DEFINE(CPU_GP_REGS, offsetof(struct kvm_cpu_context, gp_regs));
119 DEFINE(CPU_USER_PT_REGS, offsetof(struct kvm_regs, regs));
120 DEFINE(CPU_FP_REGS, offsetof(struct kvm_regs, fp_regs));
121 DEFINE(CPU_SP_EL1, offsetof(struct kvm_regs, sp_el1));
122 DEFINE(CPU_ELR_EL1, offsetof(struct kvm_regs, elr_el1));
123 DEFINE(CPU_SPSR, offsetof(struct kvm_regs, spsr));
124 DEFINE(CPU_SYSREGS, offsetof(struct kvm_cpu_context, sys_regs));
125 DEFINE(VCPU_ESR_EL2, offsetof(struct kvm_vcpu, arch.fault.esr_el2));
126 DEFINE(VCPU_FAR_EL2, offsetof(struct kvm_vcpu, arch.fault.far_el2));
127 DEFINE(VCPU_HPFAR_EL2, offsetof(struct kvm_vcpu, arch.fault.hpfar_el2));
128 DEFINE(VCPU_DEBUG_FLAGS, offsetof(struct kvm_vcpu, arch.debug_flags));
129 DEFINE(VCPU_HCR_EL2, offsetof(struct kvm_vcpu, arch.hcr_el2));
130 DEFINE(VCPU_IRQ_LINES, offsetof(struct kvm_vcpu, arch.irq_lines));
131 DEFINE(VCPU_HOST_CONTEXT, offsetof(struct kvm_vcpu, arch.host_cpu_context));
132 DEFINE(VCPU_TIMER_CNTV_CTL, offsetof(struct kvm_vcpu, arch.timer_cpu.cntv_ctl));
133 DEFINE(VCPU_TIMER_CNTV_CVAL, offsetof(struct kvm_vcpu, arch.timer_cpu.cntv_cval));
134 DEFINE(KVM_TIMER_CNTVOFF, offsetof(struct kvm, arch.timer.cntvoff));
135 DEFINE(KVM_TIMER_ENABLED, offsetof(struct kvm, arch.timer.enabled));
136 DEFINE(VCPU_KVM, offsetof(struct kvm_vcpu, kvm));
137 DEFINE(VCPU_VGIC_CPU, offsetof(struct kvm_vcpu, arch.vgic_cpu));
138 DEFINE(VGIC_SAVE_FN, offsetof(struct vgic_sr_vectors, save_vgic));
139 DEFINE(VGIC_RESTORE_FN, offsetof(struct vgic_sr_vectors, restore_vgic));
140 DEFINE(VGIC_SR_VECTOR_SZ, sizeof(struct vgic_sr_vectors));
141 DEFINE(VGIC_V2_CPU_HCR, offsetof(struct vgic_cpu, vgic_v2.vgic_hcr));
142 DEFINE(VGIC_V2_CPU_VMCR, offsetof(struct vgic_cpu, vgic_v2.vgic_vmcr));
143 DEFINE(VGIC_V2_CPU_MISR, offsetof(struct vgic_cpu, vgic_v2.vgic_misr));
144 DEFINE(VGIC_V2_CPU_EISR, offsetof(struct vgic_cpu, vgic_v2.vgic_eisr));
145 DEFINE(VGIC_V2_CPU_ELRSR, offsetof(struct vgic_cpu, vgic_v2.vgic_elrsr));
146 DEFINE(VGIC_V2_CPU_APR, offsetof(struct vgic_cpu, vgic_v2.vgic_apr));
147 DEFINE(VGIC_V2_CPU_LR, offsetof(struct vgic_cpu, vgic_v2.vgic_lr));
148 DEFINE(VGIC_V3_CPU_HCR, offsetof(struct vgic_cpu, vgic_v3.vgic_hcr));
149 DEFINE(VGIC_V3_CPU_VMCR, offsetof(struct vgic_cpu, vgic_v3.vgic_vmcr));
150 DEFINE(VGIC_V3_CPU_MISR, offsetof(struct vgic_cpu, vgic_v3.vgic_misr));
151 DEFINE(VGIC_V3_CPU_EISR, offsetof(struct vgic_cpu, vgic_v3.vgic_eisr));
152 DEFINE(VGIC_V3_CPU_ELRSR, offsetof(struct vgic_cpu, vgic_v3.vgic_elrsr));
153 DEFINE(VGIC_V3_CPU_AP0R, offsetof(struct vgic_cpu, vgic_v3.vgic_ap0r));
154 DEFINE(VGIC_V3_CPU_AP1R, offsetof(struct vgic_cpu, vgic_v3.vgic_ap1r));
155 DEFINE(VGIC_V3_CPU_LR, offsetof(struct vgic_cpu, vgic_v3.vgic_lr));
156 DEFINE(VGIC_CPU_NR_LR, offsetof(struct vgic_cpu, nr_lr));
157 DEFINE(KVM_VTTBR, offsetof(struct kvm, arch.vttbr));
158 DEFINE(KVM_VGIC_VCTRL, offsetof(struct kvm, arch.vgic.vctrl_base));
159 #endif
160 #ifdef CONFIG_ARM64_CPU_SUSPEND
161 DEFINE(CPU_SUSPEND_SZ, sizeof(struct cpu_suspend_ctx));
162 DEFINE(CPU_CTX_SP, offsetof(struct cpu_suspend_ctx, sp));
163 DEFINE(MPIDR_HASH_MASK, offsetof(struct mpidr_hash, mask));
164 DEFINE(MPIDR_HASH_SHIFTS, offsetof(struct mpidr_hash, shift_aff));
165 DEFINE(SLEEP_SAVE_SP_SZ, sizeof(struct sleep_save_sp));
166 DEFINE(SLEEP_SAVE_SP_PHYS, offsetof(struct sleep_save_sp, save_ptr_stash_phys));
167 DEFINE(SLEEP_SAVE_SP_VIRT, offsetof(struct sleep_save_sp, save_ptr_stash));
168 #endif
169 BLANK();
170 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0
171 DEFINE(TRAMP_VALIAS, TRAMP_VALIAS);
172 #endif
173 return 0;
174 }
175