1 /*
2 * PMU support
3 *
4 * Copyright (C) 2012 ARM Limited
5 * Author: Will Deacon <will.deacon@arm.com>
6 *
7 * This code is based heavily on the ARMv7 perf event code.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
20 */
21 #define pr_fmt(fmt) "hw perfevents: " fmt
22
23 #include <linux/bitmap.h>
24 #include <linux/interrupt.h>
25 #include <linux/irq.h>
26 #include <linux/kernel.h>
27 #include <linux/export.h>
28 #include <linux/perf_event.h>
29 #include <linux/platform_device.h>
30 #include <linux/spinlock.h>
31 #include <linux/uaccess.h>
32
33 #include <asm/cputype.h>
34 #include <asm/irq.h>
35 #include <asm/irq_regs.h>
36 #include <asm/pmu.h>
37 #include <asm/stacktrace.h>
38
39 /*
40 * ARMv8 supports a maximum of 32 events.
41 * The cycle counter is included in this total.
42 */
43 #define ARMPMU_MAX_HWEVENTS 32
44
45 static DEFINE_PER_CPU(struct perf_event * [ARMPMU_MAX_HWEVENTS], hw_events);
46 static DEFINE_PER_CPU(unsigned long [BITS_TO_LONGS(ARMPMU_MAX_HWEVENTS)], used_mask);
47 static DEFINE_PER_CPU(struct pmu_hw_events, cpu_hw_events);
48
49 #define to_arm_pmu(p) (container_of(p, struct arm_pmu, pmu))
50
51 /* Set at runtime when we know what CPU type we are. */
52 static struct arm_pmu *cpu_pmu;
53
54 int
armpmu_get_max_events(void)55 armpmu_get_max_events(void)
56 {
57 int max_events = 0;
58
59 if (cpu_pmu != NULL)
60 max_events = cpu_pmu->num_events;
61
62 return max_events;
63 }
64 EXPORT_SYMBOL_GPL(armpmu_get_max_events);
65
perf_num_counters(void)66 int perf_num_counters(void)
67 {
68 return armpmu_get_max_events();
69 }
70 EXPORT_SYMBOL_GPL(perf_num_counters);
71
72 #define HW_OP_UNSUPPORTED 0xFFFF
73
74 #define C(_x) \
75 PERF_COUNT_HW_CACHE_##_x
76
77 #define CACHE_OP_UNSUPPORTED 0xFFFF
78
79 static int
armpmu_map_cache_event(const unsigned (* cache_map)[PERF_COUNT_HW_CACHE_MAX][PERF_COUNT_HW_CACHE_OP_MAX][PERF_COUNT_HW_CACHE_RESULT_MAX],u64 config)80 armpmu_map_cache_event(const unsigned (*cache_map)
81 [PERF_COUNT_HW_CACHE_MAX]
82 [PERF_COUNT_HW_CACHE_OP_MAX]
83 [PERF_COUNT_HW_CACHE_RESULT_MAX],
84 u64 config)
85 {
86 unsigned int cache_type, cache_op, cache_result, ret;
87
88 cache_type = (config >> 0) & 0xff;
89 if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
90 return -EINVAL;
91
92 cache_op = (config >> 8) & 0xff;
93 if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
94 return -EINVAL;
95
96 cache_result = (config >> 16) & 0xff;
97 if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
98 return -EINVAL;
99
100 ret = (int)(*cache_map)[cache_type][cache_op][cache_result];
101
102 if (ret == CACHE_OP_UNSUPPORTED)
103 return -ENOENT;
104
105 return ret;
106 }
107
108 static int
armpmu_map_event(const unsigned (* event_map)[PERF_COUNT_HW_MAX],u64 config)109 armpmu_map_event(const unsigned (*event_map)[PERF_COUNT_HW_MAX], u64 config)
110 {
111 int mapping;
112
113 if (config >= PERF_COUNT_HW_MAX)
114 return -EINVAL;
115
116 mapping = (*event_map)[config];
117 return mapping == HW_OP_UNSUPPORTED ? -ENOENT : mapping;
118 }
119
120 static int
armpmu_map_raw_event(u32 raw_event_mask,u64 config)121 armpmu_map_raw_event(u32 raw_event_mask, u64 config)
122 {
123 return (int)(config & raw_event_mask);
124 }
125
map_cpu_event(struct perf_event * event,const unsigned (* event_map)[PERF_COUNT_HW_MAX],const unsigned (* cache_map)[PERF_COUNT_HW_CACHE_MAX][PERF_COUNT_HW_CACHE_OP_MAX][PERF_COUNT_HW_CACHE_RESULT_MAX],u32 raw_event_mask)126 static int map_cpu_event(struct perf_event *event,
127 const unsigned (*event_map)[PERF_COUNT_HW_MAX],
128 const unsigned (*cache_map)
129 [PERF_COUNT_HW_CACHE_MAX]
130 [PERF_COUNT_HW_CACHE_OP_MAX]
131 [PERF_COUNT_HW_CACHE_RESULT_MAX],
132 u32 raw_event_mask)
133 {
134 u64 config = event->attr.config;
135
136 switch (event->attr.type) {
137 case PERF_TYPE_HARDWARE:
138 return armpmu_map_event(event_map, config);
139 case PERF_TYPE_HW_CACHE:
140 return armpmu_map_cache_event(cache_map, config);
141 case PERF_TYPE_RAW:
142 return armpmu_map_raw_event(raw_event_mask, config);
143 }
144
145 return -ENOENT;
146 }
147
148 int
armpmu_event_set_period(struct perf_event * event,struct hw_perf_event * hwc,int idx)149 armpmu_event_set_period(struct perf_event *event,
150 struct hw_perf_event *hwc,
151 int idx)
152 {
153 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
154 s64 left = local64_read(&hwc->period_left);
155 s64 period = hwc->sample_period;
156 int ret = 0;
157
158 if (unlikely(left <= -period)) {
159 left = period;
160 local64_set(&hwc->period_left, left);
161 hwc->last_period = period;
162 ret = 1;
163 }
164
165 if (unlikely(left <= 0)) {
166 left += period;
167 local64_set(&hwc->period_left, left);
168 hwc->last_period = period;
169 ret = 1;
170 }
171
172 if (left > (s64)armpmu->max_period)
173 left = armpmu->max_period;
174
175 local64_set(&hwc->prev_count, (u64)-left);
176
177 armpmu->write_counter(idx, (u64)(-left) & 0xffffffff);
178
179 perf_event_update_userpage(event);
180
181 return ret;
182 }
183
184 u64
armpmu_event_update(struct perf_event * event,struct hw_perf_event * hwc,int idx)185 armpmu_event_update(struct perf_event *event,
186 struct hw_perf_event *hwc,
187 int idx)
188 {
189 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
190 u64 delta, prev_raw_count, new_raw_count;
191
192 again:
193 prev_raw_count = local64_read(&hwc->prev_count);
194 new_raw_count = armpmu->read_counter(idx);
195
196 if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
197 new_raw_count) != prev_raw_count)
198 goto again;
199
200 delta = (new_raw_count - prev_raw_count) & armpmu->max_period;
201
202 local64_add(delta, &event->count);
203 local64_sub(delta, &hwc->period_left);
204
205 return new_raw_count;
206 }
207
208 static void
armpmu_read(struct perf_event * event)209 armpmu_read(struct perf_event *event)
210 {
211 struct hw_perf_event *hwc = &event->hw;
212
213 /* Don't read disabled counters! */
214 if (hwc->idx < 0)
215 return;
216
217 armpmu_event_update(event, hwc, hwc->idx);
218 }
219
220 static void
armpmu_stop(struct perf_event * event,int flags)221 armpmu_stop(struct perf_event *event, int flags)
222 {
223 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
224 struct hw_perf_event *hwc = &event->hw;
225
226 /*
227 * ARM pmu always has to update the counter, so ignore
228 * PERF_EF_UPDATE, see comments in armpmu_start().
229 */
230 if (!(hwc->state & PERF_HES_STOPPED)) {
231 armpmu->disable(hwc, hwc->idx);
232 barrier(); /* why? */
233 armpmu_event_update(event, hwc, hwc->idx);
234 hwc->state |= PERF_HES_STOPPED | PERF_HES_UPTODATE;
235 }
236 }
237
238 static void
armpmu_start(struct perf_event * event,int flags)239 armpmu_start(struct perf_event *event, int flags)
240 {
241 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
242 struct hw_perf_event *hwc = &event->hw;
243
244 /*
245 * ARM pmu always has to reprogram the period, so ignore
246 * PERF_EF_RELOAD, see the comment below.
247 */
248 if (flags & PERF_EF_RELOAD)
249 WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE));
250
251 hwc->state = 0;
252 /*
253 * Set the period again. Some counters can't be stopped, so when we
254 * were stopped we simply disabled the IRQ source and the counter
255 * may have been left counting. If we don't do this step then we may
256 * get an interrupt too soon or *way* too late if the overflow has
257 * happened since disabling.
258 */
259 armpmu_event_set_period(event, hwc, hwc->idx);
260 armpmu->enable(hwc, hwc->idx);
261 }
262
263 static void
armpmu_del(struct perf_event * event,int flags)264 armpmu_del(struct perf_event *event, int flags)
265 {
266 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
267 struct pmu_hw_events *hw_events = armpmu->get_hw_events();
268 struct hw_perf_event *hwc = &event->hw;
269 int idx = hwc->idx;
270
271 WARN_ON(idx < 0);
272
273 armpmu_stop(event, PERF_EF_UPDATE);
274 hw_events->events[idx] = NULL;
275 clear_bit(idx, hw_events->used_mask);
276
277 perf_event_update_userpage(event);
278 }
279
280 static int
armpmu_add(struct perf_event * event,int flags)281 armpmu_add(struct perf_event *event, int flags)
282 {
283 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
284 struct pmu_hw_events *hw_events = armpmu->get_hw_events();
285 struct hw_perf_event *hwc = &event->hw;
286 int idx;
287 int err = 0;
288
289 perf_pmu_disable(event->pmu);
290
291 /* If we don't have a space for the counter then finish early. */
292 idx = armpmu->get_event_idx(hw_events, hwc);
293 if (idx < 0) {
294 err = idx;
295 goto out;
296 }
297
298 /*
299 * If there is an event in the counter we are going to use then make
300 * sure it is disabled.
301 */
302 event->hw.idx = idx;
303 armpmu->disable(hwc, idx);
304 hw_events->events[idx] = event;
305
306 hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE;
307 if (flags & PERF_EF_START)
308 armpmu_start(event, PERF_EF_RELOAD);
309
310 /* Propagate our changes to the userspace mapping. */
311 perf_event_update_userpage(event);
312
313 out:
314 perf_pmu_enable(event->pmu);
315 return err;
316 }
317
318 static int
validate_event(struct pmu * pmu,struct pmu_hw_events * hw_events,struct perf_event * event)319 validate_event(struct pmu *pmu, struct pmu_hw_events *hw_events,
320 struct perf_event *event)
321 {
322 struct arm_pmu *armpmu;
323 struct hw_perf_event fake_event = event->hw;
324 struct pmu *leader_pmu = event->group_leader->pmu;
325
326 if (is_software_event(event))
327 return 1;
328
329 /*
330 * Reject groups spanning multiple HW PMUs (e.g. CPU + CCI). The
331 * core perf code won't check that the pmu->ctx == leader->ctx
332 * until after pmu->event_init(event).
333 */
334 if (event->pmu != pmu)
335 return 0;
336
337 if (event->pmu != leader_pmu || event->state < PERF_EVENT_STATE_OFF)
338 return 1;
339
340 if (event->state == PERF_EVENT_STATE_OFF && !event->attr.enable_on_exec)
341 return 1;
342
343 armpmu = to_arm_pmu(event->pmu);
344 return armpmu->get_event_idx(hw_events, &fake_event) >= 0;
345 }
346
347 static int
validate_group(struct perf_event * event)348 validate_group(struct perf_event *event)
349 {
350 struct perf_event *sibling, *leader = event->group_leader;
351 struct pmu_hw_events fake_pmu;
352 DECLARE_BITMAP(fake_used_mask, ARMPMU_MAX_HWEVENTS);
353
354 /*
355 * Initialise the fake PMU. We only need to populate the
356 * used_mask for the purposes of validation.
357 */
358 memset(fake_used_mask, 0, sizeof(fake_used_mask));
359 fake_pmu.used_mask = fake_used_mask;
360
361 if (!validate_event(event->pmu, &fake_pmu, leader))
362 return -EINVAL;
363
364 list_for_each_entry(sibling, &leader->sibling_list, group_entry) {
365 if (!validate_event(event->pmu, &fake_pmu, sibling))
366 return -EINVAL;
367 }
368
369 if (!validate_event(event->pmu, &fake_pmu, event))
370 return -EINVAL;
371
372 return 0;
373 }
374
375 static void
armpmu_disable_percpu_irq(void * data)376 armpmu_disable_percpu_irq(void *data)
377 {
378 unsigned int irq = *(unsigned int *)data;
379 disable_percpu_irq(irq);
380 }
381
382 static void
armpmu_release_hardware(struct arm_pmu * armpmu)383 armpmu_release_hardware(struct arm_pmu *armpmu)
384 {
385 int irq;
386 unsigned int i, irqs;
387 struct platform_device *pmu_device = armpmu->plat_device;
388
389 irqs = min(pmu_device->num_resources, num_possible_cpus());
390 if (!irqs)
391 return;
392
393 irq = platform_get_irq(pmu_device, 0);
394 if (irq <= 0)
395 return;
396
397 if (irq_is_percpu(irq)) {
398 on_each_cpu(armpmu_disable_percpu_irq, &irq, 1);
399 free_percpu_irq(irq, &cpu_hw_events);
400 } else {
401 for (i = 0; i < irqs; ++i) {
402 if (!cpumask_test_and_clear_cpu(i, &armpmu->active_irqs))
403 continue;
404 irq = platform_get_irq(pmu_device, i);
405 if (irq > 0)
406 free_irq(irq, armpmu);
407 }
408 }
409 }
410
411 static void
armpmu_enable_percpu_irq(void * data)412 armpmu_enable_percpu_irq(void *data)
413 {
414 unsigned int irq = *(unsigned int *)data;
415 enable_percpu_irq(irq, IRQ_TYPE_NONE);
416 }
417
418 static int
armpmu_reserve_hardware(struct arm_pmu * armpmu)419 armpmu_reserve_hardware(struct arm_pmu *armpmu)
420 {
421 int err, irq;
422 unsigned int i, irqs;
423 struct platform_device *pmu_device = armpmu->plat_device;
424
425 if (!pmu_device) {
426 pr_err("no PMU device registered\n");
427 return -ENODEV;
428 }
429
430 irqs = min(pmu_device->num_resources, num_possible_cpus());
431 if (!irqs) {
432 pr_err("no irqs for PMUs defined\n");
433 return -ENODEV;
434 }
435
436 irq = platform_get_irq(pmu_device, 0);
437 if (irq <= 0) {
438 pr_err("failed to get valid irq for PMU device\n");
439 return -ENODEV;
440 }
441
442 if (irq_is_percpu(irq)) {
443 err = request_percpu_irq(irq, armpmu->handle_irq,
444 "arm-pmu", &cpu_hw_events);
445
446 if (err) {
447 pr_err("unable to request percpu IRQ%d for ARM PMU counters\n",
448 irq);
449 armpmu_release_hardware(armpmu);
450 return err;
451 }
452
453 on_each_cpu(armpmu_enable_percpu_irq, &irq, 1);
454 } else {
455 for (i = 0; i < irqs; ++i) {
456 err = 0;
457 irq = platform_get_irq(pmu_device, i);
458 if (irq <= 0)
459 continue;
460
461 /*
462 * If we have a single PMU interrupt that we can't shift,
463 * assume that we're running on a uniprocessor machine and
464 * continue. Otherwise, continue without this interrupt.
465 */
466 if (irq_set_affinity(irq, cpumask_of(i)) && irqs > 1) {
467 pr_warning("unable to set irq affinity (irq=%d, cpu=%u)\n",
468 irq, i);
469 continue;
470 }
471
472 err = request_irq(irq, armpmu->handle_irq,
473 IRQF_NOBALANCING,
474 "arm-pmu", armpmu);
475 if (err) {
476 pr_err("unable to request IRQ%d for ARM PMU counters\n",
477 irq);
478 armpmu_release_hardware(armpmu);
479 return err;
480 }
481
482 cpumask_set_cpu(i, &armpmu->active_irqs);
483 }
484 }
485
486 return 0;
487 }
488
489 static void
hw_perf_event_destroy(struct perf_event * event)490 hw_perf_event_destroy(struct perf_event *event)
491 {
492 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
493 atomic_t *active_events = &armpmu->active_events;
494 struct mutex *pmu_reserve_mutex = &armpmu->reserve_mutex;
495
496 if (atomic_dec_and_mutex_lock(active_events, pmu_reserve_mutex)) {
497 armpmu_release_hardware(armpmu);
498 mutex_unlock(pmu_reserve_mutex);
499 }
500 }
501
502 static int
event_requires_mode_exclusion(struct perf_event_attr * attr)503 event_requires_mode_exclusion(struct perf_event_attr *attr)
504 {
505 return attr->exclude_idle || attr->exclude_user ||
506 attr->exclude_kernel || attr->exclude_hv;
507 }
508
509 static int
__hw_perf_event_init(struct perf_event * event)510 __hw_perf_event_init(struct perf_event *event)
511 {
512 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
513 struct hw_perf_event *hwc = &event->hw;
514 int mapping, err;
515
516 mapping = armpmu->map_event(event);
517
518 if (mapping < 0) {
519 pr_debug("event %x:%llx not supported\n", event->attr.type,
520 event->attr.config);
521 return mapping;
522 }
523
524 /*
525 * We don't assign an index until we actually place the event onto
526 * hardware. Use -1 to signify that we haven't decided where to put it
527 * yet. For SMP systems, each core has it's own PMU so we can't do any
528 * clever allocation or constraints checking at this point.
529 */
530 hwc->idx = -1;
531 hwc->config_base = 0;
532 hwc->config = 0;
533 hwc->event_base = 0;
534
535 /*
536 * Check whether we need to exclude the counter from certain modes.
537 */
538 if ((!armpmu->set_event_filter ||
539 armpmu->set_event_filter(hwc, &event->attr)) &&
540 event_requires_mode_exclusion(&event->attr)) {
541 pr_debug("ARM performance counters do not support mode exclusion\n");
542 return -EPERM;
543 }
544
545 /*
546 * Store the event encoding into the config_base field.
547 */
548 hwc->config_base |= (unsigned long)mapping;
549
550 if (!hwc->sample_period) {
551 /*
552 * For non-sampling runs, limit the sample_period to half
553 * of the counter width. That way, the new counter value
554 * is far less likely to overtake the previous one unless
555 * you have some serious IRQ latency issues.
556 */
557 hwc->sample_period = armpmu->max_period >> 1;
558 hwc->last_period = hwc->sample_period;
559 local64_set(&hwc->period_left, hwc->sample_period);
560 }
561
562 err = 0;
563 if (event->group_leader != event) {
564 err = validate_group(event);
565 if (err)
566 return -EINVAL;
567 }
568
569 return err;
570 }
571
armpmu_event_init(struct perf_event * event)572 static int armpmu_event_init(struct perf_event *event)
573 {
574 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
575 int err = 0;
576 atomic_t *active_events = &armpmu->active_events;
577
578 if (armpmu->map_event(event) == -ENOENT)
579 return -ENOENT;
580
581 event->destroy = hw_perf_event_destroy;
582
583 if (!atomic_inc_not_zero(active_events)) {
584 mutex_lock(&armpmu->reserve_mutex);
585 if (atomic_read(active_events) == 0)
586 err = armpmu_reserve_hardware(armpmu);
587
588 if (!err)
589 atomic_inc(active_events);
590 mutex_unlock(&armpmu->reserve_mutex);
591 }
592
593 if (err)
594 return err;
595
596 err = __hw_perf_event_init(event);
597 if (err)
598 hw_perf_event_destroy(event);
599
600 return err;
601 }
602
armpmu_enable(struct pmu * pmu)603 static void armpmu_enable(struct pmu *pmu)
604 {
605 struct arm_pmu *armpmu = to_arm_pmu(pmu);
606 struct pmu_hw_events *hw_events = armpmu->get_hw_events();
607 int enabled = bitmap_weight(hw_events->used_mask, armpmu->num_events);
608
609 if (enabled)
610 armpmu->start();
611 }
612
armpmu_disable(struct pmu * pmu)613 static void armpmu_disable(struct pmu *pmu)
614 {
615 struct arm_pmu *armpmu = to_arm_pmu(pmu);
616 armpmu->stop();
617 }
618
armpmu_init(struct arm_pmu * armpmu)619 static void __init armpmu_init(struct arm_pmu *armpmu)
620 {
621 atomic_set(&armpmu->active_events, 0);
622 mutex_init(&armpmu->reserve_mutex);
623
624 armpmu->pmu = (struct pmu) {
625 .pmu_enable = armpmu_enable,
626 .pmu_disable = armpmu_disable,
627 .event_init = armpmu_event_init,
628 .add = armpmu_add,
629 .del = armpmu_del,
630 .start = armpmu_start,
631 .stop = armpmu_stop,
632 .read = armpmu_read,
633 };
634 }
635
armpmu_register(struct arm_pmu * armpmu,char * name,int type)636 int __init armpmu_register(struct arm_pmu *armpmu, char *name, int type)
637 {
638 armpmu_init(armpmu);
639 return perf_pmu_register(&armpmu->pmu, name, type);
640 }
641
642 /*
643 * ARMv8 PMUv3 Performance Events handling code.
644 * Common event types.
645 */
646 enum armv8_pmuv3_perf_types {
647 /* Required events. */
648 ARMV8_PMUV3_PERFCTR_PMNC_SW_INCR = 0x00,
649 ARMV8_PMUV3_PERFCTR_L1_DCACHE_REFILL = 0x03,
650 ARMV8_PMUV3_PERFCTR_L1_DCACHE_ACCESS = 0x04,
651 ARMV8_PMUV3_PERFCTR_PC_BRANCH_MIS_PRED = 0x10,
652 ARMV8_PMUV3_PERFCTR_CLOCK_CYCLES = 0x11,
653 ARMV8_PMUV3_PERFCTR_PC_BRANCH_PRED = 0x12,
654
655 /* At least one of the following is required. */
656 ARMV8_PMUV3_PERFCTR_INSTR_EXECUTED = 0x08,
657 ARMV8_PMUV3_PERFCTR_OP_SPEC = 0x1B,
658
659 /* Common architectural events. */
660 ARMV8_PMUV3_PERFCTR_MEM_READ = 0x06,
661 ARMV8_PMUV3_PERFCTR_MEM_WRITE = 0x07,
662 ARMV8_PMUV3_PERFCTR_EXC_TAKEN = 0x09,
663 ARMV8_PMUV3_PERFCTR_EXC_EXECUTED = 0x0A,
664 ARMV8_PMUV3_PERFCTR_CID_WRITE = 0x0B,
665 ARMV8_PMUV3_PERFCTR_PC_WRITE = 0x0C,
666 ARMV8_PMUV3_PERFCTR_PC_IMM_BRANCH = 0x0D,
667 ARMV8_PMUV3_PERFCTR_PC_PROC_RETURN = 0x0E,
668 ARMV8_PMUV3_PERFCTR_MEM_UNALIGNED_ACCESS = 0x0F,
669 ARMV8_PMUV3_PERFCTR_TTBR_WRITE = 0x1C,
670
671 /* Common microarchitectural events. */
672 ARMV8_PMUV3_PERFCTR_L1_ICACHE_REFILL = 0x01,
673 ARMV8_PMUV3_PERFCTR_ITLB_REFILL = 0x02,
674 ARMV8_PMUV3_PERFCTR_DTLB_REFILL = 0x05,
675 ARMV8_PMUV3_PERFCTR_MEM_ACCESS = 0x13,
676 ARMV8_PMUV3_PERFCTR_L1_ICACHE_ACCESS = 0x14,
677 ARMV8_PMUV3_PERFCTR_L1_DCACHE_WB = 0x15,
678 ARMV8_PMUV3_PERFCTR_L2_CACHE_ACCESS = 0x16,
679 ARMV8_PMUV3_PERFCTR_L2_CACHE_REFILL = 0x17,
680 ARMV8_PMUV3_PERFCTR_L2_CACHE_WB = 0x18,
681 ARMV8_PMUV3_PERFCTR_BUS_ACCESS = 0x19,
682 ARMV8_PMUV3_PERFCTR_MEM_ERROR = 0x1A,
683 ARMV8_PMUV3_PERFCTR_BUS_CYCLES = 0x1D,
684 };
685
686 /* PMUv3 HW events mapping. */
687 static const unsigned armv8_pmuv3_perf_map[PERF_COUNT_HW_MAX] = {
688 [PERF_COUNT_HW_CPU_CYCLES] = ARMV8_PMUV3_PERFCTR_CLOCK_CYCLES,
689 [PERF_COUNT_HW_INSTRUCTIONS] = ARMV8_PMUV3_PERFCTR_INSTR_EXECUTED,
690 [PERF_COUNT_HW_CACHE_REFERENCES] = ARMV8_PMUV3_PERFCTR_L1_DCACHE_ACCESS,
691 [PERF_COUNT_HW_CACHE_MISSES] = ARMV8_PMUV3_PERFCTR_L1_DCACHE_REFILL,
692 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = HW_OP_UNSUPPORTED,
693 [PERF_COUNT_HW_BRANCH_MISSES] = ARMV8_PMUV3_PERFCTR_PC_BRANCH_MIS_PRED,
694 [PERF_COUNT_HW_BUS_CYCLES] = HW_OP_UNSUPPORTED,
695 [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = HW_OP_UNSUPPORTED,
696 [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = HW_OP_UNSUPPORTED,
697 };
698
699 static const unsigned armv8_pmuv3_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
700 [PERF_COUNT_HW_CACHE_OP_MAX]
701 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
702 [C(L1D)] = {
703 [C(OP_READ)] = {
704 [C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1_DCACHE_ACCESS,
705 [C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1_DCACHE_REFILL,
706 },
707 [C(OP_WRITE)] = {
708 [C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1_DCACHE_ACCESS,
709 [C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1_DCACHE_REFILL,
710 },
711 [C(OP_PREFETCH)] = {
712 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
713 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
714 },
715 },
716 [C(L1I)] = {
717 [C(OP_READ)] = {
718 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
719 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
720 },
721 [C(OP_WRITE)] = {
722 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
723 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
724 },
725 [C(OP_PREFETCH)] = {
726 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
727 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
728 },
729 },
730 [C(LL)] = {
731 [C(OP_READ)] = {
732 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
733 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
734 },
735 [C(OP_WRITE)] = {
736 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
737 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
738 },
739 [C(OP_PREFETCH)] = {
740 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
741 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
742 },
743 },
744 [C(DTLB)] = {
745 [C(OP_READ)] = {
746 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
747 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
748 },
749 [C(OP_WRITE)] = {
750 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
751 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
752 },
753 [C(OP_PREFETCH)] = {
754 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
755 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
756 },
757 },
758 [C(ITLB)] = {
759 [C(OP_READ)] = {
760 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
761 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
762 },
763 [C(OP_WRITE)] = {
764 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
765 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
766 },
767 [C(OP_PREFETCH)] = {
768 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
769 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
770 },
771 },
772 [C(BPU)] = {
773 [C(OP_READ)] = {
774 [C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_PC_BRANCH_PRED,
775 [C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_PC_BRANCH_MIS_PRED,
776 },
777 [C(OP_WRITE)] = {
778 [C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_PC_BRANCH_PRED,
779 [C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_PC_BRANCH_MIS_PRED,
780 },
781 [C(OP_PREFETCH)] = {
782 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
783 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
784 },
785 },
786 [C(NODE)] = {
787 [C(OP_READ)] = {
788 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
789 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
790 },
791 [C(OP_WRITE)] = {
792 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
793 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
794 },
795 [C(OP_PREFETCH)] = {
796 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
797 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
798 },
799 },
800 };
801
802 /*
803 * Perf Events' indices
804 */
805 #define ARMV8_IDX_CYCLE_COUNTER 0
806 #define ARMV8_IDX_COUNTER0 1
807 #define ARMV8_IDX_COUNTER_LAST (ARMV8_IDX_CYCLE_COUNTER + cpu_pmu->num_events - 1)
808
809 #define ARMV8_MAX_COUNTERS 32
810 #define ARMV8_COUNTER_MASK (ARMV8_MAX_COUNTERS - 1)
811
812 /*
813 * ARMv8 low level PMU access
814 */
815
816 /*
817 * Perf Event to low level counters mapping
818 */
819 #define ARMV8_IDX_TO_COUNTER(x) \
820 (((x) - ARMV8_IDX_COUNTER0) & ARMV8_COUNTER_MASK)
821
822 /*
823 * Per-CPU PMCR: config reg
824 */
825 #define ARMV8_PMCR_E (1 << 0) /* Enable all counters */
826 #define ARMV8_PMCR_P (1 << 1) /* Reset all counters */
827 #define ARMV8_PMCR_C (1 << 2) /* Cycle counter reset */
828 #define ARMV8_PMCR_D (1 << 3) /* CCNT counts every 64th cpu cycle */
829 #define ARMV8_PMCR_X (1 << 4) /* Export to ETM */
830 #define ARMV8_PMCR_DP (1 << 5) /* Disable CCNT if non-invasive debug*/
831 #define ARMV8_PMCR_N_SHIFT 11 /* Number of counters supported */
832 #define ARMV8_PMCR_N_MASK 0x1f
833 #define ARMV8_PMCR_MASK 0x3f /* Mask for writable bits */
834
835 /*
836 * PMOVSR: counters overflow flag status reg
837 */
838 #define ARMV8_OVSR_MASK 0xffffffff /* Mask for writable bits */
839 #define ARMV8_OVERFLOWED_MASK ARMV8_OVSR_MASK
840
841 /*
842 * PMXEVTYPER: Event selection reg
843 */
844 #define ARMV8_EVTYPE_MASK 0xc80003ff /* Mask for writable bits */
845 #define ARMV8_EVTYPE_EVENT 0x3ff /* Mask for EVENT bits */
846
847 /*
848 * Event filters for PMUv3
849 */
850 #define ARMV8_EXCLUDE_EL1 (1 << 31)
851 #define ARMV8_EXCLUDE_EL0 (1 << 30)
852 #define ARMV8_INCLUDE_EL2 (1 << 27)
853
armv8pmu_pmcr_read(void)854 static inline u32 armv8pmu_pmcr_read(void)
855 {
856 u32 val;
857 asm volatile("mrs %0, pmcr_el0" : "=r" (val));
858 return val;
859 }
860
armv8pmu_pmcr_write(u32 val)861 static inline void armv8pmu_pmcr_write(u32 val)
862 {
863 val &= ARMV8_PMCR_MASK;
864 isb();
865 asm volatile("msr pmcr_el0, %0" :: "r" (val));
866 }
867
armv8pmu_has_overflowed(u32 pmovsr)868 static inline int armv8pmu_has_overflowed(u32 pmovsr)
869 {
870 return pmovsr & ARMV8_OVERFLOWED_MASK;
871 }
872
armv8pmu_counter_valid(int idx)873 static inline int armv8pmu_counter_valid(int idx)
874 {
875 return idx >= ARMV8_IDX_CYCLE_COUNTER && idx <= ARMV8_IDX_COUNTER_LAST;
876 }
877
armv8pmu_counter_has_overflowed(u32 pmnc,int idx)878 static inline int armv8pmu_counter_has_overflowed(u32 pmnc, int idx)
879 {
880 int ret = 0;
881 u32 counter;
882
883 if (!armv8pmu_counter_valid(idx)) {
884 pr_err("CPU%u checking wrong counter %d overflow status\n",
885 smp_processor_id(), idx);
886 } else {
887 counter = ARMV8_IDX_TO_COUNTER(idx);
888 ret = pmnc & BIT(counter);
889 }
890
891 return ret;
892 }
893
armv8pmu_select_counter(int idx)894 static inline int armv8pmu_select_counter(int idx)
895 {
896 u32 counter;
897
898 if (!armv8pmu_counter_valid(idx)) {
899 pr_err("CPU%u selecting wrong PMNC counter %d\n",
900 smp_processor_id(), idx);
901 return -EINVAL;
902 }
903
904 counter = ARMV8_IDX_TO_COUNTER(idx);
905 asm volatile("msr pmselr_el0, %0" :: "r" (counter));
906 isb();
907
908 return idx;
909 }
910
armv8pmu_read_counter(int idx)911 static inline u32 armv8pmu_read_counter(int idx)
912 {
913 u32 value = 0;
914
915 if (!armv8pmu_counter_valid(idx))
916 pr_err("CPU%u reading wrong counter %d\n",
917 smp_processor_id(), idx);
918 else if (idx == ARMV8_IDX_CYCLE_COUNTER)
919 asm volatile("mrs %0, pmccntr_el0" : "=r" (value));
920 else if (armv8pmu_select_counter(idx) == idx)
921 asm volatile("mrs %0, pmxevcntr_el0" : "=r" (value));
922
923 return value;
924 }
925
armv8pmu_write_counter(int idx,u32 value)926 static inline void armv8pmu_write_counter(int idx, u32 value)
927 {
928 if (!armv8pmu_counter_valid(idx))
929 pr_err("CPU%u writing wrong counter %d\n",
930 smp_processor_id(), idx);
931 else if (idx == ARMV8_IDX_CYCLE_COUNTER)
932 asm volatile("msr pmccntr_el0, %0" :: "r" (value));
933 else if (armv8pmu_select_counter(idx) == idx)
934 asm volatile("msr pmxevcntr_el0, %0" :: "r" (value));
935 }
936
armv8pmu_write_evtype(int idx,u32 val)937 static inline void armv8pmu_write_evtype(int idx, u32 val)
938 {
939 if (armv8pmu_select_counter(idx) == idx) {
940 val &= ARMV8_EVTYPE_MASK;
941 asm volatile("msr pmxevtyper_el0, %0" :: "r" (val));
942 }
943 }
944
armv8pmu_enable_counter(int idx)945 static inline int armv8pmu_enable_counter(int idx)
946 {
947 u32 counter;
948
949 if (!armv8pmu_counter_valid(idx)) {
950 pr_err("CPU%u enabling wrong PMNC counter %d\n",
951 smp_processor_id(), idx);
952 return -EINVAL;
953 }
954
955 counter = ARMV8_IDX_TO_COUNTER(idx);
956 asm volatile("msr pmcntenset_el0, %0" :: "r" (BIT(counter)));
957 return idx;
958 }
959
armv8pmu_disable_counter(int idx)960 static inline int armv8pmu_disable_counter(int idx)
961 {
962 u32 counter;
963
964 if (!armv8pmu_counter_valid(idx)) {
965 pr_err("CPU%u disabling wrong PMNC counter %d\n",
966 smp_processor_id(), idx);
967 return -EINVAL;
968 }
969
970 counter = ARMV8_IDX_TO_COUNTER(idx);
971 asm volatile("msr pmcntenclr_el0, %0" :: "r" (BIT(counter)));
972 return idx;
973 }
974
armv8pmu_enable_intens(int idx)975 static inline int armv8pmu_enable_intens(int idx)
976 {
977 u32 counter;
978
979 if (!armv8pmu_counter_valid(idx)) {
980 pr_err("CPU%u enabling wrong PMNC counter IRQ enable %d\n",
981 smp_processor_id(), idx);
982 return -EINVAL;
983 }
984
985 counter = ARMV8_IDX_TO_COUNTER(idx);
986 asm volatile("msr pmintenset_el1, %0" :: "r" (BIT(counter)));
987 return idx;
988 }
989
armv8pmu_disable_intens(int idx)990 static inline int armv8pmu_disable_intens(int idx)
991 {
992 u32 counter;
993
994 if (!armv8pmu_counter_valid(idx)) {
995 pr_err("CPU%u disabling wrong PMNC counter IRQ enable %d\n",
996 smp_processor_id(), idx);
997 return -EINVAL;
998 }
999
1000 counter = ARMV8_IDX_TO_COUNTER(idx);
1001 asm volatile("msr pmintenclr_el1, %0" :: "r" (BIT(counter)));
1002 isb();
1003 /* Clear the overflow flag in case an interrupt is pending. */
1004 asm volatile("msr pmovsclr_el0, %0" :: "r" (BIT(counter)));
1005 isb();
1006 return idx;
1007 }
1008
armv8pmu_getreset_flags(void)1009 static inline u32 armv8pmu_getreset_flags(void)
1010 {
1011 u32 value;
1012
1013 /* Read */
1014 asm volatile("mrs %0, pmovsclr_el0" : "=r" (value));
1015
1016 /* Write to clear flags */
1017 value &= ARMV8_OVSR_MASK;
1018 asm volatile("msr pmovsclr_el0, %0" :: "r" (value));
1019
1020 return value;
1021 }
1022
armv8pmu_enable_event(struct hw_perf_event * hwc,int idx)1023 static void armv8pmu_enable_event(struct hw_perf_event *hwc, int idx)
1024 {
1025 unsigned long flags;
1026 struct pmu_hw_events *events = cpu_pmu->get_hw_events();
1027
1028 /*
1029 * Enable counter and interrupt, and set the counter to count
1030 * the event that we're interested in.
1031 */
1032 raw_spin_lock_irqsave(&events->pmu_lock, flags);
1033
1034 /*
1035 * Disable counter
1036 */
1037 armv8pmu_disable_counter(idx);
1038
1039 /*
1040 * Set event (if destined for PMNx counters).
1041 */
1042 armv8pmu_write_evtype(idx, hwc->config_base);
1043
1044 /*
1045 * Enable interrupt for this counter
1046 */
1047 armv8pmu_enable_intens(idx);
1048
1049 /*
1050 * Enable counter
1051 */
1052 armv8pmu_enable_counter(idx);
1053
1054 raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
1055 }
1056
armv8pmu_disable_event(struct hw_perf_event * hwc,int idx)1057 static void armv8pmu_disable_event(struct hw_perf_event *hwc, int idx)
1058 {
1059 unsigned long flags;
1060 struct pmu_hw_events *events = cpu_pmu->get_hw_events();
1061
1062 /*
1063 * Disable counter and interrupt
1064 */
1065 raw_spin_lock_irqsave(&events->pmu_lock, flags);
1066
1067 /*
1068 * Disable counter
1069 */
1070 armv8pmu_disable_counter(idx);
1071
1072 /*
1073 * Disable interrupt for this counter
1074 */
1075 armv8pmu_disable_intens(idx);
1076
1077 raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
1078 }
1079
armv8pmu_handle_irq(int irq_num,void * dev)1080 static irqreturn_t armv8pmu_handle_irq(int irq_num, void *dev)
1081 {
1082 u32 pmovsr;
1083 struct perf_sample_data data;
1084 struct pmu_hw_events *cpuc;
1085 struct pt_regs *regs;
1086 int idx;
1087
1088 /*
1089 * Get and reset the IRQ flags
1090 */
1091 pmovsr = armv8pmu_getreset_flags();
1092
1093 /*
1094 * Did an overflow occur?
1095 */
1096 if (!armv8pmu_has_overflowed(pmovsr))
1097 return IRQ_NONE;
1098
1099 /*
1100 * Handle the counter(s) overflow(s)
1101 */
1102 regs = get_irq_regs();
1103
1104 cpuc = this_cpu_ptr(&cpu_hw_events);
1105 for (idx = 0; idx < cpu_pmu->num_events; ++idx) {
1106 struct perf_event *event = cpuc->events[idx];
1107 struct hw_perf_event *hwc;
1108
1109 /* Ignore if we don't have an event. */
1110 if (!event)
1111 continue;
1112
1113 /*
1114 * We have a single interrupt for all counters. Check that
1115 * each counter has overflowed before we process it.
1116 */
1117 if (!armv8pmu_counter_has_overflowed(pmovsr, idx))
1118 continue;
1119
1120 hwc = &event->hw;
1121 armpmu_event_update(event, hwc, idx);
1122 perf_sample_data_init(&data, 0, hwc->last_period);
1123 if (!armpmu_event_set_period(event, hwc, idx))
1124 continue;
1125
1126 if (perf_event_overflow(event, &data, regs))
1127 cpu_pmu->disable(hwc, idx);
1128 }
1129
1130 /*
1131 * Handle the pending perf events.
1132 *
1133 * Note: this call *must* be run with interrupts disabled. For
1134 * platforms that can have the PMU interrupts raised as an NMI, this
1135 * will not work.
1136 */
1137 irq_work_run();
1138
1139 return IRQ_HANDLED;
1140 }
1141
armv8pmu_start(void)1142 static void armv8pmu_start(void)
1143 {
1144 unsigned long flags;
1145 struct pmu_hw_events *events = cpu_pmu->get_hw_events();
1146
1147 raw_spin_lock_irqsave(&events->pmu_lock, flags);
1148 /* Enable all counters */
1149 armv8pmu_pmcr_write(armv8pmu_pmcr_read() | ARMV8_PMCR_E);
1150 raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
1151 }
1152
armv8pmu_stop(void)1153 static void armv8pmu_stop(void)
1154 {
1155 unsigned long flags;
1156 struct pmu_hw_events *events = cpu_pmu->get_hw_events();
1157
1158 raw_spin_lock_irqsave(&events->pmu_lock, flags);
1159 /* Disable all counters */
1160 armv8pmu_pmcr_write(armv8pmu_pmcr_read() & ~ARMV8_PMCR_E);
1161 raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
1162 }
1163
armv8pmu_get_event_idx(struct pmu_hw_events * cpuc,struct hw_perf_event * event)1164 static int armv8pmu_get_event_idx(struct pmu_hw_events *cpuc,
1165 struct hw_perf_event *event)
1166 {
1167 int idx;
1168 unsigned long evtype = event->config_base & ARMV8_EVTYPE_EVENT;
1169
1170 /* Always place a cycle counter into the cycle counter. */
1171 if (evtype == ARMV8_PMUV3_PERFCTR_CLOCK_CYCLES) {
1172 if (test_and_set_bit(ARMV8_IDX_CYCLE_COUNTER, cpuc->used_mask))
1173 return -EAGAIN;
1174
1175 return ARMV8_IDX_CYCLE_COUNTER;
1176 }
1177
1178 /*
1179 * For anything other than a cycle counter, try and use
1180 * the events counters
1181 */
1182 for (idx = ARMV8_IDX_COUNTER0; idx < cpu_pmu->num_events; ++idx) {
1183 if (!test_and_set_bit(idx, cpuc->used_mask))
1184 return idx;
1185 }
1186
1187 /* The counters are all in use. */
1188 return -EAGAIN;
1189 }
1190
1191 /*
1192 * Add an event filter to a given event. This will only work for PMUv2 PMUs.
1193 */
armv8pmu_set_event_filter(struct hw_perf_event * event,struct perf_event_attr * attr)1194 static int armv8pmu_set_event_filter(struct hw_perf_event *event,
1195 struct perf_event_attr *attr)
1196 {
1197 unsigned long config_base = 0;
1198
1199 if (attr->exclude_idle)
1200 return -EPERM;
1201 if (attr->exclude_user)
1202 config_base |= ARMV8_EXCLUDE_EL0;
1203 if (attr->exclude_kernel)
1204 config_base |= ARMV8_EXCLUDE_EL1;
1205 if (!attr->exclude_hv)
1206 config_base |= ARMV8_INCLUDE_EL2;
1207
1208 /*
1209 * Install the filter into config_base as this is used to
1210 * construct the event type.
1211 */
1212 event->config_base = config_base;
1213
1214 return 0;
1215 }
1216
armv8pmu_reset(void * info)1217 static void armv8pmu_reset(void *info)
1218 {
1219 u32 idx, nb_cnt = cpu_pmu->num_events;
1220
1221 /* The counter and interrupt enable registers are unknown at reset. */
1222 for (idx = ARMV8_IDX_CYCLE_COUNTER; idx < nb_cnt; ++idx)
1223 armv8pmu_disable_event(NULL, idx);
1224
1225 /* Initialize & Reset PMNC: C and P bits. */
1226 armv8pmu_pmcr_write(ARMV8_PMCR_P | ARMV8_PMCR_C);
1227
1228 /* Disable access from userspace. */
1229 asm volatile("msr pmuserenr_el0, %0" :: "r" (0));
1230 }
1231
armv8_pmuv3_map_event(struct perf_event * event)1232 static int armv8_pmuv3_map_event(struct perf_event *event)
1233 {
1234 return map_cpu_event(event, &armv8_pmuv3_perf_map,
1235 &armv8_pmuv3_perf_cache_map,
1236 ARMV8_EVTYPE_EVENT);
1237 }
1238
1239 static struct arm_pmu armv8pmu = {
1240 .handle_irq = armv8pmu_handle_irq,
1241 .enable = armv8pmu_enable_event,
1242 .disable = armv8pmu_disable_event,
1243 .read_counter = armv8pmu_read_counter,
1244 .write_counter = armv8pmu_write_counter,
1245 .get_event_idx = armv8pmu_get_event_idx,
1246 .start = armv8pmu_start,
1247 .stop = armv8pmu_stop,
1248 .reset = armv8pmu_reset,
1249 .max_period = (1LLU << 32) - 1,
1250 };
1251
armv8pmu_read_num_pmnc_events(void)1252 static u32 __init armv8pmu_read_num_pmnc_events(void)
1253 {
1254 u32 nb_cnt;
1255
1256 /* Read the nb of CNTx counters supported from PMNC */
1257 nb_cnt = (armv8pmu_pmcr_read() >> ARMV8_PMCR_N_SHIFT) & ARMV8_PMCR_N_MASK;
1258
1259 /* Add the CPU cycles counter and return */
1260 return nb_cnt + 1;
1261 }
1262
armv8_pmuv3_pmu_init(void)1263 static struct arm_pmu *__init armv8_pmuv3_pmu_init(void)
1264 {
1265 armv8pmu.name = "arm/armv8-pmuv3";
1266 armv8pmu.map_event = armv8_pmuv3_map_event;
1267 armv8pmu.num_events = armv8pmu_read_num_pmnc_events();
1268 armv8pmu.set_event_filter = armv8pmu_set_event_filter;
1269 return &armv8pmu;
1270 }
1271
1272 /*
1273 * Ensure the PMU has sane values out of reset.
1274 * This requires SMP to be available, so exists as a separate initcall.
1275 */
1276 static int __init
cpu_pmu_reset(void)1277 cpu_pmu_reset(void)
1278 {
1279 if (cpu_pmu && cpu_pmu->reset)
1280 return on_each_cpu(cpu_pmu->reset, NULL, 1);
1281 return 0;
1282 }
1283 arch_initcall(cpu_pmu_reset);
1284
1285 /*
1286 * PMU platform driver and devicetree bindings.
1287 */
1288 static const struct of_device_id armpmu_of_device_ids[] = {
1289 {.compatible = "arm,armv8-pmuv3"},
1290 {},
1291 };
1292
armpmu_device_probe(struct platform_device * pdev)1293 static int armpmu_device_probe(struct platform_device *pdev)
1294 {
1295 if (!cpu_pmu)
1296 return -ENODEV;
1297
1298 cpu_pmu->plat_device = pdev;
1299 return 0;
1300 }
1301
1302 static struct platform_driver armpmu_driver = {
1303 .driver = {
1304 .name = "arm-pmu",
1305 .of_match_table = armpmu_of_device_ids,
1306 },
1307 .probe = armpmu_device_probe,
1308 };
1309
register_pmu_driver(void)1310 static int __init register_pmu_driver(void)
1311 {
1312 return platform_driver_register(&armpmu_driver);
1313 }
1314 device_initcall(register_pmu_driver);
1315
armpmu_get_cpu_events(void)1316 static struct pmu_hw_events *armpmu_get_cpu_events(void)
1317 {
1318 return this_cpu_ptr(&cpu_hw_events);
1319 }
1320
cpu_pmu_init(struct arm_pmu * armpmu)1321 static void __init cpu_pmu_init(struct arm_pmu *armpmu)
1322 {
1323 int cpu;
1324 for_each_possible_cpu(cpu) {
1325 struct pmu_hw_events *events = &per_cpu(cpu_hw_events, cpu);
1326 events->events = per_cpu(hw_events, cpu);
1327 events->used_mask = per_cpu(used_mask, cpu);
1328 raw_spin_lock_init(&events->pmu_lock);
1329 }
1330 armpmu->get_hw_events = armpmu_get_cpu_events;
1331 }
1332
init_hw_perf_events(void)1333 static int __init init_hw_perf_events(void)
1334 {
1335 u64 dfr = read_system_reg(SYS_ID_AA64DFR0_EL1);
1336
1337 switch (cpuid_feature_extract_field(dfr, ID_AA64DFR0_PMUVER_SHIFT)) {
1338 case 0x1: /* PMUv3 */
1339 cpu_pmu = armv8_pmuv3_pmu_init();
1340 break;
1341 }
1342
1343 if (cpu_pmu) {
1344 pr_info("enabled with %s PMU driver, %d counters available\n",
1345 cpu_pmu->name, cpu_pmu->num_events);
1346 cpu_pmu_init(cpu_pmu);
1347 armpmu_register(cpu_pmu, "cpu", PERF_TYPE_RAW);
1348 } else {
1349 pr_info("no hardware support available\n");
1350 }
1351
1352 return 0;
1353 }
1354 early_initcall(init_hw_perf_events);
1355
1356 /*
1357 * Callchain handling code.
1358 */
1359 struct frame_tail {
1360 struct frame_tail __user *fp;
1361 unsigned long lr;
1362 } __attribute__((packed));
1363
1364 /*
1365 * Get the return address for a single stackframe and return a pointer to the
1366 * next frame tail.
1367 */
1368 static struct frame_tail __user *
user_backtrace(struct frame_tail __user * tail,struct perf_callchain_entry * entry)1369 user_backtrace(struct frame_tail __user *tail,
1370 struct perf_callchain_entry *entry)
1371 {
1372 struct frame_tail buftail;
1373 unsigned long err;
1374
1375 /* Also check accessibility of one struct frame_tail beyond */
1376 if (!access_ok(VERIFY_READ, tail, sizeof(buftail)))
1377 return NULL;
1378
1379 pagefault_disable();
1380 err = __copy_from_user_inatomic(&buftail, tail, sizeof(buftail));
1381 pagefault_enable();
1382
1383 if (err)
1384 return NULL;
1385
1386 perf_callchain_store(entry, buftail.lr);
1387
1388 /*
1389 * Frame pointers should strictly progress back up the stack
1390 * (towards higher addresses).
1391 */
1392 if (tail >= buftail.fp)
1393 return NULL;
1394
1395 return buftail.fp;
1396 }
1397
1398 #ifdef CONFIG_COMPAT
1399 /*
1400 * The registers we're interested in are at the end of the variable
1401 * length saved register structure. The fp points at the end of this
1402 * structure so the address of this struct is:
1403 * (struct compat_frame_tail *)(xxx->fp)-1
1404 *
1405 * This code has been adapted from the ARM OProfile support.
1406 */
1407 struct compat_frame_tail {
1408 compat_uptr_t fp; /* a (struct compat_frame_tail *) in compat mode */
1409 u32 sp;
1410 u32 lr;
1411 } __attribute__((packed));
1412
1413 static struct compat_frame_tail __user *
compat_user_backtrace(struct compat_frame_tail __user * tail,struct perf_callchain_entry * entry)1414 compat_user_backtrace(struct compat_frame_tail __user *tail,
1415 struct perf_callchain_entry *entry)
1416 {
1417 struct compat_frame_tail buftail;
1418 unsigned long err;
1419
1420 /* Also check accessibility of one struct frame_tail beyond */
1421 if (!access_ok(VERIFY_READ, tail, sizeof(buftail)))
1422 return NULL;
1423
1424 pagefault_disable();
1425 err = __copy_from_user_inatomic(&buftail, tail, sizeof(buftail));
1426 pagefault_enable();
1427
1428 if (err)
1429 return NULL;
1430
1431 perf_callchain_store(entry, buftail.lr);
1432
1433 /*
1434 * Frame pointers should strictly progress back up the stack
1435 * (towards higher addresses).
1436 */
1437 if (tail + 1 >= (struct compat_frame_tail __user *)
1438 compat_ptr(buftail.fp))
1439 return NULL;
1440
1441 return (struct compat_frame_tail __user *)compat_ptr(buftail.fp) - 1;
1442 }
1443 #endif /* CONFIG_COMPAT */
1444
perf_callchain_user(struct perf_callchain_entry * entry,struct pt_regs * regs)1445 void perf_callchain_user(struct perf_callchain_entry *entry,
1446 struct pt_regs *regs)
1447 {
1448 if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
1449 /* We don't support guest os callchain now */
1450 return;
1451 }
1452
1453 perf_callchain_store(entry, regs->pc);
1454
1455 if (!compat_user_mode(regs)) {
1456 /* AARCH64 mode */
1457 struct frame_tail __user *tail;
1458
1459 tail = (struct frame_tail __user *)regs->regs[29];
1460
1461 while (entry->nr < PERF_MAX_STACK_DEPTH &&
1462 tail && !((unsigned long)tail & 0xf))
1463 tail = user_backtrace(tail, entry);
1464 } else {
1465 #ifdef CONFIG_COMPAT
1466 /* AARCH32 compat mode */
1467 struct compat_frame_tail __user *tail;
1468
1469 tail = (struct compat_frame_tail __user *)regs->compat_fp - 1;
1470
1471 while ((entry->nr < PERF_MAX_STACK_DEPTH) &&
1472 tail && !((unsigned long)tail & 0x3))
1473 tail = compat_user_backtrace(tail, entry);
1474 #endif
1475 }
1476 }
1477
1478 /*
1479 * Gets called by walk_stackframe() for every stackframe. This will be called
1480 * whist unwinding the stackframe and is like a subroutine return so we use
1481 * the PC.
1482 */
callchain_trace(struct stackframe * frame,void * data)1483 static int callchain_trace(struct stackframe *frame, void *data)
1484 {
1485 struct perf_callchain_entry *entry = data;
1486 perf_callchain_store(entry, frame->pc);
1487 return 0;
1488 }
1489
perf_callchain_kernel(struct perf_callchain_entry * entry,struct pt_regs * regs)1490 void perf_callchain_kernel(struct perf_callchain_entry *entry,
1491 struct pt_regs *regs)
1492 {
1493 struct stackframe frame;
1494
1495 if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
1496 /* We don't support guest os callchain now */
1497 return;
1498 }
1499
1500 frame.fp = regs->regs[29];
1501 frame.sp = regs->sp;
1502 frame.pc = regs->pc;
1503
1504 walk_stackframe(&frame, callchain_trace, entry);
1505 }
1506
perf_instruction_pointer(struct pt_regs * regs)1507 unsigned long perf_instruction_pointer(struct pt_regs *regs)
1508 {
1509 if (perf_guest_cbs && perf_guest_cbs->is_in_guest())
1510 return perf_guest_cbs->get_guest_ip();
1511
1512 return instruction_pointer(regs);
1513 }
1514
perf_misc_flags(struct pt_regs * regs)1515 unsigned long perf_misc_flags(struct pt_regs *regs)
1516 {
1517 int misc = 0;
1518
1519 if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
1520 if (perf_guest_cbs->is_user_mode())
1521 misc |= PERF_RECORD_MISC_GUEST_USER;
1522 else
1523 misc |= PERF_RECORD_MISC_GUEST_KERNEL;
1524 } else {
1525 if (user_mode(regs))
1526 misc |= PERF_RECORD_MISC_USER;
1527 else
1528 misc |= PERF_RECORD_MISC_KERNEL;
1529 }
1530
1531 return misc;
1532 }
1533