1 /*
2 * Based on arch/arm/kernel/setup.c
3 *
4 * Copyright (C) 1995-2001 Russell King
5 * Copyright (C) 2012 ARM Ltd.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include <linux/export.h>
21 #include <linux/kernel.h>
22 #include <linux/stddef.h>
23 #include <linux/ioport.h>
24 #include <linux/delay.h>
25 #include <linux/utsname.h>
26 #include <linux/initrd.h>
27 #include <linux/console.h>
28 #include <linux/cache.h>
29 #include <linux/bootmem.h>
30 #include <linux/screen_info.h>
31 #include <linux/init.h>
32 #include <linux/kexec.h>
33 #include <linux/crash_dump.h>
34 #include <linux/root_dev.h>
35 #include <linux/clk-provider.h>
36 #include <linux/cpu.h>
37 #include <linux/interrupt.h>
38 #include <linux/smp.h>
39 #include <linux/fs.h>
40 #include <linux/proc_fs.h>
41 #include <linux/memblock.h>
42 #include <linux/of_fdt.h>
43 #include <linux/of_platform.h>
44 #include <linux/efi.h>
45 #include <linux/personality.h>
46
47 #include <asm/fixmap.h>
48 #include <asm/cpu.h>
49 #include <asm/cputype.h>
50 #include <asm/elf.h>
51 #include <asm/cpufeature.h>
52 #include <asm/cpu_ops.h>
53 #include <asm/sections.h>
54 #include <asm/setup.h>
55 #include <asm/smp_plat.h>
56 #include <asm/cacheflush.h>
57 #include <asm/tlbflush.h>
58 #include <asm/traps.h>
59 #include <asm/memblock.h>
60 #include <asm/psci.h>
61 #include <asm/efi.h>
62
63 phys_addr_t __fdt_pointer __initdata;
64
65 /*
66 * Standard memory resources
67 */
68 static struct resource mem_res[] = {
69 {
70 .name = "Kernel code",
71 .start = 0,
72 .end = 0,
73 .flags = IORESOURCE_MEM
74 },
75 {
76 .name = "Kernel data",
77 .start = 0,
78 .end = 0,
79 .flags = IORESOURCE_MEM
80 }
81 };
82
83 #define kernel_code mem_res[0]
84 #define kernel_data mem_res[1]
85
early_print(const char * str,...)86 void __init early_print(const char *str, ...)
87 {
88 char buf[256];
89 va_list ap;
90
91 va_start(ap, str);
92 vsnprintf(buf, sizeof(buf), str, ap);
93 va_end(ap);
94
95 printk("%s", buf);
96 }
97
98 /*
99 * The recorded values of x0 .. x3 upon kernel entry.
100 */
101 u64 __cacheline_aligned boot_args[4];
102
smp_setup_processor_id(void)103 void __init smp_setup_processor_id(void)
104 {
105 /*
106 * clear __my_cpu_offset on boot CPU to avoid hang caused by
107 * using percpu variable early, for example, lockdep will
108 * access percpu variable inside lock_release
109 */
110 set_my_cpu_offset(0);
111 }
112
arch_match_cpu_phys_id(int cpu,u64 phys_id)113 bool arch_match_cpu_phys_id(int cpu, u64 phys_id)
114 {
115 return phys_id == cpu_logical_map(cpu);
116 }
117
118 struct mpidr_hash mpidr_hash;
119 /**
120 * smp_build_mpidr_hash - Pre-compute shifts required at each affinity
121 * level in order to build a linear index from an
122 * MPIDR value. Resulting algorithm is a collision
123 * free hash carried out through shifting and ORing
124 */
smp_build_mpidr_hash(void)125 static void __init smp_build_mpidr_hash(void)
126 {
127 u32 i, affinity, fs[4], bits[4], ls;
128 u64 mask = 0;
129 /*
130 * Pre-scan the list of MPIDRS and filter out bits that do
131 * not contribute to affinity levels, ie they never toggle.
132 */
133 for_each_possible_cpu(i)
134 mask |= (cpu_logical_map(i) ^ cpu_logical_map(0));
135 pr_debug("mask of set bits %#llx\n", mask);
136 /*
137 * Find and stash the last and first bit set at all affinity levels to
138 * check how many bits are required to represent them.
139 */
140 for (i = 0; i < 4; i++) {
141 affinity = MPIDR_AFFINITY_LEVEL(mask, i);
142 /*
143 * Find the MSB bit and LSB bits position
144 * to determine how many bits are required
145 * to express the affinity level.
146 */
147 ls = fls(affinity);
148 fs[i] = affinity ? ffs(affinity) - 1 : 0;
149 bits[i] = ls - fs[i];
150 }
151 /*
152 * An index can be created from the MPIDR_EL1 by isolating the
153 * significant bits at each affinity level and by shifting
154 * them in order to compress the 32 bits values space to a
155 * compressed set of values. This is equivalent to hashing
156 * the MPIDR_EL1 through shifting and ORing. It is a collision free
157 * hash though not minimal since some levels might contain a number
158 * of CPUs that is not an exact power of 2 and their bit
159 * representation might contain holes, eg MPIDR_EL1[7:0] = {0x2, 0x80}.
160 */
161 mpidr_hash.shift_aff[0] = MPIDR_LEVEL_SHIFT(0) + fs[0];
162 mpidr_hash.shift_aff[1] = MPIDR_LEVEL_SHIFT(1) + fs[1] - bits[0];
163 mpidr_hash.shift_aff[2] = MPIDR_LEVEL_SHIFT(2) + fs[2] -
164 (bits[1] + bits[0]);
165 mpidr_hash.shift_aff[3] = MPIDR_LEVEL_SHIFT(3) +
166 fs[3] - (bits[2] + bits[1] + bits[0]);
167 mpidr_hash.mask = mask;
168 mpidr_hash.bits = bits[3] + bits[2] + bits[1] + bits[0];
169 pr_debug("MPIDR hash: aff0[%u] aff1[%u] aff2[%u] aff3[%u] mask[%#llx] bits[%u]\n",
170 mpidr_hash.shift_aff[0],
171 mpidr_hash.shift_aff[1],
172 mpidr_hash.shift_aff[2],
173 mpidr_hash.shift_aff[3],
174 mpidr_hash.mask,
175 mpidr_hash.bits);
176 /*
177 * 4x is an arbitrary value used to warn on a hash table much bigger
178 * than expected on most systems.
179 */
180 if (mpidr_hash_size() > 4 * num_possible_cpus())
181 pr_warn("Large number of MPIDR hash buckets detected\n");
182 __flush_dcache_area(&mpidr_hash, sizeof(struct mpidr_hash));
183 }
184
setup_machine_fdt(phys_addr_t dt_phys)185 static void __init setup_machine_fdt(phys_addr_t dt_phys)
186 {
187 if (!dt_phys || !early_init_dt_scan(phys_to_virt(dt_phys))) {
188 early_print("\n"
189 "Error: invalid device tree blob at physical address 0x%p (virtual address 0x%p)\n"
190 "The dtb must be 8-byte aligned and passed in the first 512MB of memory\n"
191 "\nPlease check your bootloader.\n",
192 dt_phys, phys_to_virt(dt_phys));
193
194 while (true)
195 cpu_relax();
196 }
197
198 dump_stack_set_arch_desc("%s (DT)", of_flat_dt_get_machine_name());
199 }
200
201 /*
202 * Limit the memory size that was specified via FDT.
203 */
early_mem(char * p)204 static int __init early_mem(char *p)
205 {
206 phys_addr_t limit;
207
208 if (!p)
209 return 1;
210
211 limit = memparse(p, &p) & PAGE_MASK;
212 pr_notice("Memory limited to %lldMB\n", limit >> 20);
213
214 memblock_enforce_memory_limit(limit);
215
216 return 0;
217 }
218 early_param("mem", early_mem);
219
request_standard_resources(void)220 static void __init request_standard_resources(void)
221 {
222 struct memblock_region *region;
223 struct resource *res;
224
225 kernel_code.start = virt_to_phys(_text);
226 kernel_code.end = virt_to_phys(__init_begin - 1);
227 kernel_data.start = virt_to_phys(_sdata);
228 kernel_data.end = virt_to_phys(_end - 1);
229
230 for_each_memblock(memory, region) {
231 res = alloc_bootmem_low(sizeof(*res));
232 res->name = "System RAM";
233 res->start = __pfn_to_phys(memblock_region_memory_base_pfn(region));
234 res->end = __pfn_to_phys(memblock_region_memory_end_pfn(region)) - 1;
235 res->flags = IORESOURCE_MEM | IORESOURCE_BUSY;
236
237 request_resource(&iomem_resource, res);
238
239 if (kernel_code.start >= res->start &&
240 kernel_code.end <= res->end)
241 request_resource(res, &kernel_code);
242 if (kernel_data.start >= res->start &&
243 kernel_data.end <= res->end)
244 request_resource(res, &kernel_data);
245 }
246 }
247
248 u64 __cpu_logical_map[NR_CPUS] = { [0 ... NR_CPUS-1] = INVALID_HWID };
249
setup_arch(char ** cmdline_p)250 void __init setup_arch(char **cmdline_p)
251 {
252 pr_info("Boot CPU: AArch64 Processor [%08x]\n", read_cpuid_id());
253
254 setup_machine_fdt(__fdt_pointer);
255
256 sprintf(init_utsname()->machine, ELF_PLATFORM);
257 init_mm.start_code = (unsigned long) _text;
258 init_mm.end_code = (unsigned long) _etext;
259 init_mm.end_data = (unsigned long) _edata;
260 init_mm.brk = (unsigned long) _end;
261
262 *cmdline_p = boot_command_line;
263
264 early_fixmap_init();
265 early_ioremap_init();
266
267 parse_early_param();
268
269 /*
270 * Unmask asynchronous aborts after bringing up possible earlycon.
271 * (Report possible System Errors once we can report this occurred)
272 */
273 local_async_enable();
274
275 efi_init();
276 arm64_memblock_init();
277
278 paging_init();
279 request_standard_resources();
280
281 early_ioremap_reset();
282
283 unflatten_device_tree();
284
285 psci_init();
286
287 cpu_logical_map(0) = read_cpuid_mpidr() & MPIDR_HWID_BITMASK;
288 cpu_read_bootcpu_ops();
289 smp_init_cpus();
290 smp_build_mpidr_hash();
291
292 #ifdef CONFIG_ARM64_SW_TTBR0_PAN
293 /*
294 * Make sure init_thread_info.ttbr0 always generates translation
295 * faults in case uaccess_enable() is inadvertently called by the init
296 * thread.
297 */
298 init_thread_info.ttbr0 = virt_to_phys(empty_zero_page);
299 #endif
300
301 #ifdef CONFIG_VT
302 #if defined(CONFIG_VGA_CONSOLE)
303 conswitchp = &vga_con;
304 #elif defined(CONFIG_DUMMY_CONSOLE)
305 conswitchp = &dummy_con;
306 #endif
307 #endif
308 if (boot_args[1] || boot_args[2] || boot_args[3]) {
309 pr_err("WARNING: x1-x3 nonzero in violation of boot protocol:\n"
310 "\tx1: %016llx\n\tx2: %016llx\n\tx3: %016llx\n"
311 "This indicates a broken bootloader or old kernel\n",
312 boot_args[1], boot_args[2], boot_args[3]);
313 }
314 }
315
arm64_device_init(void)316 static int __init arm64_device_init(void)
317 {
318 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
319 return 0;
320 }
321 arch_initcall_sync(arm64_device_init);
322
topology_init(void)323 static int __init topology_init(void)
324 {
325 int i;
326
327 for_each_possible_cpu(i) {
328 struct cpu *cpu = &per_cpu(cpu_data.cpu, i);
329 cpu->hotpluggable = 1;
330 register_cpu(cpu, i);
331 }
332
333 return 0;
334 }
335 subsys_initcall(topology_init);
336