1 /*
2 * Copyright (C) 2005-2006 Atmel Corporation
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8 #include <linux/init.h>
9 #include <linux/device.h>
10 #include <linux/seq_file.h>
11 #include <linux/cpu.h>
12 #include <linux/module.h>
13 #include <linux/percpu.h>
14 #include <linux/param.h>
15 #include <linux/errno.h>
16 #include <linux/clk.h>
17
18 #include <asm/setup.h>
19 #include <asm/sysreg.h>
20
21 static DEFINE_PER_CPU(struct cpu, cpu_devices);
22
23 #ifdef CONFIG_PERFORMANCE_COUNTERS
24
25 /*
26 * XXX: If/when a SMP-capable implementation of AVR32 will ever be
27 * made, we must make sure that the code executes on the correct CPU.
28 */
show_pc0event(struct device * dev,struct device_attribute * attr,char * buf)29 static ssize_t show_pc0event(struct device *dev,
30 struct device_attribute *attr, char *buf)
31 {
32 unsigned long pccr;
33
34 pccr = sysreg_read(PCCR);
35 return sprintf(buf, "0x%lx\n", (pccr >> 12) & 0x3f);
36 }
store_pc0event(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)37 static ssize_t store_pc0event(struct device *dev,
38 struct device_attribute *attr, const char *buf,
39 size_t count)
40 {
41 unsigned long val;
42 int ret;
43
44 ret = kstrtoul(buf, 0, &val);
45 if (ret)
46 return ret;
47 if (val > 0x3f)
48 return -EINVAL;
49 val = (val << 12) | (sysreg_read(PCCR) & 0xfffc0fff);
50 sysreg_write(PCCR, val);
51 return count;
52 }
show_pc0count(struct device * dev,struct device_attribute * attr,char * buf)53 static ssize_t show_pc0count(struct device *dev,
54 struct device_attribute *attr, char *buf)
55 {
56 unsigned long pcnt0;
57
58 pcnt0 = sysreg_read(PCNT0);
59 return sprintf(buf, "%lu\n", pcnt0);
60 }
store_pc0count(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)61 static ssize_t store_pc0count(struct device *dev,
62 struct device_attribute *attr,
63 const char *buf, size_t count)
64 {
65 unsigned long val;
66 int ret;
67
68 ret = kstrtoul(buf, 0, &val);
69 if (ret)
70 return ret;
71 sysreg_write(PCNT0, val);
72
73 return count;
74 }
75
show_pc1event(struct device * dev,struct device_attribute * attr,char * buf)76 static ssize_t show_pc1event(struct device *dev,
77 struct device_attribute *attr, char *buf)
78 {
79 unsigned long pccr;
80
81 pccr = sysreg_read(PCCR);
82 return sprintf(buf, "0x%lx\n", (pccr >> 18) & 0x3f);
83 }
store_pc1event(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)84 static ssize_t store_pc1event(struct device *dev,
85 struct device_attribute *attr, const char *buf,
86 size_t count)
87 {
88 unsigned long val;
89 int ret;
90
91 ret = kstrtoul(buf, 0, &val);
92 if (ret)
93 return ret;
94 if (val > 0x3f)
95 return -EINVAL;
96 val = (val << 18) | (sysreg_read(PCCR) & 0xff03ffff);
97 sysreg_write(PCCR, val);
98 return count;
99 }
show_pc1count(struct device * dev,struct device_attribute * attr,char * buf)100 static ssize_t show_pc1count(struct device *dev,
101 struct device_attribute *attr, char *buf)
102 {
103 unsigned long pcnt1;
104
105 pcnt1 = sysreg_read(PCNT1);
106 return sprintf(buf, "%lu\n", pcnt1);
107 }
store_pc1count(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)108 static ssize_t store_pc1count(struct device *dev,
109 struct device_attribute *attr, const char *buf,
110 size_t count)
111 {
112 unsigned long val;
113 int ret;
114
115 ret = kstrtoul(buf, 0, &val);
116 if (ret)
117 return ret;
118 sysreg_write(PCNT1, val);
119
120 return count;
121 }
122
show_pccycles(struct device * dev,struct device_attribute * attr,char * buf)123 static ssize_t show_pccycles(struct device *dev,
124 struct device_attribute *attr, char *buf)
125 {
126 unsigned long pccnt;
127
128 pccnt = sysreg_read(PCCNT);
129 return sprintf(buf, "%lu\n", pccnt);
130 }
store_pccycles(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)131 static ssize_t store_pccycles(struct device *dev,
132 struct device_attribute *attr, const char *buf,
133 size_t count)
134 {
135 unsigned long val;
136 int ret;
137
138 ret = kstrtoul(buf, 0, &val);
139 if (ret)
140 return ret;
141 sysreg_write(PCCNT, val);
142
143 return count;
144 }
145
show_pcenable(struct device * dev,struct device_attribute * attr,char * buf)146 static ssize_t show_pcenable(struct device *dev,
147 struct device_attribute *attr, char *buf)
148 {
149 unsigned long pccr;
150
151 pccr = sysreg_read(PCCR);
152 return sprintf(buf, "%c\n", (pccr & 1)?'1':'0');
153 }
store_pcenable(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)154 static ssize_t store_pcenable(struct device *dev,
155 struct device_attribute *attr, const char *buf,
156 size_t count)
157 {
158 unsigned long pccr, val;
159 int ret;
160
161 ret = kstrtoul(buf, 0, &val);
162 if (ret)
163 return ret;
164 if (val)
165 val = 1;
166
167 pccr = sysreg_read(PCCR);
168 pccr = (pccr & ~1UL) | val;
169 sysreg_write(PCCR, pccr);
170
171 return count;
172 }
173
174 static DEVICE_ATTR(pc0event, 0600, show_pc0event, store_pc0event);
175 static DEVICE_ATTR(pc0count, 0600, show_pc0count, store_pc0count);
176 static DEVICE_ATTR(pc1event, 0600, show_pc1event, store_pc1event);
177 static DEVICE_ATTR(pc1count, 0600, show_pc1count, store_pc1count);
178 static DEVICE_ATTR(pccycles, 0600, show_pccycles, store_pccycles);
179 static DEVICE_ATTR(pcenable, 0600, show_pcenable, store_pcenable);
180
181 #endif /* CONFIG_PERFORMANCE_COUNTERS */
182
topology_init(void)183 static int __init topology_init(void)
184 {
185 int cpu;
186
187 for_each_possible_cpu(cpu) {
188 struct cpu *c = &per_cpu(cpu_devices, cpu);
189
190 register_cpu(c, cpu);
191
192 #ifdef CONFIG_PERFORMANCE_COUNTERS
193 device_create_file(&c->dev, &dev_attr_pc0event);
194 device_create_file(&c->dev, &dev_attr_pc0count);
195 device_create_file(&c->dev, &dev_attr_pc1event);
196 device_create_file(&c->dev, &dev_attr_pc1count);
197 device_create_file(&c->dev, &dev_attr_pccycles);
198 device_create_file(&c->dev, &dev_attr_pcenable);
199 #endif
200 }
201
202 return 0;
203 }
204
205 subsys_initcall(topology_init);
206
207 struct chip_id_map {
208 u16 mid;
209 u16 pn;
210 const char *name;
211 };
212
213 static const struct chip_id_map chip_names[] = {
214 { .mid = 0x1f, .pn = 0x1e82, .name = "AT32AP700x" },
215 };
216 #define NR_CHIP_NAMES ARRAY_SIZE(chip_names)
217
218 static const char *cpu_names[] = {
219 "Morgan",
220 "AP7",
221 };
222 #define NR_CPU_NAMES ARRAY_SIZE(cpu_names)
223
224 static const char *arch_names[] = {
225 "AVR32A",
226 "AVR32B",
227 };
228 #define NR_ARCH_NAMES ARRAY_SIZE(arch_names)
229
230 static const char *mmu_types[] = {
231 "No MMU",
232 "ITLB and DTLB",
233 "Shared TLB",
234 "MPU"
235 };
236
237 static const char *cpu_feature_flags[] = {
238 "rmw", "dsp", "simd", "ocd", "perfctr", "java", "fpu",
239 };
240
get_chip_name(struct avr32_cpuinfo * cpu)241 static const char *get_chip_name(struct avr32_cpuinfo *cpu)
242 {
243 unsigned int i;
244 unsigned int mid = avr32_get_manufacturer_id(cpu);
245 unsigned int pn = avr32_get_product_number(cpu);
246
247 for (i = 0; i < NR_CHIP_NAMES; i++) {
248 if (chip_names[i].mid == mid && chip_names[i].pn == pn)
249 return chip_names[i].name;
250 }
251
252 return "(unknown)";
253 }
254
setup_processor(void)255 void __init setup_processor(void)
256 {
257 unsigned long config0, config1;
258 unsigned long features;
259 unsigned cpu_id, cpu_rev, arch_id, arch_rev, mmu_type;
260 unsigned device_id;
261 unsigned tmp;
262 unsigned i;
263
264 config0 = sysreg_read(CONFIG0);
265 config1 = sysreg_read(CONFIG1);
266 cpu_id = SYSREG_BFEXT(PROCESSORID, config0);
267 cpu_rev = SYSREG_BFEXT(PROCESSORREVISION, config0);
268 arch_id = SYSREG_BFEXT(AT, config0);
269 arch_rev = SYSREG_BFEXT(AR, config0);
270 mmu_type = SYSREG_BFEXT(MMUT, config0);
271
272 device_id = ocd_read(DID);
273
274 boot_cpu_data.arch_type = arch_id;
275 boot_cpu_data.cpu_type = cpu_id;
276 boot_cpu_data.arch_revision = arch_rev;
277 boot_cpu_data.cpu_revision = cpu_rev;
278 boot_cpu_data.tlb_config = mmu_type;
279 boot_cpu_data.device_id = device_id;
280
281 tmp = SYSREG_BFEXT(ILSZ, config1);
282 if (tmp) {
283 boot_cpu_data.icache.ways = 1 << SYSREG_BFEXT(IASS, config1);
284 boot_cpu_data.icache.sets = 1 << SYSREG_BFEXT(ISET, config1);
285 boot_cpu_data.icache.linesz = 1 << (tmp + 1);
286 }
287 tmp = SYSREG_BFEXT(DLSZ, config1);
288 if (tmp) {
289 boot_cpu_data.dcache.ways = 1 << SYSREG_BFEXT(DASS, config1);
290 boot_cpu_data.dcache.sets = 1 << SYSREG_BFEXT(DSET, config1);
291 boot_cpu_data.dcache.linesz = 1 << (tmp + 1);
292 }
293
294 if ((cpu_id >= NR_CPU_NAMES) || (arch_id >= NR_ARCH_NAMES)) {
295 printk ("Unknown CPU configuration (ID %02x, arch %02x), "
296 "continuing anyway...\n",
297 cpu_id, arch_id);
298 return;
299 }
300
301 printk ("CPU: %s chip revision %c\n", get_chip_name(&boot_cpu_data),
302 avr32_get_chip_revision(&boot_cpu_data) + 'A');
303 printk ("CPU: %s [%02x] core revision %d (%s arch revision %d)\n",
304 cpu_names[cpu_id], cpu_id, cpu_rev,
305 arch_names[arch_id], arch_rev);
306 printk ("CPU: MMU configuration: %s\n", mmu_types[mmu_type]);
307
308 printk ("CPU: features:");
309 features = 0;
310 if (config0 & SYSREG_BIT(CONFIG0_R))
311 features |= AVR32_FEATURE_RMW;
312 if (config0 & SYSREG_BIT(CONFIG0_D))
313 features |= AVR32_FEATURE_DSP;
314 if (config0 & SYSREG_BIT(CONFIG0_S))
315 features |= AVR32_FEATURE_SIMD;
316 if (config0 & SYSREG_BIT(CONFIG0_O))
317 features |= AVR32_FEATURE_OCD;
318 if (config0 & SYSREG_BIT(CONFIG0_P))
319 features |= AVR32_FEATURE_PCTR;
320 if (config0 & SYSREG_BIT(CONFIG0_J))
321 features |= AVR32_FEATURE_JAVA;
322 if (config0 & SYSREG_BIT(CONFIG0_F))
323 features |= AVR32_FEATURE_FPU;
324
325 for (i = 0; i < ARRAY_SIZE(cpu_feature_flags); i++)
326 if (features & (1 << i))
327 printk(" %s", cpu_feature_flags[i]);
328
329 printk("\n");
330 boot_cpu_data.features = features;
331 }
332
333 #ifdef CONFIG_PROC_FS
c_show(struct seq_file * m,void * v)334 static int c_show(struct seq_file *m, void *v)
335 {
336 unsigned int icache_size, dcache_size;
337 unsigned int cpu = smp_processor_id();
338 unsigned int freq;
339 unsigned int i;
340
341 icache_size = boot_cpu_data.icache.ways *
342 boot_cpu_data.icache.sets *
343 boot_cpu_data.icache.linesz;
344 dcache_size = boot_cpu_data.dcache.ways *
345 boot_cpu_data.dcache.sets *
346 boot_cpu_data.dcache.linesz;
347
348 seq_printf(m, "processor\t: %d\n", cpu);
349
350 seq_printf(m, "chip type\t: %s revision %c\n",
351 get_chip_name(&boot_cpu_data),
352 avr32_get_chip_revision(&boot_cpu_data) + 'A');
353 if (boot_cpu_data.arch_type < NR_ARCH_NAMES)
354 seq_printf(m, "cpu arch\t: %s revision %d\n",
355 arch_names[boot_cpu_data.arch_type],
356 boot_cpu_data.arch_revision);
357 if (boot_cpu_data.cpu_type < NR_CPU_NAMES)
358 seq_printf(m, "cpu core\t: %s revision %d\n",
359 cpu_names[boot_cpu_data.cpu_type],
360 boot_cpu_data.cpu_revision);
361
362 freq = (clk_get_rate(boot_cpu_data.clk) + 500) / 1000;
363 seq_printf(m, "cpu MHz\t\t: %u.%03u\n", freq / 1000, freq % 1000);
364
365 seq_printf(m, "i-cache\t\t: %dK (%u ways x %u sets x %u)\n",
366 icache_size >> 10,
367 boot_cpu_data.icache.ways,
368 boot_cpu_data.icache.sets,
369 boot_cpu_data.icache.linesz);
370 seq_printf(m, "d-cache\t\t: %dK (%u ways x %u sets x %u)\n",
371 dcache_size >> 10,
372 boot_cpu_data.dcache.ways,
373 boot_cpu_data.dcache.sets,
374 boot_cpu_data.dcache.linesz);
375
376 seq_printf(m, "features\t:");
377 for (i = 0; i < ARRAY_SIZE(cpu_feature_flags); i++)
378 if (boot_cpu_data.features & (1 << i))
379 seq_printf(m, " %s", cpu_feature_flags[i]);
380
381 seq_printf(m, "\nbogomips\t: %lu.%02lu\n",
382 boot_cpu_data.loops_per_jiffy / (500000/HZ),
383 (boot_cpu_data.loops_per_jiffy / (5000/HZ)) % 100);
384
385 return 0;
386 }
387
c_start(struct seq_file * m,loff_t * pos)388 static void *c_start(struct seq_file *m, loff_t *pos)
389 {
390 return *pos < 1 ? (void *)1 : NULL;
391 }
392
c_next(struct seq_file * m,void * v,loff_t * pos)393 static void *c_next(struct seq_file *m, void *v, loff_t *pos)
394 {
395 ++*pos;
396 return NULL;
397 }
398
c_stop(struct seq_file * m,void * v)399 static void c_stop(struct seq_file *m, void *v)
400 {
401
402 }
403
404 const struct seq_operations cpuinfo_op = {
405 .start = c_start,
406 .next = c_next,
407 .stop = c_stop,
408 .show = c_show
409 };
410 #endif /* CONFIG_PROC_FS */
411