1 #ifndef __bif_dma_defs_h 2 #define __bif_dma_defs_h 3 4 /* 5 * This file is autogenerated from 6 * file: ../../inst/bif/rtl/bif_dma_regs.r 7 * id: bif_dma_regs.r,v 1.6 2005/02/04 13:28:31 perz Exp 8 * last modfied: Mon Apr 11 16:06:33 2005 9 * 10 * by /n/asic/design/tools/rdesc/src/rdes2c --outfile bif_dma_defs.h ../../inst/bif/rtl/bif_dma_regs.r 11 * id: $Id: bif_dma_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $ 12 * Any changes here will be lost. 13 * 14 * -*- buffer-read-only: t -*- 15 */ 16 /* Main access macros */ 17 #ifndef REG_RD 18 #define REG_RD( scope, inst, reg ) \ 19 REG_READ( reg_##scope##_##reg, \ 20 (inst) + REG_RD_ADDR_##scope##_##reg ) 21 #endif 22 23 #ifndef REG_WR 24 #define REG_WR( scope, inst, reg, val ) \ 25 REG_WRITE( reg_##scope##_##reg, \ 26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) 27 #endif 28 29 #ifndef REG_RD_VECT 30 #define REG_RD_VECT( scope, inst, reg, index ) \ 31 REG_READ( reg_##scope##_##reg, \ 32 (inst) + REG_RD_ADDR_##scope##_##reg + \ 33 (index) * STRIDE_##scope##_##reg ) 34 #endif 35 36 #ifndef REG_WR_VECT 37 #define REG_WR_VECT( scope, inst, reg, index, val ) \ 38 REG_WRITE( reg_##scope##_##reg, \ 39 (inst) + REG_WR_ADDR_##scope##_##reg + \ 40 (index) * STRIDE_##scope##_##reg, (val) ) 41 #endif 42 43 #ifndef REG_RD_INT 44 #define REG_RD_INT( scope, inst, reg ) \ 45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) 46 #endif 47 48 #ifndef REG_WR_INT 49 #define REG_WR_INT( scope, inst, reg, val ) \ 50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) 51 #endif 52 53 #ifndef REG_RD_INT_VECT 54 #define REG_RD_INT_VECT( scope, inst, reg, index ) \ 55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ 56 (index) * STRIDE_##scope##_##reg ) 57 #endif 58 59 #ifndef REG_WR_INT_VECT 60 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ 61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ 62 (index) * STRIDE_##scope##_##reg, (val) ) 63 #endif 64 65 #ifndef REG_TYPE_CONV 66 #define REG_TYPE_CONV( type, orgtype, val ) \ 67 ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) 68 #endif 69 70 #ifndef reg_page_size 71 #define reg_page_size 8192 72 #endif 73 74 #ifndef REG_ADDR 75 #define REG_ADDR( scope, inst, reg ) \ 76 ( (inst) + REG_RD_ADDR_##scope##_##reg ) 77 #endif 78 79 #ifndef REG_ADDR_VECT 80 #define REG_ADDR_VECT( scope, inst, reg, index ) \ 81 ( (inst) + REG_RD_ADDR_##scope##_##reg + \ 82 (index) * STRIDE_##scope##_##reg ) 83 #endif 84 85 /* C-code for register scope bif_dma */ 86 87 /* Register rw_ch0_ctrl, scope bif_dma, type rw */ 88 typedef struct { 89 unsigned int bw : 2; 90 unsigned int burst_len : 1; 91 unsigned int cont : 1; 92 unsigned int end_pad : 1; 93 unsigned int cnt : 1; 94 unsigned int dreq_pin : 3; 95 unsigned int dreq_mode : 2; 96 unsigned int tc_in_pin : 3; 97 unsigned int tc_in_mode : 2; 98 unsigned int bus_mode : 2; 99 unsigned int rate_en : 1; 100 unsigned int wr_all : 1; 101 unsigned int dummy1 : 12; 102 } reg_bif_dma_rw_ch0_ctrl; 103 #define REG_RD_ADDR_bif_dma_rw_ch0_ctrl 0 104 #define REG_WR_ADDR_bif_dma_rw_ch0_ctrl 0 105 106 /* Register rw_ch0_addr, scope bif_dma, type rw */ 107 typedef struct { 108 unsigned int addr : 32; 109 } reg_bif_dma_rw_ch0_addr; 110 #define REG_RD_ADDR_bif_dma_rw_ch0_addr 4 111 #define REG_WR_ADDR_bif_dma_rw_ch0_addr 4 112 113 /* Register rw_ch0_start, scope bif_dma, type rw */ 114 typedef struct { 115 unsigned int run : 1; 116 unsigned int dummy1 : 31; 117 } reg_bif_dma_rw_ch0_start; 118 #define REG_RD_ADDR_bif_dma_rw_ch0_start 8 119 #define REG_WR_ADDR_bif_dma_rw_ch0_start 8 120 121 /* Register rw_ch0_cnt, scope bif_dma, type rw */ 122 typedef struct { 123 unsigned int start_cnt : 16; 124 unsigned int dummy1 : 16; 125 } reg_bif_dma_rw_ch0_cnt; 126 #define REG_RD_ADDR_bif_dma_rw_ch0_cnt 12 127 #define REG_WR_ADDR_bif_dma_rw_ch0_cnt 12 128 129 /* Register r_ch0_stat, scope bif_dma, type r */ 130 typedef struct { 131 unsigned int cnt : 16; 132 unsigned int dummy1 : 15; 133 unsigned int run : 1; 134 } reg_bif_dma_r_ch0_stat; 135 #define REG_RD_ADDR_bif_dma_r_ch0_stat 16 136 137 /* Register rw_ch1_ctrl, scope bif_dma, type rw */ 138 typedef struct { 139 unsigned int bw : 2; 140 unsigned int burst_len : 1; 141 unsigned int cont : 1; 142 unsigned int end_discard : 1; 143 unsigned int cnt : 1; 144 unsigned int dreq_pin : 3; 145 unsigned int dreq_mode : 2; 146 unsigned int tc_in_pin : 3; 147 unsigned int tc_in_mode : 2; 148 unsigned int bus_mode : 2; 149 unsigned int rate_en : 1; 150 unsigned int dummy1 : 13; 151 } reg_bif_dma_rw_ch1_ctrl; 152 #define REG_RD_ADDR_bif_dma_rw_ch1_ctrl 32 153 #define REG_WR_ADDR_bif_dma_rw_ch1_ctrl 32 154 155 /* Register rw_ch1_addr, scope bif_dma, type rw */ 156 typedef struct { 157 unsigned int addr : 32; 158 } reg_bif_dma_rw_ch1_addr; 159 #define REG_RD_ADDR_bif_dma_rw_ch1_addr 36 160 #define REG_WR_ADDR_bif_dma_rw_ch1_addr 36 161 162 /* Register rw_ch1_start, scope bif_dma, type rw */ 163 typedef struct { 164 unsigned int run : 1; 165 unsigned int dummy1 : 31; 166 } reg_bif_dma_rw_ch1_start; 167 #define REG_RD_ADDR_bif_dma_rw_ch1_start 40 168 #define REG_WR_ADDR_bif_dma_rw_ch1_start 40 169 170 /* Register rw_ch1_cnt, scope bif_dma, type rw */ 171 typedef struct { 172 unsigned int start_cnt : 16; 173 unsigned int dummy1 : 16; 174 } reg_bif_dma_rw_ch1_cnt; 175 #define REG_RD_ADDR_bif_dma_rw_ch1_cnt 44 176 #define REG_WR_ADDR_bif_dma_rw_ch1_cnt 44 177 178 /* Register r_ch1_stat, scope bif_dma, type r */ 179 typedef struct { 180 unsigned int cnt : 16; 181 unsigned int dummy1 : 15; 182 unsigned int run : 1; 183 } reg_bif_dma_r_ch1_stat; 184 #define REG_RD_ADDR_bif_dma_r_ch1_stat 48 185 186 /* Register rw_ch2_ctrl, scope bif_dma, type rw */ 187 typedef struct { 188 unsigned int bw : 2; 189 unsigned int burst_len : 1; 190 unsigned int cont : 1; 191 unsigned int end_pad : 1; 192 unsigned int cnt : 1; 193 unsigned int dreq_pin : 3; 194 unsigned int dreq_mode : 2; 195 unsigned int tc_in_pin : 3; 196 unsigned int tc_in_mode : 2; 197 unsigned int bus_mode : 2; 198 unsigned int rate_en : 1; 199 unsigned int wr_all : 1; 200 unsigned int dummy1 : 12; 201 } reg_bif_dma_rw_ch2_ctrl; 202 #define REG_RD_ADDR_bif_dma_rw_ch2_ctrl 64 203 #define REG_WR_ADDR_bif_dma_rw_ch2_ctrl 64 204 205 /* Register rw_ch2_addr, scope bif_dma, type rw */ 206 typedef struct { 207 unsigned int addr : 32; 208 } reg_bif_dma_rw_ch2_addr; 209 #define REG_RD_ADDR_bif_dma_rw_ch2_addr 68 210 #define REG_WR_ADDR_bif_dma_rw_ch2_addr 68 211 212 /* Register rw_ch2_start, scope bif_dma, type rw */ 213 typedef struct { 214 unsigned int run : 1; 215 unsigned int dummy1 : 31; 216 } reg_bif_dma_rw_ch2_start; 217 #define REG_RD_ADDR_bif_dma_rw_ch2_start 72 218 #define REG_WR_ADDR_bif_dma_rw_ch2_start 72 219 220 /* Register rw_ch2_cnt, scope bif_dma, type rw */ 221 typedef struct { 222 unsigned int start_cnt : 16; 223 unsigned int dummy1 : 16; 224 } reg_bif_dma_rw_ch2_cnt; 225 #define REG_RD_ADDR_bif_dma_rw_ch2_cnt 76 226 #define REG_WR_ADDR_bif_dma_rw_ch2_cnt 76 227 228 /* Register r_ch2_stat, scope bif_dma, type r */ 229 typedef struct { 230 unsigned int cnt : 16; 231 unsigned int dummy1 : 15; 232 unsigned int run : 1; 233 } reg_bif_dma_r_ch2_stat; 234 #define REG_RD_ADDR_bif_dma_r_ch2_stat 80 235 236 /* Register rw_ch3_ctrl, scope bif_dma, type rw */ 237 typedef struct { 238 unsigned int bw : 2; 239 unsigned int burst_len : 1; 240 unsigned int cont : 1; 241 unsigned int end_discard : 1; 242 unsigned int cnt : 1; 243 unsigned int dreq_pin : 3; 244 unsigned int dreq_mode : 2; 245 unsigned int tc_in_pin : 3; 246 unsigned int tc_in_mode : 2; 247 unsigned int bus_mode : 2; 248 unsigned int rate_en : 1; 249 unsigned int dummy1 : 13; 250 } reg_bif_dma_rw_ch3_ctrl; 251 #define REG_RD_ADDR_bif_dma_rw_ch3_ctrl 96 252 #define REG_WR_ADDR_bif_dma_rw_ch3_ctrl 96 253 254 /* Register rw_ch3_addr, scope bif_dma, type rw */ 255 typedef struct { 256 unsigned int addr : 32; 257 } reg_bif_dma_rw_ch3_addr; 258 #define REG_RD_ADDR_bif_dma_rw_ch3_addr 100 259 #define REG_WR_ADDR_bif_dma_rw_ch3_addr 100 260 261 /* Register rw_ch3_start, scope bif_dma, type rw */ 262 typedef struct { 263 unsigned int run : 1; 264 unsigned int dummy1 : 31; 265 } reg_bif_dma_rw_ch3_start; 266 #define REG_RD_ADDR_bif_dma_rw_ch3_start 104 267 #define REG_WR_ADDR_bif_dma_rw_ch3_start 104 268 269 /* Register rw_ch3_cnt, scope bif_dma, type rw */ 270 typedef struct { 271 unsigned int start_cnt : 16; 272 unsigned int dummy1 : 16; 273 } reg_bif_dma_rw_ch3_cnt; 274 #define REG_RD_ADDR_bif_dma_rw_ch3_cnt 108 275 #define REG_WR_ADDR_bif_dma_rw_ch3_cnt 108 276 277 /* Register r_ch3_stat, scope bif_dma, type r */ 278 typedef struct { 279 unsigned int cnt : 16; 280 unsigned int dummy1 : 15; 281 unsigned int run : 1; 282 } reg_bif_dma_r_ch3_stat; 283 #define REG_RD_ADDR_bif_dma_r_ch3_stat 112 284 285 /* Register rw_intr_mask, scope bif_dma, type rw */ 286 typedef struct { 287 unsigned int ext_dma0 : 1; 288 unsigned int ext_dma1 : 1; 289 unsigned int ext_dma2 : 1; 290 unsigned int ext_dma3 : 1; 291 unsigned int dummy1 : 28; 292 } reg_bif_dma_rw_intr_mask; 293 #define REG_RD_ADDR_bif_dma_rw_intr_mask 128 294 #define REG_WR_ADDR_bif_dma_rw_intr_mask 128 295 296 /* Register rw_ack_intr, scope bif_dma, type rw */ 297 typedef struct { 298 unsigned int ext_dma0 : 1; 299 unsigned int ext_dma1 : 1; 300 unsigned int ext_dma2 : 1; 301 unsigned int ext_dma3 : 1; 302 unsigned int dummy1 : 28; 303 } reg_bif_dma_rw_ack_intr; 304 #define REG_RD_ADDR_bif_dma_rw_ack_intr 132 305 #define REG_WR_ADDR_bif_dma_rw_ack_intr 132 306 307 /* Register r_intr, scope bif_dma, type r */ 308 typedef struct { 309 unsigned int ext_dma0 : 1; 310 unsigned int ext_dma1 : 1; 311 unsigned int ext_dma2 : 1; 312 unsigned int ext_dma3 : 1; 313 unsigned int dummy1 : 28; 314 } reg_bif_dma_r_intr; 315 #define REG_RD_ADDR_bif_dma_r_intr 136 316 317 /* Register r_masked_intr, scope bif_dma, type r */ 318 typedef struct { 319 unsigned int ext_dma0 : 1; 320 unsigned int ext_dma1 : 1; 321 unsigned int ext_dma2 : 1; 322 unsigned int ext_dma3 : 1; 323 unsigned int dummy1 : 28; 324 } reg_bif_dma_r_masked_intr; 325 #define REG_RD_ADDR_bif_dma_r_masked_intr 140 326 327 /* Register rw_pin0_cfg, scope bif_dma, type rw */ 328 typedef struct { 329 unsigned int master_ch : 2; 330 unsigned int master_mode : 3; 331 unsigned int slave_ch : 2; 332 unsigned int slave_mode : 3; 333 unsigned int dummy1 : 22; 334 } reg_bif_dma_rw_pin0_cfg; 335 #define REG_RD_ADDR_bif_dma_rw_pin0_cfg 160 336 #define REG_WR_ADDR_bif_dma_rw_pin0_cfg 160 337 338 /* Register rw_pin1_cfg, scope bif_dma, type rw */ 339 typedef struct { 340 unsigned int master_ch : 2; 341 unsigned int master_mode : 3; 342 unsigned int slave_ch : 2; 343 unsigned int slave_mode : 3; 344 unsigned int dummy1 : 22; 345 } reg_bif_dma_rw_pin1_cfg; 346 #define REG_RD_ADDR_bif_dma_rw_pin1_cfg 164 347 #define REG_WR_ADDR_bif_dma_rw_pin1_cfg 164 348 349 /* Register rw_pin2_cfg, scope bif_dma, type rw */ 350 typedef struct { 351 unsigned int master_ch : 2; 352 unsigned int master_mode : 3; 353 unsigned int slave_ch : 2; 354 unsigned int slave_mode : 3; 355 unsigned int dummy1 : 22; 356 } reg_bif_dma_rw_pin2_cfg; 357 #define REG_RD_ADDR_bif_dma_rw_pin2_cfg 168 358 #define REG_WR_ADDR_bif_dma_rw_pin2_cfg 168 359 360 /* Register rw_pin3_cfg, scope bif_dma, type rw */ 361 typedef struct { 362 unsigned int master_ch : 2; 363 unsigned int master_mode : 3; 364 unsigned int slave_ch : 2; 365 unsigned int slave_mode : 3; 366 unsigned int dummy1 : 22; 367 } reg_bif_dma_rw_pin3_cfg; 368 #define REG_RD_ADDR_bif_dma_rw_pin3_cfg 172 369 #define REG_WR_ADDR_bif_dma_rw_pin3_cfg 172 370 371 /* Register rw_pin4_cfg, scope bif_dma, type rw */ 372 typedef struct { 373 unsigned int master_ch : 2; 374 unsigned int master_mode : 3; 375 unsigned int slave_ch : 2; 376 unsigned int slave_mode : 3; 377 unsigned int dummy1 : 22; 378 } reg_bif_dma_rw_pin4_cfg; 379 #define REG_RD_ADDR_bif_dma_rw_pin4_cfg 176 380 #define REG_WR_ADDR_bif_dma_rw_pin4_cfg 176 381 382 /* Register rw_pin5_cfg, scope bif_dma, type rw */ 383 typedef struct { 384 unsigned int master_ch : 2; 385 unsigned int master_mode : 3; 386 unsigned int slave_ch : 2; 387 unsigned int slave_mode : 3; 388 unsigned int dummy1 : 22; 389 } reg_bif_dma_rw_pin5_cfg; 390 #define REG_RD_ADDR_bif_dma_rw_pin5_cfg 180 391 #define REG_WR_ADDR_bif_dma_rw_pin5_cfg 180 392 393 /* Register rw_pin6_cfg, scope bif_dma, type rw */ 394 typedef struct { 395 unsigned int master_ch : 2; 396 unsigned int master_mode : 3; 397 unsigned int slave_ch : 2; 398 unsigned int slave_mode : 3; 399 unsigned int dummy1 : 22; 400 } reg_bif_dma_rw_pin6_cfg; 401 #define REG_RD_ADDR_bif_dma_rw_pin6_cfg 184 402 #define REG_WR_ADDR_bif_dma_rw_pin6_cfg 184 403 404 /* Register rw_pin7_cfg, scope bif_dma, type rw */ 405 typedef struct { 406 unsigned int master_ch : 2; 407 unsigned int master_mode : 3; 408 unsigned int slave_ch : 2; 409 unsigned int slave_mode : 3; 410 unsigned int dummy1 : 22; 411 } reg_bif_dma_rw_pin7_cfg; 412 #define REG_RD_ADDR_bif_dma_rw_pin7_cfg 188 413 #define REG_WR_ADDR_bif_dma_rw_pin7_cfg 188 414 415 /* Register r_pin_stat, scope bif_dma, type r */ 416 typedef struct { 417 unsigned int pin0 : 1; 418 unsigned int pin1 : 1; 419 unsigned int pin2 : 1; 420 unsigned int pin3 : 1; 421 unsigned int pin4 : 1; 422 unsigned int pin5 : 1; 423 unsigned int pin6 : 1; 424 unsigned int pin7 : 1; 425 unsigned int dummy1 : 24; 426 } reg_bif_dma_r_pin_stat; 427 #define REG_RD_ADDR_bif_dma_r_pin_stat 192 428 429 430 /* Constants */ 431 enum { 432 regk_bif_dma_as_master = 0x00000001, 433 regk_bif_dma_as_slave = 0x00000001, 434 regk_bif_dma_burst1 = 0x00000000, 435 regk_bif_dma_burst8 = 0x00000001, 436 regk_bif_dma_bw16 = 0x00000001, 437 regk_bif_dma_bw32 = 0x00000002, 438 regk_bif_dma_bw8 = 0x00000000, 439 regk_bif_dma_dack = 0x00000006, 440 regk_bif_dma_dack_inv = 0x00000007, 441 regk_bif_dma_force = 0x00000001, 442 regk_bif_dma_hi = 0x00000003, 443 regk_bif_dma_inv = 0x00000003, 444 regk_bif_dma_lo = 0x00000002, 445 regk_bif_dma_master = 0x00000001, 446 regk_bif_dma_no = 0x00000000, 447 regk_bif_dma_norm = 0x00000002, 448 regk_bif_dma_off = 0x00000000, 449 regk_bif_dma_rw_ch0_ctrl_default = 0x00000000, 450 regk_bif_dma_rw_ch0_start_default = 0x00000000, 451 regk_bif_dma_rw_ch1_ctrl_default = 0x00000000, 452 regk_bif_dma_rw_ch1_start_default = 0x00000000, 453 regk_bif_dma_rw_ch2_ctrl_default = 0x00000000, 454 regk_bif_dma_rw_ch2_start_default = 0x00000000, 455 regk_bif_dma_rw_ch3_ctrl_default = 0x00000000, 456 regk_bif_dma_rw_ch3_start_default = 0x00000000, 457 regk_bif_dma_rw_intr_mask_default = 0x00000000, 458 regk_bif_dma_rw_pin0_cfg_default = 0x00000000, 459 regk_bif_dma_rw_pin1_cfg_default = 0x00000000, 460 regk_bif_dma_rw_pin2_cfg_default = 0x00000000, 461 regk_bif_dma_rw_pin3_cfg_default = 0x00000000, 462 regk_bif_dma_rw_pin4_cfg_default = 0x00000000, 463 regk_bif_dma_rw_pin5_cfg_default = 0x00000000, 464 regk_bif_dma_rw_pin6_cfg_default = 0x00000000, 465 regk_bif_dma_rw_pin7_cfg_default = 0x00000000, 466 regk_bif_dma_slave = 0x00000002, 467 regk_bif_dma_sreq = 0x00000006, 468 regk_bif_dma_sreq_inv = 0x00000007, 469 regk_bif_dma_tc = 0x00000004, 470 regk_bif_dma_tc_inv = 0x00000005, 471 regk_bif_dma_yes = 0x00000001 472 }; 473 #endif /* __bif_dma_defs_h */ 474