1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1994 - 2002 by Ralf Baechle
7 * Copyright (C) 1999, 2000, 2001 Silicon Graphics, Inc.
8 * Copyright (C) 2002 Maciej W. Rozycki
9 */
10 #ifndef _ASM_PGTABLE_BITS_H
11 #define _ASM_PGTABLE_BITS_H
12
13
14 /*
15 * Note that we shift the lower 32bits of each EntryLo[01] entry
16 * 6 bits to the left. That way we can convert the PFN into the
17 * physical address by a single 'and' operation and gain 6 additional
18 * bits for storing information which isn't present in a normal
19 * MIPS page table.
20 *
21 * Similar to the Alpha port, we need to keep track of the ref
22 * and mod bits in software. We have a software "yeah you can read
23 * from this page" bit, and a hardware one which actually lets the
24 * process read from the page. On the same token we have a software
25 * writable bit and the real hardware one which actually lets the
26 * process write to the page, this keeps a mod bit via the hardware
27 * dirty bit.
28 *
29 * Certain revisions of the R4000 and R5000 have a bug where if a
30 * certain sequence occurs in the last 3 instructions of an executable
31 * page, and the following page is not mapped, the cpu can do
32 * unpredictable things. The code (when it is written) to deal with
33 * this problem will be in the update_mmu_cache() code for the r4k.
34 */
35 #if defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32)
36
37 /*
38 * The following bits are implemented by the TLB hardware
39 */
40 #define _PAGE_NO_EXEC_SHIFT 0
41 #define _PAGE_NO_EXEC (1 << _PAGE_NO_EXEC_SHIFT)
42 #define _PAGE_NO_READ_SHIFT (_PAGE_NO_EXEC_SHIFT + 1)
43 #define _PAGE_NO_READ (1 << _PAGE_NO_READ_SHIFT)
44 #define _PAGE_GLOBAL_SHIFT (_PAGE_NO_READ_SHIFT + 1)
45 #define _PAGE_GLOBAL (1 << _PAGE_GLOBAL_SHIFT)
46 #define _PAGE_VALID_SHIFT (_PAGE_GLOBAL_SHIFT + 1)
47 #define _PAGE_VALID (1 << _PAGE_VALID_SHIFT)
48 #define _PAGE_DIRTY_SHIFT (_PAGE_VALID_SHIFT + 1)
49 #define _PAGE_DIRTY (1 << _PAGE_DIRTY_SHIFT)
50 #define _CACHE_SHIFT (_PAGE_DIRTY_SHIFT + 1)
51 #define _CACHE_MASK (7 << _CACHE_SHIFT)
52
53 /*
54 * The following bits are implemented in software
55 *
56 * _PAGE_FILE semantics: set:pagecache unset:swap
57 */
58 #define _PAGE_PRESENT_SHIFT (24)
59 #define _PAGE_PRESENT (1 << _PAGE_PRESENT_SHIFT)
60 #define _PAGE_READ_SHIFT (_PAGE_PRESENT_SHIFT + 1)
61 #define _PAGE_READ (1 << _PAGE_READ_SHIFT)
62 #define _PAGE_WRITE_SHIFT (_PAGE_READ_SHIFT + 1)
63 #define _PAGE_WRITE (1 << _PAGE_WRITE_SHIFT)
64 #define _PAGE_ACCESSED_SHIFT (_PAGE_WRITE_SHIFT + 1)
65 #define _PAGE_ACCESSED (1 << _PAGE_ACCESSED_SHIFT)
66 #define _PAGE_MODIFIED_SHIFT (_PAGE_ACCESSED_SHIFT + 1)
67 #define _PAGE_MODIFIED (1 << _PAGE_MODIFIED_SHIFT)
68
69 #define _PAGE_FILE _PAGE_MODIFIED
70
71 #define _PFN_SHIFT (PAGE_SHIFT - 12 + _CACHE_SHIFT + 3)
72
73 /*
74 * Bits for extended EntryLo0/EntryLo1 registers
75 */
76 #define _PFNX_MASK 0xffffff
77
78 #elif defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
79
80 /*
81 * The following bits are implemented in software
82 */
83 #define _PAGE_PRESENT_SHIFT (0)
84 #define _PAGE_PRESENT (1 << _PAGE_PRESENT_SHIFT)
85 #define _PAGE_READ_SHIFT (_PAGE_PRESENT_SHIFT + 1)
86 #define _PAGE_READ (1 << _PAGE_READ_SHIFT)
87 #define _PAGE_WRITE_SHIFT (_PAGE_READ_SHIFT + 1)
88 #define _PAGE_WRITE (1 << _PAGE_WRITE_SHIFT)
89 #define _PAGE_ACCESSED_SHIFT (_PAGE_WRITE_SHIFT + 1)
90 #define _PAGE_ACCESSED (1 << _PAGE_ACCESSED_SHIFT)
91 #define _PAGE_MODIFIED_SHIFT (_PAGE_ACCESSED_SHIFT + 1)
92 #define _PAGE_MODIFIED (1 << _PAGE_MODIFIED_SHIFT)
93 #define _PAGE_FILE_SHIFT (_PAGE_MODIFIED_SHIFT + 1)
94 #define _PAGE_FILE (1 << _PAGE_FILE_SHIFT)
95
96 /*
97 * The following bits are implemented by the TLB hardware
98 */
99 #define _PAGE_GLOBAL_SHIFT (_PAGE_MODIFIED_SHIFT + 4)
100 #define _PAGE_GLOBAL (1 << _PAGE_GLOBAL_SHIFT)
101 #define _PAGE_VALID_SHIFT (_PAGE_GLOBAL_SHIFT + 1)
102 #define _PAGE_VALID (1 << _PAGE_VALID_SHIFT)
103 #define _PAGE_DIRTY_SHIFT (_PAGE_VALID_SHIFT + 1)
104 #define _PAGE_DIRTY (1 << _PAGE_DIRTY_SHIFT)
105 #define _CACHE_UNCACHED_SHIFT (_PAGE_DIRTY_SHIFT + 1)
106 #define _CACHE_UNCACHED (1 << _CACHE_UNCACHED_SHIFT)
107 #define _CACHE_MASK _CACHE_UNCACHED
108
109 #define _PFN_SHIFT PAGE_SHIFT
110
111 #else
112 /*
113 * Below are the "Normal" R4K cases
114 */
115
116 /*
117 * The following bits are implemented in software
118 */
119 #define _PAGE_PRESENT_SHIFT 0
120 #define _PAGE_PRESENT (1 << _PAGE_PRESENT_SHIFT)
121 /* R2 or later cores check for RI/XI support to determine _PAGE_READ */
122 #if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6)
123 #define _PAGE_WRITE_SHIFT (_PAGE_PRESENT_SHIFT + 1)
124 #define _PAGE_WRITE (1 << _PAGE_WRITE_SHIFT)
125 #else
126 #define _PAGE_READ_SHIFT (_PAGE_PRESENT_SHIFT + 1)
127 #define _PAGE_READ (1 << _PAGE_READ_SHIFT)
128 #define _PAGE_WRITE_SHIFT (_PAGE_READ_SHIFT + 1)
129 #define _PAGE_WRITE (1 << _PAGE_WRITE_SHIFT)
130 #endif
131 #define _PAGE_ACCESSED_SHIFT (_PAGE_WRITE_SHIFT + 1)
132 #define _PAGE_ACCESSED (1 << _PAGE_ACCESSED_SHIFT)
133 #define _PAGE_MODIFIED_SHIFT (_PAGE_ACCESSED_SHIFT + 1)
134 #define _PAGE_MODIFIED (1 << _PAGE_MODIFIED_SHIFT)
135 #define _PAGE_FILE (_PAGE_MODIFIED)
136
137 #if defined(CONFIG_64BIT) && defined(CONFIG_MIPS_HUGE_TLB_SUPPORT)
138 /* Huge TLB page */
139 #define _PAGE_HUGE_SHIFT (_PAGE_MODIFIED_SHIFT + 1)
140 #define _PAGE_HUGE (1 << _PAGE_HUGE_SHIFT)
141 #define _PAGE_SPLITTING_SHIFT (_PAGE_HUGE_SHIFT + 1)
142 #define _PAGE_SPLITTING (1 << _PAGE_SPLITTING_SHIFT)
143
144 /* Only R2 or newer cores have the XI bit */
145 #if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6)
146 #define _PAGE_NO_EXEC_SHIFT (_PAGE_SPLITTING_SHIFT + 1)
147 #else
148 #define _PAGE_GLOBAL_SHIFT (_PAGE_SPLITTING_SHIFT + 1)
149 #define _PAGE_GLOBAL (1 << _PAGE_GLOBAL_SHIFT)
150 #endif /* CONFIG_CPU_MIPSR2 || CONFIG_CPU_MIPSR6 */
151
152 #endif /* CONFIG_64BIT && CONFIG_MIPS_HUGE_TLB_SUPPORT */
153
154 #if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6)
155 /* XI - page cannot be executed */
156 #ifndef _PAGE_NO_EXEC_SHIFT
157 #define _PAGE_NO_EXEC_SHIFT (_PAGE_MODIFIED_SHIFT + 1)
158 #endif
159 #define _PAGE_NO_EXEC (cpu_has_rixi ? (1 << _PAGE_NO_EXEC_SHIFT) : 0)
160
161 /* RI - page cannot be read */
162 #define _PAGE_READ_SHIFT (_PAGE_NO_EXEC_SHIFT + 1)
163 #define _PAGE_READ (cpu_has_rixi ? 0 : (1 << _PAGE_READ_SHIFT))
164 #define _PAGE_NO_READ_SHIFT _PAGE_READ_SHIFT
165 #define _PAGE_NO_READ (cpu_has_rixi ? (1 << _PAGE_READ_SHIFT) : 0)
166
167 #define _PAGE_GLOBAL_SHIFT (_PAGE_NO_READ_SHIFT + 1)
168 #define _PAGE_GLOBAL (1 << _PAGE_GLOBAL_SHIFT)
169
170 #else /* !CONFIG_CPU_MIPSR2 && !CONFIG_CPU_MIPSR6 */
171 #define _PAGE_GLOBAL_SHIFT (_PAGE_MODIFIED_SHIFT + 1)
172 #define _PAGE_GLOBAL (1 << _PAGE_GLOBAL_SHIFT)
173 #endif /* CONFIG_CPU_MIPSR2 || CONFIG_CPU_MIPSR6 */
174
175 #define _PAGE_VALID_SHIFT (_PAGE_GLOBAL_SHIFT + 1)
176 #define _PAGE_VALID (1 << _PAGE_VALID_SHIFT)
177 #define _PAGE_DIRTY_SHIFT (_PAGE_VALID_SHIFT + 1)
178 #define _PAGE_DIRTY (1 << _PAGE_DIRTY_SHIFT)
179 #define _CACHE_SHIFT (_PAGE_DIRTY_SHIFT + 1)
180 #define _CACHE_MASK (7 << _CACHE_SHIFT)
181
182 #define _PFN_SHIFT (PAGE_SHIFT - 12 + _CACHE_SHIFT + 3)
183
184 #endif /* defined(CONFIG_PHYS_ADDR_T_64BIT && defined(CONFIG_CPU_MIPS32) */
185
186 #ifndef _PAGE_NO_EXEC
187 #define _PAGE_NO_EXEC 0
188 #endif
189 #ifndef _PAGE_NO_READ
190 #define _PAGE_NO_READ 0
191 #endif
192
193 #define _PAGE_SILENT_READ _PAGE_VALID
194 #define _PAGE_SILENT_WRITE _PAGE_DIRTY
195
196 #define _PFN_MASK (~((1 << (_PFN_SHIFT)) - 1))
197
198 /*
199 * The final layouts of the PTE bits are:
200 *
201 * 64-bit, R1 or earlier: CCC D V G [S H] M A W R P
202 * 32-bit, R1 or earler: CCC D V G M A W R P
203 * 64-bit, R2 or later: CCC D V G RI/R XI [S H] M A W P
204 * 32-bit, R2 or later: CCC D V G RI/R XI M A W P
205 */
206
207
208 #ifndef __ASSEMBLY__
209 /*
210 * pte_to_entrylo converts a page table entry (PTE) into a Mips
211 * entrylo0/1 value.
212 */
pte_to_entrylo(unsigned long pte_val)213 static inline uint64_t pte_to_entrylo(unsigned long pte_val)
214 {
215 #if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6)
216 if (cpu_has_rixi) {
217 int sa;
218 #ifdef CONFIG_32BIT
219 sa = 31 - _PAGE_NO_READ_SHIFT;
220 #else
221 sa = 63 - _PAGE_NO_READ_SHIFT;
222 #endif
223 /*
224 * C has no way to express that this is a DSRL
225 * _PAGE_NO_EXEC_SHIFT followed by a ROTR 2. Luckily
226 * in the fast path this is done in assembly
227 */
228 return (pte_val >> _PAGE_GLOBAL_SHIFT) |
229 ((pte_val & (_PAGE_NO_EXEC | _PAGE_NO_READ)) << sa);
230 }
231 #endif
232
233 return pte_val >> _PAGE_GLOBAL_SHIFT;
234 }
235 #endif
236
237 /*
238 * Cache attributes
239 */
240 #if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
241
242 #define _CACHE_CACHABLE_NONCOHERENT 0
243 #define _CACHE_UNCACHED_ACCELERATED _CACHE_UNCACHED
244
245 #elif defined(CONFIG_CPU_SB1)
246
247 /* No penalty for being coherent on the SB1, so just
248 use it for "noncoherent" spaces, too. Shouldn't hurt. */
249
250 #define _CACHE_CACHABLE_NONCOHERENT (5<<_CACHE_SHIFT)
251
252 #elif defined(CONFIG_CPU_LOONGSON3)
253
254 /* Using COHERENT flag for NONCOHERENT doesn't hurt. */
255
256 #define _CACHE_CACHABLE_NONCOHERENT (3<<_CACHE_SHIFT) /* LOONGSON */
257 #define _CACHE_CACHABLE_COHERENT (3<<_CACHE_SHIFT) /* LOONGSON-3 */
258
259 #elif defined(CONFIG_MACH_JZ4740)
260
261 /* Ingenic uses the WA bit to achieve write-combine memory writes */
262 #define _CACHE_UNCACHED_ACCELERATED (1<<_CACHE_SHIFT)
263
264 #endif
265
266 #ifndef _CACHE_CACHABLE_NO_WA
267 #define _CACHE_CACHABLE_NO_WA (0<<_CACHE_SHIFT)
268 #endif
269 #ifndef _CACHE_CACHABLE_WA
270 #define _CACHE_CACHABLE_WA (1<<_CACHE_SHIFT)
271 #endif
272 #ifndef _CACHE_UNCACHED
273 #define _CACHE_UNCACHED (2<<_CACHE_SHIFT)
274 #endif
275 #ifndef _CACHE_CACHABLE_NONCOHERENT
276 #define _CACHE_CACHABLE_NONCOHERENT (3<<_CACHE_SHIFT)
277 #endif
278 #ifndef _CACHE_CACHABLE_CE
279 #define _CACHE_CACHABLE_CE (4<<_CACHE_SHIFT)
280 #endif
281 #ifndef _CACHE_CACHABLE_COW
282 #define _CACHE_CACHABLE_COW (5<<_CACHE_SHIFT)
283 #endif
284 #ifndef _CACHE_CACHABLE_CUW
285 #define _CACHE_CACHABLE_CUW (6<<_CACHE_SHIFT)
286 #endif
287 #ifndef _CACHE_UNCACHED_ACCELERATED
288 #define _CACHE_UNCACHED_ACCELERATED (7<<_CACHE_SHIFT)
289 #endif
290
291 #define __READABLE (_PAGE_SILENT_READ | _PAGE_READ | _PAGE_ACCESSED)
292 #define __WRITEABLE (_PAGE_SILENT_WRITE | _PAGE_WRITE | _PAGE_MODIFIED)
293
294 #define _PAGE_CHG_MASK (_PAGE_ACCESSED | _PAGE_MODIFIED | \
295 _PFN_MASK | _CACHE_MASK)
296
297 #endif /* _ASM_PGTABLE_BITS_H */
298