1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2007 MIPS Technologies, Inc.
7 * Copyright (C) 2007 Ralf Baechle <ralf@linux-mips.org>
8 */
9 #include <linux/clockchips.h>
10 #include <linux/interrupt.h>
11 #include <linux/percpu.h>
12 #include <linux/smp.h>
13 #include <linux/irq.h>
14
15 #include <asm/time.h>
16 #include <asm/cevt-r4k.h>
17 #include <asm/gic.h>
18
mips_next_event(unsigned long delta,struct clock_event_device * evt)19 static int mips_next_event(unsigned long delta,
20 struct clock_event_device *evt)
21 {
22 unsigned int cnt;
23 int res;
24
25 cnt = read_c0_count();
26 cnt += delta;
27 write_c0_compare(cnt);
28 res = ((int)(read_c0_count() - cnt) >= 0) ? -ETIME : 0;
29 return res;
30 }
31
mips_set_clock_mode(enum clock_event_mode mode,struct clock_event_device * evt)32 void mips_set_clock_mode(enum clock_event_mode mode,
33 struct clock_event_device *evt)
34 {
35 /* Nothing to do ... */
36 }
37
38 DEFINE_PER_CPU(struct clock_event_device, mips_clockevent_device);
39 int cp0_timer_irq_installed;
40
c0_compare_interrupt(int irq,void * dev_id)41 irqreturn_t c0_compare_interrupt(int irq, void *dev_id)
42 {
43 const int r2 = cpu_has_mips_r2_r6;
44 struct clock_event_device *cd;
45 int cpu = smp_processor_id();
46
47 /*
48 * Suckage alert:
49 * Before R2 of the architecture there was no way to see if a
50 * performance counter interrupt was pending, so we have to run
51 * the performance counter interrupt handler anyway.
52 */
53 if (handle_perf_irq(r2))
54 return IRQ_HANDLED;
55
56 /*
57 * The same applies to performance counter interrupts. But with the
58 * above we now know that the reason we got here must be a timer
59 * interrupt. Being the paranoiacs we are we check anyway.
60 */
61 if (!r2 || (read_c0_cause() & (1 << 30))) {
62 /* Clear Count/Compare Interrupt */
63 write_c0_compare(read_c0_compare());
64 cd = &per_cpu(mips_clockevent_device, cpu);
65 cd->event_handler(cd);
66
67 return IRQ_HANDLED;
68 }
69
70 return IRQ_NONE;
71 }
72
73 struct irqaction c0_compare_irqaction = {
74 .handler = c0_compare_interrupt,
75 /*
76 * IRQF_SHARED: The timer interrupt may be shared with other interrupts
77 * such as perf counter and FDC interrupts.
78 */
79 .flags = IRQF_PERCPU | IRQF_TIMER | IRQF_SHARED,
80 .name = "timer",
81 };
82
83
mips_event_handler(struct clock_event_device * dev)84 void mips_event_handler(struct clock_event_device *dev)
85 {
86 }
87
88 /*
89 * FIXME: This doesn't hold for the relocated E9000 compare interrupt.
90 */
c0_compare_int_pending(void)91 static int c0_compare_int_pending(void)
92 {
93 #ifdef CONFIG_IRQ_GIC
94 if (cpu_has_veic)
95 return gic_get_timer_pending();
96 #endif
97 return (read_c0_cause() >> cp0_compare_irq_shift) & (1ul << CAUSEB_IP);
98 }
99
100 /*
101 * Compare interrupt can be routed and latched outside the core,
102 * so wait up to worst case number of cycle counter ticks for timer interrupt
103 * changes to propagate to the cause register.
104 */
105 #define COMPARE_INT_SEEN_TICKS 50
106
c0_compare_int_usable(void)107 int c0_compare_int_usable(void)
108 {
109 unsigned int delta;
110 unsigned int cnt;
111
112 #ifdef CONFIG_KVM_GUEST
113 return 1;
114 #endif
115
116 /*
117 * IP7 already pending? Try to clear it by acking the timer.
118 */
119 if (c0_compare_int_pending()) {
120 cnt = read_c0_count();
121 write_c0_compare(cnt);
122 back_to_back_c0_hazard();
123 while (read_c0_count() < (cnt + COMPARE_INT_SEEN_TICKS))
124 if (!c0_compare_int_pending())
125 break;
126 if (c0_compare_int_pending())
127 return 0;
128 }
129
130 for (delta = 0x10; delta <= 0x400000; delta <<= 1) {
131 cnt = read_c0_count();
132 cnt += delta;
133 write_c0_compare(cnt);
134 back_to_back_c0_hazard();
135 if ((int)(read_c0_count() - cnt) < 0)
136 break;
137 /* increase delta if the timer was already expired */
138 }
139
140 while ((int)(read_c0_count() - cnt) <= 0)
141 ; /* Wait for expiry */
142
143 while (read_c0_count() < (cnt + COMPARE_INT_SEEN_TICKS))
144 if (c0_compare_int_pending())
145 break;
146 if (!c0_compare_int_pending())
147 return 0;
148 cnt = read_c0_count();
149 write_c0_compare(cnt);
150 back_to_back_c0_hazard();
151 while (read_c0_count() < (cnt + COMPARE_INT_SEEN_TICKS))
152 if (!c0_compare_int_pending())
153 break;
154 if (c0_compare_int_pending())
155 return 0;
156
157 /*
158 * Feels like a real count / compare timer.
159 */
160 return 1;
161 }
162
r4k_clockevent_init(void)163 int r4k_clockevent_init(void)
164 {
165 unsigned int cpu = smp_processor_id();
166 struct clock_event_device *cd;
167 unsigned int irq;
168
169 if (!cpu_has_counter || !mips_hpt_frequency)
170 return -ENXIO;
171
172 if (!c0_compare_int_usable())
173 return -ENXIO;
174
175 /*
176 * With vectored interrupts things are getting platform specific.
177 * get_c0_compare_int is a hook to allow a platform to return the
178 * interrupt number of it's liking.
179 */
180 irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq;
181 if (get_c0_compare_int)
182 irq = get_c0_compare_int();
183
184 cd = &per_cpu(mips_clockevent_device, cpu);
185
186 cd->name = "MIPS";
187 cd->features = CLOCK_EVT_FEAT_ONESHOT |
188 CLOCK_EVT_FEAT_C3STOP |
189 CLOCK_EVT_FEAT_PERCPU;
190
191 clockevent_set_clock(cd, mips_hpt_frequency);
192
193 /* Calculate the min / max delta */
194 cd->max_delta_ns = clockevent_delta2ns(0x7fffffff, cd);
195 cd->min_delta_ns = clockevent_delta2ns(0x300, cd);
196
197 cd->rating = 300;
198 cd->irq = irq;
199 cd->cpumask = cpumask_of(cpu);
200 cd->set_next_event = mips_next_event;
201 cd->set_mode = mips_set_clock_mode;
202 cd->event_handler = mips_event_handler;
203
204 clockevents_register_device(cd);
205
206 if (cp0_timer_irq_installed)
207 return 0;
208
209 cp0_timer_irq_installed = 1;
210
211 setup_irq(irq, &c0_compare_irqaction);
212
213 return 0;
214 }
215
216