1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Code to handle x86 style IRQs plus some generic interrupt stuff.
7 *
8 * Copyright (C) 1992 Linus Torvalds
9 * Copyright (C) 1994 - 2000 Ralf Baechle
10 */
11 #include <linux/delay.h>
12 #include <linux/init.h>
13 #include <linux/ioport.h>
14 #include <linux/interrupt.h>
15 #include <linux/kernel.h>
16 #include <linux/spinlock.h>
17 #include <linux/syscore_ops.h>
18 #include <linux/irq.h>
19
20 #include <asm/i8259.h>
21 #include <asm/io.h>
22
23 /*
24 * This is the 'legacy' 8259A Programmable Interrupt Controller,
25 * present in the majority of PC/AT boxes.
26 * plus some generic x86 specific things if generic specifics makes
27 * any sense at all.
28 * this file should become arch/i386/kernel/irq.c when the old irq.c
29 * moves to arch independent land
30 */
31
32 static int i8259A_auto_eoi = -1;
33 DEFINE_RAW_SPINLOCK(i8259A_lock);
34 static void disable_8259A_irq(struct irq_data *d);
35 static void enable_8259A_irq(struct irq_data *d);
36 static void mask_and_ack_8259A(struct irq_data *d);
37 static void init_8259A(int auto_eoi);
38
39 static struct irq_chip i8259A_chip = {
40 .name = "XT-PIC",
41 .irq_mask = disable_8259A_irq,
42 .irq_disable = disable_8259A_irq,
43 .irq_unmask = enable_8259A_irq,
44 .irq_mask_ack = mask_and_ack_8259A,
45 };
46
47 /*
48 * 8259A PIC functions to handle ISA devices:
49 */
50
51 /*
52 * This contains the irq mask for both 8259A irq controllers,
53 */
54 static unsigned int cached_irq_mask = 0xffff;
55
56 #define cached_master_mask (cached_irq_mask)
57 #define cached_slave_mask (cached_irq_mask >> 8)
58
disable_8259A_irq(struct irq_data * d)59 static void disable_8259A_irq(struct irq_data *d)
60 {
61 unsigned int mask, irq = d->irq - I8259A_IRQ_BASE;
62 unsigned long flags;
63
64 mask = 1 << irq;
65 raw_spin_lock_irqsave(&i8259A_lock, flags);
66 cached_irq_mask |= mask;
67 if (irq & 8)
68 outb(cached_slave_mask, PIC_SLAVE_IMR);
69 else
70 outb(cached_master_mask, PIC_MASTER_IMR);
71 raw_spin_unlock_irqrestore(&i8259A_lock, flags);
72 }
73
enable_8259A_irq(struct irq_data * d)74 static void enable_8259A_irq(struct irq_data *d)
75 {
76 unsigned int mask, irq = d->irq - I8259A_IRQ_BASE;
77 unsigned long flags;
78
79 mask = ~(1 << irq);
80 raw_spin_lock_irqsave(&i8259A_lock, flags);
81 cached_irq_mask &= mask;
82 if (irq & 8)
83 outb(cached_slave_mask, PIC_SLAVE_IMR);
84 else
85 outb(cached_master_mask, PIC_MASTER_IMR);
86 raw_spin_unlock_irqrestore(&i8259A_lock, flags);
87 }
88
i8259A_irq_pending(unsigned int irq)89 int i8259A_irq_pending(unsigned int irq)
90 {
91 unsigned int mask;
92 unsigned long flags;
93 int ret;
94
95 irq -= I8259A_IRQ_BASE;
96 mask = 1 << irq;
97 raw_spin_lock_irqsave(&i8259A_lock, flags);
98 if (irq < 8)
99 ret = inb(PIC_MASTER_CMD) & mask;
100 else
101 ret = inb(PIC_SLAVE_CMD) & (mask >> 8);
102 raw_spin_unlock_irqrestore(&i8259A_lock, flags);
103
104 return ret;
105 }
106
make_8259A_irq(unsigned int irq)107 void make_8259A_irq(unsigned int irq)
108 {
109 disable_irq_nosync(irq);
110 irq_set_chip_and_handler(irq, &i8259A_chip, handle_level_irq);
111 enable_irq(irq);
112 }
113
114 /*
115 * This function assumes to be called rarely. Switching between
116 * 8259A registers is slow.
117 * This has to be protected by the irq controller spinlock
118 * before being called.
119 */
i8259A_irq_real(unsigned int irq)120 static inline int i8259A_irq_real(unsigned int irq)
121 {
122 int value;
123 int irqmask = 1 << irq;
124
125 if (irq < 8) {
126 outb(0x0B, PIC_MASTER_CMD); /* ISR register */
127 value = inb(PIC_MASTER_CMD) & irqmask;
128 outb(0x0A, PIC_MASTER_CMD); /* back to the IRR register */
129 return value;
130 }
131 outb(0x0B, PIC_SLAVE_CMD); /* ISR register */
132 value = inb(PIC_SLAVE_CMD) & (irqmask >> 8);
133 outb(0x0A, PIC_SLAVE_CMD); /* back to the IRR register */
134 return value;
135 }
136
137 /*
138 * Careful! The 8259A is a fragile beast, it pretty
139 * much _has_ to be done exactly like this (mask it
140 * first, _then_ send the EOI, and the order of EOI
141 * to the two 8259s is important!
142 */
mask_and_ack_8259A(struct irq_data * d)143 static void mask_and_ack_8259A(struct irq_data *d)
144 {
145 unsigned int irqmask, irq = d->irq - I8259A_IRQ_BASE;
146 unsigned long flags;
147
148 irqmask = 1 << irq;
149 raw_spin_lock_irqsave(&i8259A_lock, flags);
150 /*
151 * Lightweight spurious IRQ detection. We do not want
152 * to overdo spurious IRQ handling - it's usually a sign
153 * of hardware problems, so we only do the checks we can
154 * do without slowing down good hardware unnecessarily.
155 *
156 * Note that IRQ7 and IRQ15 (the two spurious IRQs
157 * usually resulting from the 8259A-1|2 PICs) occur
158 * even if the IRQ is masked in the 8259A. Thus we
159 * can check spurious 8259A IRQs without doing the
160 * quite slow i8259A_irq_real() call for every IRQ.
161 * This does not cover 100% of spurious interrupts,
162 * but should be enough to warn the user that there
163 * is something bad going on ...
164 */
165 if (cached_irq_mask & irqmask)
166 goto spurious_8259A_irq;
167 cached_irq_mask |= irqmask;
168
169 handle_real_irq:
170 if (irq & 8) {
171 inb(PIC_SLAVE_IMR); /* DUMMY - (do we need this?) */
172 outb(cached_slave_mask, PIC_SLAVE_IMR);
173 outb(0x60+(irq&7), PIC_SLAVE_CMD);/* 'Specific EOI' to slave */
174 outb(0x60+PIC_CASCADE_IR, PIC_MASTER_CMD); /* 'Specific EOI' to master-IRQ2 */
175 } else {
176 inb(PIC_MASTER_IMR); /* DUMMY - (do we need this?) */
177 outb(cached_master_mask, PIC_MASTER_IMR);
178 outb(0x60+irq, PIC_MASTER_CMD); /* 'Specific EOI to master */
179 }
180 raw_spin_unlock_irqrestore(&i8259A_lock, flags);
181 return;
182
183 spurious_8259A_irq:
184 /*
185 * this is the slow path - should happen rarely.
186 */
187 if (i8259A_irq_real(irq))
188 /*
189 * oops, the IRQ _is_ in service according to the
190 * 8259A - not spurious, go handle it.
191 */
192 goto handle_real_irq;
193
194 {
195 static int spurious_irq_mask;
196 /*
197 * At this point we can be sure the IRQ is spurious,
198 * lets ACK and report it. [once per IRQ]
199 */
200 if (!(spurious_irq_mask & irqmask)) {
201 printk(KERN_DEBUG "spurious 8259A interrupt: IRQ%d.\n", irq);
202 spurious_irq_mask |= irqmask;
203 }
204 atomic_inc(&irq_err_count);
205 /*
206 * Theoretically we do not have to handle this IRQ,
207 * but in Linux this does not cause problems and is
208 * simpler for us.
209 */
210 goto handle_real_irq;
211 }
212 }
213
i8259A_resume(void)214 static void i8259A_resume(void)
215 {
216 if (i8259A_auto_eoi >= 0)
217 init_8259A(i8259A_auto_eoi);
218 }
219
i8259A_shutdown(void)220 static void i8259A_shutdown(void)
221 {
222 /* Put the i8259A into a quiescent state that
223 * the kernel initialization code can get it
224 * out of.
225 */
226 if (i8259A_auto_eoi >= 0) {
227 outb(0xff, PIC_MASTER_IMR); /* mask all of 8259A-1 */
228 outb(0xff, PIC_SLAVE_IMR); /* mask all of 8259A-2 */
229 }
230 }
231
232 static struct syscore_ops i8259_syscore_ops = {
233 .resume = i8259A_resume,
234 .shutdown = i8259A_shutdown,
235 };
236
i8259A_init_sysfs(void)237 static int __init i8259A_init_sysfs(void)
238 {
239 register_syscore_ops(&i8259_syscore_ops);
240 return 0;
241 }
242
243 device_initcall(i8259A_init_sysfs);
244
init_8259A(int auto_eoi)245 static void init_8259A(int auto_eoi)
246 {
247 unsigned long flags;
248
249 i8259A_auto_eoi = auto_eoi;
250
251 raw_spin_lock_irqsave(&i8259A_lock, flags);
252
253 outb(0xff, PIC_MASTER_IMR); /* mask all of 8259A-1 */
254 outb(0xff, PIC_SLAVE_IMR); /* mask all of 8259A-2 */
255
256 /*
257 * outb_p - this has to work on a wide range of PC hardware.
258 */
259 outb_p(0x11, PIC_MASTER_CMD); /* ICW1: select 8259A-1 init */
260 outb_p(I8259A_IRQ_BASE + 0, PIC_MASTER_IMR); /* ICW2: 8259A-1 IR0 mapped to I8259A_IRQ_BASE + 0x00 */
261 outb_p(1U << PIC_CASCADE_IR, PIC_MASTER_IMR); /* 8259A-1 (the master) has a slave on IR2 */
262 if (auto_eoi) /* master does Auto EOI */
263 outb_p(MASTER_ICW4_DEFAULT | PIC_ICW4_AEOI, PIC_MASTER_IMR);
264 else /* master expects normal EOI */
265 outb_p(MASTER_ICW4_DEFAULT, PIC_MASTER_IMR);
266
267 outb_p(0x11, PIC_SLAVE_CMD); /* ICW1: select 8259A-2 init */
268 outb_p(I8259A_IRQ_BASE + 8, PIC_SLAVE_IMR); /* ICW2: 8259A-2 IR0 mapped to I8259A_IRQ_BASE + 0x08 */
269 outb_p(PIC_CASCADE_IR, PIC_SLAVE_IMR); /* 8259A-2 is a slave on master's IR2 */
270 outb_p(SLAVE_ICW4_DEFAULT, PIC_SLAVE_IMR); /* (slave's support for AEOI in flat mode is to be investigated) */
271 if (auto_eoi)
272 /*
273 * In AEOI mode we just have to mask the interrupt
274 * when acking.
275 */
276 i8259A_chip.irq_mask_ack = disable_8259A_irq;
277 else
278 i8259A_chip.irq_mask_ack = mask_and_ack_8259A;
279
280 udelay(100); /* wait for 8259A to initialize */
281
282 outb(cached_master_mask, PIC_MASTER_IMR); /* restore master IRQ mask */
283 outb(cached_slave_mask, PIC_SLAVE_IMR); /* restore slave IRQ mask */
284
285 raw_spin_unlock_irqrestore(&i8259A_lock, flags);
286 }
287
288 /*
289 * IRQ2 is cascade interrupt to second interrupt controller
290 */
291 static struct irqaction irq2 = {
292 .handler = no_action,
293 .name = "cascade",
294 .flags = IRQF_NO_THREAD,
295 };
296
297 static struct resource pic1_io_resource = {
298 .name = "pic1",
299 .start = PIC_MASTER_CMD,
300 .end = PIC_MASTER_IMR,
301 .flags = IORESOURCE_BUSY
302 };
303
304 static struct resource pic2_io_resource = {
305 .name = "pic2",
306 .start = PIC_SLAVE_CMD,
307 .end = PIC_SLAVE_IMR,
308 .flags = IORESOURCE_BUSY
309 };
310
311 /*
312 * On systems with i8259-style interrupt controllers we assume for
313 * driver compatibility reasons interrupts 0 - 15 to be the i8259
314 * interrupts even if the hardware uses a different interrupt numbering.
315 */
init_i8259_irqs(void)316 void __init init_i8259_irqs(void)
317 {
318 int i;
319
320 insert_resource(&ioport_resource, &pic1_io_resource);
321 insert_resource(&ioport_resource, &pic2_io_resource);
322
323 init_8259A(0);
324
325 for (i = I8259A_IRQ_BASE; i < I8259A_IRQ_BASE + 16; i++) {
326 irq_set_chip_and_handler(i, &i8259A_chip, handle_level_irq);
327 irq_set_probe(i);
328 }
329
330 setup_irq(I8259A_IRQ_BASE + PIC_CASCADE_IR, &irq2);
331 }
332