1 /*
2 * Copyright (C) 1995, 1996, 2001 Ralf Baechle
3 * Copyright (C) 2001, 2004 MIPS Technologies, Inc.
4 * Copyright (C) 2004 Maciej W. Rozycki
5 */
6 #include <linux/delay.h>
7 #include <linux/kernel.h>
8 #include <linux/sched.h>
9 #include <linux/seq_file.h>
10 #include <asm/bootinfo.h>
11 #include <asm/cpu.h>
12 #include <asm/cpu-features.h>
13 #include <asm/idle.h>
14 #include <asm/mipsregs.h>
15 #include <asm/processor.h>
16 #include <asm/prom.h>
17
18 unsigned int vced_count, vcei_count;
19
20 /*
21 * * No lock; only written during early bootup by CPU 0.
22 * */
23 static RAW_NOTIFIER_HEAD(proc_cpuinfo_chain);
24
register_proc_cpuinfo_notifier(struct notifier_block * nb)25 int __ref register_proc_cpuinfo_notifier(struct notifier_block *nb)
26 {
27 return raw_notifier_chain_register(&proc_cpuinfo_chain, nb);
28 }
29
proc_cpuinfo_notifier_call_chain(unsigned long val,void * v)30 int proc_cpuinfo_notifier_call_chain(unsigned long val, void *v)
31 {
32 return raw_notifier_call_chain(&proc_cpuinfo_chain, val, v);
33 }
34
show_cpuinfo(struct seq_file * m,void * v)35 static int show_cpuinfo(struct seq_file *m, void *v)
36 {
37 struct proc_cpuinfo_notifier_args proc_cpuinfo_notifier_args;
38 unsigned long n = (unsigned long) v - 1;
39 unsigned int version = cpu_data[n].processor_id;
40 unsigned int fp_vers = cpu_data[n].fpu_id;
41 char fmt [64];
42 int i;
43
44 #ifdef CONFIG_SMP
45 if (!cpu_online(n))
46 return 0;
47 #endif
48
49 /*
50 * For the first processor also print the system type
51 */
52 if (n == 0) {
53 seq_printf(m, "system type\t\t: %s\n", get_system_type());
54 #ifndef CONFIG_GOLDFISH
55 if (mips_get_machine_name())
56 seq_printf(m, "machine\t\t\t: %s\n",
57 mips_get_machine_name());
58 #else
59 /*
60 * This is needed by the Android init process to run
61 * target specific startup code
62 */
63 seq_printf(m, "Hardware\t\t: %s\n", mips_get_machine_name());
64 seq_printf(m, "Revison\t\t\t: %d\n", 1);
65 #endif
66
67 }
68
69 seq_printf(m, "processor\t\t: %ld\n", n);
70 sprintf(fmt, "cpu model\t\t: %%s V%%d.%%d%s\n",
71 cpu_data[n].options & MIPS_CPU_FPU ? " FPU V%d.%d" : "");
72 seq_printf(m, fmt, __cpu_name[n],
73 (version >> 4) & 0x0f, version & 0x0f,
74 (fp_vers >> 4) & 0x0f, fp_vers & 0x0f);
75 seq_printf(m, "BogoMIPS\t\t: %u.%02u\n",
76 cpu_data[n].udelay_val / (500000/HZ),
77 (cpu_data[n].udelay_val / (5000/HZ)) % 100);
78 seq_printf(m, "wait instruction\t: %s\n", cpu_wait ? "yes" : "no");
79 seq_printf(m, "microsecond timers\t: %s\n",
80 cpu_has_counter ? "yes" : "no");
81 seq_printf(m, "tlb_entries\t\t: %d\n", cpu_data[n].tlbsize);
82 seq_printf(m, "extra interrupt vector\t: %s\n",
83 cpu_has_divec ? "yes" : "no");
84 seq_printf(m, "hardware watchpoint\t: %s",
85 cpu_has_watch ? "yes, " : "no\n");
86 if (cpu_has_watch) {
87 seq_printf(m, "count: %d, address/irw mask: [",
88 cpu_data[n].watch_reg_count);
89 for (i = 0; i < cpu_data[n].watch_reg_count; i++)
90 seq_printf(m, "%s0x%04x", i ? ", " : "" ,
91 cpu_data[n].watch_reg_masks[i]);
92 seq_printf(m, "]\n");
93 }
94
95 seq_printf(m, "isa\t\t\t:");
96 if (cpu_has_mips_r1)
97 seq_printf(m, " mips1");
98 if (cpu_has_mips_2)
99 seq_printf(m, "%s", " mips2");
100 if (cpu_has_mips_3)
101 seq_printf(m, "%s", " mips3");
102 if (cpu_has_mips_4)
103 seq_printf(m, "%s", " mips4");
104 if (cpu_has_mips_5)
105 seq_printf(m, "%s", " mips5");
106 if (cpu_has_mips32r1)
107 seq_printf(m, "%s", " mips32r1");
108 if (cpu_has_mips32r2)
109 seq_printf(m, "%s", " mips32r2");
110 if (cpu_has_mips32r6)
111 seq_printf(m, "%s", " mips32r6");
112 if (cpu_has_mips64r1)
113 seq_printf(m, "%s", " mips64r1");
114 if (cpu_has_mips64r2)
115 seq_printf(m, "%s", " mips64r2");
116 if (cpu_has_mips64r6)
117 seq_printf(m, "%s", " mips64r6");
118 seq_printf(m, "\n");
119
120 seq_printf(m, "ASEs implemented\t:");
121 if (cpu_has_mips16) seq_printf(m, "%s", " mips16");
122 if (cpu_has_mdmx) seq_printf(m, "%s", " mdmx");
123 if (cpu_has_mips3d) seq_printf(m, "%s", " mips3d");
124 if (cpu_has_smartmips) seq_printf(m, "%s", " smartmips");
125 if (cpu_has_dsp) seq_printf(m, "%s", " dsp");
126 if (cpu_has_dsp2) seq_printf(m, "%s", " dsp2");
127 if (cpu_has_mipsmt) seq_printf(m, "%s", " mt");
128 if (cpu_has_mmips) seq_printf(m, "%s", " micromips");
129 if (cpu_has_vz) seq_printf(m, "%s", " vz");
130 if (cpu_has_msa) seq_printf(m, "%s", " msa");
131 if (cpu_has_eva) seq_printf(m, "%s", " eva");
132 if (cpu_has_htw) seq_printf(m, "%s", " htw");
133 if (cpu_has_xpa) seq_printf(m, "%s", " xpa");
134 seq_printf(m, "\n");
135
136 if (cpu_has_mmips) {
137 seq_printf(m, "micromips kernel\t: %s\n",
138 (read_c0_config3() & MIPS_CONF3_ISA_OE) ? "yes" : "no");
139 }
140 seq_printf(m, "shadow register sets\t: %d\n",
141 cpu_data[n].srsets);
142 seq_printf(m, "kscratch registers\t: %d\n",
143 hweight8(cpu_data[n].kscratch_mask));
144 seq_printf(m, "package\t\t\t: %d\n", cpu_data[n].package);
145 seq_printf(m, "core\t\t\t: %d\n", cpu_data[n].core);
146
147 sprintf(fmt, "VCE%%c exceptions\t\t: %s\n",
148 cpu_has_vce ? "%u" : "not available");
149 seq_printf(m, fmt, 'D', vced_count);
150 seq_printf(m, fmt, 'I', vcei_count);
151
152 proc_cpuinfo_notifier_args.m = m;
153 proc_cpuinfo_notifier_args.n = n;
154
155 raw_notifier_call_chain(&proc_cpuinfo_chain, 0,
156 &proc_cpuinfo_notifier_args);
157
158 seq_printf(m, "\n");
159
160 return 0;
161 }
162
c_start(struct seq_file * m,loff_t * pos)163 static void *c_start(struct seq_file *m, loff_t *pos)
164 {
165 unsigned long i = *pos;
166
167 return i < NR_CPUS ? (void *) (i + 1) : NULL;
168 }
169
c_next(struct seq_file * m,void * v,loff_t * pos)170 static void *c_next(struct seq_file *m, void *v, loff_t *pos)
171 {
172 ++*pos;
173 return c_start(m, pos);
174 }
175
c_stop(struct seq_file * m,void * v)176 static void c_stop(struct seq_file *m, void *v)
177 {
178 }
179
180 const struct seq_operations cpuinfo_op = {
181 .start = c_start,
182 .next = c_next,
183 .stop = c_stop,
184 .show = show_cpuinfo,
185 };
186