1 #include <linux/init.h>
2 #include <linux/pci.h>
3 #include <asm/mips-boards/piix4.h>
4
5 /* PCI interrupt pins */
6 #define PCIA 1
7 #define PCIB 2
8 #define PCIC 3
9 #define PCID 4
10
11 /* This table is filled in by interrogating the PIIX4 chip */
12 static char pci_irq[5] = {
13 };
14
15 static char irq_tab[][5] __initdata = {
16 /* INTA INTB INTC INTD */
17 {0, 0, 0, 0, 0 }, /* 0: GT64120 PCI bridge */
18 {0, 0, 0, 0, 0 }, /* 1: Unused */
19 {0, 0, 0, 0, 0 }, /* 2: Unused */
20 {0, 0, 0, 0, 0 }, /* 3: Unused */
21 {0, 0, 0, 0, 0 }, /* 4: Unused */
22 {0, 0, 0, 0, 0 }, /* 5: Unused */
23 {0, 0, 0, 0, 0 }, /* 6: Unused */
24 {0, 0, 0, 0, 0 }, /* 7: Unused */
25 {0, 0, 0, 0, 0 }, /* 8: Unused */
26 {0, 0, 0, 0, 0 }, /* 9: Unused */
27 {0, 0, 0, 0, PCID }, /* 10: PIIX4 USB */
28 {0, PCIB, 0, 0, 0 }, /* 11: AMD 79C973 Ethernet */
29 {0, PCIC, 0, 0, 0 }, /* 12: Crystal 4281 Sound */
30 {0, 0, 0, 0, 0 }, /* 13: Unused */
31 {0, 0, 0, 0, 0 }, /* 14: Unused */
32 {0, 0, 0, 0, 0 }, /* 15: Unused */
33 {0, 0, 0, 0, 0 }, /* 16: Unused */
34 {0, 0, 0, 0, 0 }, /* 17: Bonito/SOC-it PCI Bridge*/
35 {0, PCIA, PCIB, PCIC, PCID }, /* 18: PCI Slot 1 */
36 {0, PCIB, PCIC, PCID, PCIA }, /* 19: PCI Slot 2 */
37 {0, PCIC, PCID, PCIA, PCIB }, /* 20: PCI Slot 3 */
38 {0, PCID, PCIA, PCIB, PCIC } /* 21: PCI Slot 4 */
39 };
40
pcibios_map_irq(const struct pci_dev * dev,u8 slot,u8 pin)41 int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
42 {
43 int virq;
44 virq = irq_tab[slot][pin];
45 return pci_irq[virq];
46 }
47
48 /* Do platform specific device initialization at pci_enable_device() time */
pcibios_plat_dev_init(struct pci_dev * dev)49 int pcibios_plat_dev_init(struct pci_dev *dev)
50 {
51 return 0;
52 }
53
malta_piix_func3_base_fixup(struct pci_dev * dev)54 static void malta_piix_func3_base_fixup(struct pci_dev *dev)
55 {
56 /* Set a sane PM I/O base address */
57 pci_write_config_word(dev, PIIX4_FUNC3_PMBA, 0x1000);
58
59 /* Enable access to the PM I/O region */
60 pci_write_config_byte(dev, PIIX4_FUNC3_PMREGMISC,
61 PIIX4_FUNC3_PMREGMISC_EN);
62 }
63
64 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3,
65 malta_piix_func3_base_fixup);
66
malta_piix_func0_fixup(struct pci_dev * pdev)67 static void malta_piix_func0_fixup(struct pci_dev *pdev)
68 {
69 unsigned char reg_val;
70 u32 reg_val32;
71 u16 reg_val16;
72 /* PIIX PIRQC[A:D] irq mappings */
73 static int piixirqmap[PIIX4_FUNC0_PIRQRC_IRQ_ROUTING_MAX] = {
74 0, 0, 0, 3,
75 4, 5, 6, 7,
76 0, 9, 10, 11,
77 12, 0, 14, 15
78 };
79 int i;
80
81 /* Interrogate PIIX4 to get PCI IRQ mapping */
82 for (i = 0; i <= 3; i++) {
83 pci_read_config_byte(pdev, PIIX4_FUNC0_PIRQRC+i, ®_val);
84 if (reg_val & PIIX4_FUNC0_PIRQRC_IRQ_ROUTING_DISABLE)
85 pci_irq[PCIA+i] = 0; /* Disabled */
86 else
87 pci_irq[PCIA+i] = piixirqmap[reg_val &
88 PIIX4_FUNC0_PIRQRC_IRQ_ROUTING_MASK];
89 }
90
91 /* Done by YAMON 2.00 onwards */
92 if (PCI_SLOT(pdev->devfn) == 10) {
93 /*
94 * Set top of main memory accessible by ISA or DMA
95 * devices to 16 Mb.
96 */
97 pci_read_config_byte(pdev, PIIX4_FUNC0_TOM, ®_val);
98 pci_write_config_byte(pdev, PIIX4_FUNC0_TOM, reg_val |
99 PIIX4_FUNC0_TOM_TOP_OF_MEMORY_MASK);
100 }
101
102 /* Mux SERIRQ to its pin */
103 pci_read_config_dword(pdev, PIIX4_FUNC0_GENCFG, ®_val32);
104 pci_write_config_dword(pdev, PIIX4_FUNC0_GENCFG,
105 reg_val32 | PIIX4_FUNC0_GENCFG_SERIRQ);
106
107 /* Enable SERIRQ */
108 pci_read_config_byte(pdev, PIIX4_FUNC0_SERIRQC, ®_val);
109 reg_val |= PIIX4_FUNC0_SERIRQC_EN | PIIX4_FUNC0_SERIRQC_CONT;
110 pci_write_config_byte(pdev, PIIX4_FUNC0_SERIRQC, reg_val);
111
112 /* Enable response to special cycles */
113 pci_read_config_word(pdev, PCI_COMMAND, ®_val16);
114 pci_write_config_word(pdev, PCI_COMMAND,
115 reg_val16 | PCI_COMMAND_SPECIAL);
116 }
117
118 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_0,
119 malta_piix_func0_fixup);
120
malta_piix_func1_fixup(struct pci_dev * pdev)121 static void malta_piix_func1_fixup(struct pci_dev *pdev)
122 {
123 unsigned char reg_val;
124
125 /* Done by YAMON 2.02 onwards */
126 if (PCI_SLOT(pdev->devfn) == 10) {
127 /*
128 * IDE Decode enable.
129 */
130 pci_read_config_byte(pdev, PIIX4_FUNC1_IDETIM_PRIMARY_HI,
131 ®_val);
132 pci_write_config_byte(pdev, PIIX4_FUNC1_IDETIM_PRIMARY_HI,
133 reg_val|PIIX4_FUNC1_IDETIM_PRIMARY_HI_IDE_DECODE_EN);
134 pci_read_config_byte(pdev, PIIX4_FUNC1_IDETIM_SECONDARY_HI,
135 ®_val);
136 pci_write_config_byte(pdev, PIIX4_FUNC1_IDETIM_SECONDARY_HI,
137 reg_val|PIIX4_FUNC1_IDETIM_SECONDARY_HI_IDE_DECODE_EN);
138 }
139 }
140
141 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB,
142 malta_piix_func1_fixup);
143
144 /* Enable PCI 2.1 compatibility in PIIX4 */
quirk_dlcsetup(struct pci_dev * dev)145 static void quirk_dlcsetup(struct pci_dev *dev)
146 {
147 u8 odlc, ndlc;
148
149 (void) pci_read_config_byte(dev, PIIX4_FUNC0_DLC, &odlc);
150 /* Enable passive releases and delayed transaction */
151 ndlc = odlc | PIIX4_FUNC0_DLC_USBPR_EN |
152 PIIX4_FUNC0_DLC_PASSIVE_RELEASE_EN |
153 PIIX4_FUNC0_DLC_DELAYED_TRANSACTION_EN;
154 (void) pci_write_config_byte(dev, PIIX4_FUNC0_DLC, ndlc);
155 }
156
157 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_0,
158 quirk_dlcsetup);
159