1/* 2 * MPC8569E MDS Device Tree Source 3 * 4 * Copyright (C) 2009 Freescale Semiconductor Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by the 8 * Free Software Foundation; either version 2 of the License, or (at your 9 * option) any later version. 10 */ 11 12/include/ "fsl/mpc8569si-pre.dtsi" 13 14/ { 15 model = "MPC8569EMDS"; 16 compatible = "fsl,MPC8569EMDS"; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 interrupt-parent = <&mpic>; 20 21 aliases { 22 ethernet2 = &enet2; 23 ethernet3 = &enet3; 24 ethernet5 = &enet5; 25 ethernet7 = &enet7; 26 rapidio0 = &rio; 27 }; 28 29 memory { 30 device_type = "memory"; 31 }; 32 33 lbc: localbus@e0005000 { 34 reg = <0x0 0xe0005000 0x0 0x1000>; 35 36 ranges = <0x0 0x0 0x0 0xfe000000 0x02000000 37 0x1 0x0 0x0 0xf8000000 0x00008000 38 0x2 0x0 0x0 0xf0000000 0x04000000 39 0x3 0x0 0x0 0xfc000000 0x00008000 40 0x4 0x0 0x0 0xf8008000 0x00008000 41 0x5 0x0 0x0 0xf8010000 0x00008000>; 42 43 nor@0,0 { 44 #address-cells = <1>; 45 #size-cells = <1>; 46 compatible = "cfi-flash"; 47 reg = <0x0 0x0 0x02000000>; 48 bank-width = <1>; 49 device-width = <1>; 50 partition@0 { 51 label = "ramdisk"; 52 reg = <0x00000000 0x01c00000>; 53 }; 54 partition@1c00000 { 55 label = "kernel"; 56 reg = <0x01c00000 0x002e0000>; 57 }; 58 partiton@1ee0000 { 59 label = "dtb"; 60 reg = <0x01ee0000 0x00020000>; 61 }; 62 partition@1f00000 { 63 label = "firmware"; 64 reg = <0x01f00000 0x00080000>; 65 read-only; 66 }; 67 partition@1f80000 { 68 label = "u-boot"; 69 reg = <0x01f80000 0x00080000>; 70 read-only; 71 }; 72 }; 73 74 bcsr@1,0 { 75 #address-cells = <1>; 76 #size-cells = <1>; 77 compatible = "fsl,mpc8569mds-bcsr"; 78 reg = <1 0 0x8000>; 79 ranges = <0 1 0 0x8000>; 80 81 bcsr17: gpio-controller@11 { 82 #gpio-cells = <2>; 83 compatible = "fsl,mpc8569mds-bcsr-gpio"; 84 reg = <0x11 0x1>; 85 gpio-controller; 86 }; 87 }; 88 89 nand@3,0 { 90 compatible = "fsl,mpc8569-fcm-nand", 91 "fsl,elbc-fcm-nand"; 92 reg = <3 0 0x8000>; 93 }; 94 95 pib@4,0 { 96 compatible = "fsl,mpc8569mds-pib"; 97 reg = <4 0 0x8000>; 98 }; 99 100 pib@5,0 { 101 compatible = "fsl,mpc8569mds-pib"; 102 reg = <5 0 0x8000>; 103 }; 104 }; 105 106 soc: soc@e0000000 { 107 ranges = <0x0 0x0 0xe0000000 0x100000>; 108 109 i2c-sleep-nexus { 110 i2c@3000 { 111 rtc@68 { 112 compatible = "dallas,ds1374"; 113 reg = <0x68>; 114 interrupts = <3 1 0 0>; 115 }; 116 }; 117 }; 118 119 sdhc@2e000 { 120 status = "disabled"; 121 sdhci,1-bit-only; 122 bus-width = <1>; 123 }; 124 125 par_io@e0100 { 126 num-ports = <7>; 127 128 qe_pio_e: gpio-controller@80 { 129 #gpio-cells = <2>; 130 compatible = "fsl,mpc8569-qe-pario-bank", 131 "fsl,mpc8323-qe-pario-bank"; 132 reg = <0x80 0x18>; 133 gpio-controller; 134 }; 135 136 qe_pio_f: gpio-controller@a0 { 137 #gpio-cells = <2>; 138 compatible = "fsl,mpc8569-qe-pario-bank", 139 "fsl,mpc8323-qe-pario-bank"; 140 reg = <0xa0 0x18>; 141 gpio-controller; 142 }; 143 144 pio1: ucc_pin@01 { 145 pio-map = < 146 /* port pin dir open_drain assignment has_irq */ 147 0x2 0x1f 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */ 148 0x2 0x1e 0x3 0x0 0x2 0x0 /* QE_MUX_MDIO */ 149 0x2 0x0b 0x2 0x0 0x1 0x0 /* CLK12*/ 150 0x0 0x0 0x1 0x0 0x3 0x0 /* ENET1_TXD0_SER1_TXD0 */ 151 0x0 0x1 0x1 0x0 0x3 0x0 /* ENET1_TXD1_SER1_TXD1 */ 152 0x0 0x2 0x1 0x0 0x1 0x0 /* ENET1_TXD2_SER1_TXD2 */ 153 0x0 0x3 0x1 0x0 0x2 0x0 /* ENET1_TXD3_SER1_TXD3 */ 154 0x0 0x6 0x2 0x0 0x3 0x0 /* ENET1_RXD0_SER1_RXD0 */ 155 0x0 0x7 0x2 0x0 0x1 0x0 /* ENET1_RXD1_SER1_RXD1 */ 156 0x0 0x8 0x2 0x0 0x2 0x0 /* ENET1_RXD2_SER1_RXD2 */ 157 0x0 0x9 0x2 0x0 0x2 0x0 /* ENET1_RXD3_SER1_RXD3 */ 158 0x0 0x4 0x1 0x0 0x2 0x0 /* ENET1_TX_EN_SER1_RTS_B */ 159 0x0 0xc 0x2 0x0 0x3 0x0 /* ENET1_RX_DV_SER1_CTS_B */ 160 0x2 0x8 0x2 0x0 0x1 0x0 /* ENET1_GRXCLK */ 161 0x2 0x14 0x1 0x0 0x2 0x0>; /* ENET1_GTXCLK */ 162 }; 163 164 pio2: ucc_pin@02 { 165 pio-map = < 166 /* port pin dir open_drain assignment has_irq */ 167 0x2 0x1f 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */ 168 0x2 0x1e 0x3 0x0 0x2 0x0 /* QE_MUX_MDIO */ 169 0x2 0x10 0x2 0x0 0x3 0x0 /* CLK17 */ 170 0x0 0xe 0x1 0x0 0x2 0x0 /* ENET2_TXD0_SER2_TXD0 */ 171 0x0 0xf 0x1 0x0 0x2 0x0 /* ENET2_TXD1_SER2_TXD1 */ 172 0x0 0x10 0x1 0x0 0x1 0x0 /* ENET2_TXD2_SER2_TXD2 */ 173 0x0 0x11 0x1 0x0 0x1 0x0 /* ENET2_TXD3_SER2_TXD3 */ 174 0x0 0x14 0x2 0x0 0x2 0x0 /* ENET2_RXD0_SER2_RXD0 */ 175 0x0 0x15 0x2 0x0 0x1 0x0 /* ENET2_RXD1_SER2_RXD1 */ 176 0x0 0x16 0x2 0x0 0x1 0x0 /* ENET2_RXD2_SER2_RXD2 */ 177 0x0 0x17 0x2 0x0 0x1 0x0 /* ENET2_RXD3_SER2_RXD3 */ 178 0x0 0x12 0x1 0x0 0x2 0x0 /* ENET2_TX_EN_SER2_RTS_B */ 179 0x0 0x1a 0x2 0x0 0x3 0x0 /* ENET2_RX_DV_SER2_CTS_B */ 180 0x2 0x3 0x2 0x0 0x1 0x0 /* ENET2_GRXCLK */ 181 0x2 0x2 0x1 0x0 0x2 0x0>; /* ENET2_GTXCLK */ 182 }; 183 184 pio3: ucc_pin@03 { 185 pio-map = < 186 /* port pin dir open_drain assignment has_irq */ 187 0x2 0x1f 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */ 188 0x2 0x1e 0x3 0x0 0x2 0x0 /* QE_MUX_MDIO */ 189 0x2 0x0b 0x2 0x0 0x1 0x0 /* CLK12*/ 190 0x0 0x1d 0x1 0x0 0x2 0x0 /* ENET3_TXD0_SER3_TXD0 */ 191 0x0 0x1e 0x1 0x0 0x3 0x0 /* ENET3_TXD1_SER3_TXD1 */ 192 0x0 0x1f 0x1 0x0 0x2 0x0 /* ENET3_TXD2_SER3_TXD2 */ 193 0x1 0x0 0x1 0x0 0x3 0x0 /* ENET3_TXD3_SER3_TXD3 */ 194 0x1 0x3 0x2 0x0 0x3 0x0 /* ENET3_RXD0_SER3_RXD0 */ 195 0x1 0x4 0x2 0x0 0x1 0x0 /* ENET3_RXD1_SER3_RXD1 */ 196 0x1 0x5 0x2 0x0 0x2 0x0 /* ENET3_RXD2_SER3_RXD2 */ 197 0x1 0x6 0x2 0x0 0x3 0x0 /* ENET3_RXD3_SER3_RXD3 */ 198 0x1 0x1 0x1 0x0 0x1 0x0 /* ENET3_TX_EN_SER3_RTS_B */ 199 0x1 0x9 0x2 0x0 0x3 0x0 /* ENET3_RX_DV_SER3_CTS_B */ 200 0x2 0x9 0x2 0x0 0x2 0x0 /* ENET3_GRXCLK */ 201 0x2 0x19 0x1 0x0 0x2 0x0>; /* ENET3_GTXCLK */ 202 }; 203 204 pio4: ucc_pin@04 { 205 pio-map = < 206 /* port pin dir open_drain assignment has_irq */ 207 0x2 0x1f 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */ 208 0x2 0x1e 0x3 0x0 0x2 0x0 /* QE_MUX_MDIO */ 209 0x2 0x10 0x2 0x0 0x3 0x0 /* CLK17 */ 210 0x1 0xc 0x1 0x0 0x2 0x0 /* ENET4_TXD0_SER4_TXD0 */ 211 0x1 0xd 0x1 0x0 0x2 0x0 /* ENET4_TXD1_SER4_TXD1 */ 212 0x1 0xe 0x1 0x0 0x1 0x0 /* ENET4_TXD2_SER4_TXD2 */ 213 0x1 0xf 0x1 0x0 0x2 0x0 /* ENET4_TXD3_SER4_TXD3 */ 214 0x1 0x12 0x2 0x0 0x2 0x0 /* ENET4_RXD0_SER4_RXD0 */ 215 0x1 0x13 0x2 0x0 0x1 0x0 /* ENET4_RXD1_SER4_RXD1 */ 216 0x1 0x14 0x2 0x0 0x1 0x0 /* ENET4_RXD2_SER4_RXD2 */ 217 0x1 0x15 0x2 0x0 0x2 0x0 /* ENET4_RXD3_SER4_RXD3 */ 218 0x1 0x10 0x1 0x0 0x2 0x0 /* ENET4_TX_EN_SER4_RTS_B */ 219 0x1 0x18 0x2 0x0 0x3 0x0 /* ENET4_RX_DV_SER4_CTS_B */ 220 0x2 0x11 0x2 0x0 0x2 0x0 /* ENET4_GRXCLK */ 221 0x2 0x18 0x1 0x0 0x2 0x0>; /* ENET4_GTXCLK */ 222 }; 223 }; 224 }; 225 226 qe: qe@e0080000 { 227 ranges = <0x0 0x0 0xe0080000 0x40000>; 228 reg = <0x0 0xe0080000 0x0 0x480>; 229 230 spi@4c0 { 231 gpios = <&qe_pio_e 30 0>; 232 mode = "cpu-qe"; 233 234 serial-flash@0 { 235 compatible = "stm,m25p40"; 236 reg = <0>; 237 spi-max-frequency = <25000000>; 238 }; 239 }; 240 241 spi@500 { 242 mode = "cpu"; 243 }; 244 245 usb@6c0 { 246 fsl,fullspeed-clock = "clk5"; 247 fsl,lowspeed-clock = "brg10"; 248 gpios = <&qe_pio_f 3 0 /* USBOE */ 249 &qe_pio_f 4 0 /* USBTP */ 250 &qe_pio_f 5 0 /* USBTN */ 251 &qe_pio_f 6 0 /* USBRP */ 252 &qe_pio_f 8 0 /* USBRN */ 253 &bcsr17 1 0 /* SPEED */ 254 &bcsr17 2 0>; /* POWER */ 255 }; 256 257 enet0: ucc@2000 { 258 device_type = "network"; 259 compatible = "ucc_geth"; 260 local-mac-address = [ 00 00 00 00 00 00 ]; 261 rx-clock-name = "none"; 262 tx-clock-name = "clk12"; 263 pio-handle = <&pio1>; 264 tbi-handle = <&tbi1>; 265 phy-handle = <&qe_phy0>; 266 phy-connection-type = "rgmii-id"; 267 }; 268 269 mdio@2120 { 270 #address-cells = <1>; 271 #size-cells = <0>; 272 reg = <0x2120 0x18>; 273 compatible = "fsl,ucc-mdio"; 274 275 qe_phy0: ethernet-phy@07 { 276 interrupt-parent = <&mpic>; 277 interrupts = <1 1 0 0>; 278 reg = <0x7>; 279 }; 280 qe_phy1: ethernet-phy@01 { 281 interrupt-parent = <&mpic>; 282 interrupts = <2 1 0 0>; 283 reg = <0x1>; 284 }; 285 qe_phy2: ethernet-phy@02 { 286 interrupt-parent = <&mpic>; 287 interrupts = <3 1 0 0>; 288 reg = <0x2>; 289 }; 290 qe_phy3: ethernet-phy@03 { 291 interrupt-parent = <&mpic>; 292 interrupts = <4 1 0 0>; 293 reg = <0x3>; 294 }; 295 qe_phy5: ethernet-phy@04 { 296 reg = <0x04>; 297 }; 298 qe_phy7: ethernet-phy@06 { 299 reg = <0x6>; 300 }; 301 tbi1: tbi-phy@11 { 302 reg = <0x11>; 303 device_type = "tbi-phy"; 304 }; 305 }; 306 mdio@3520 { 307 #address-cells = <1>; 308 #size-cells = <0>; 309 reg = <0x3520 0x18>; 310 compatible = "fsl,ucc-mdio"; 311 312 tbi6: tbi-phy@15 { 313 reg = <0x15>; 314 device_type = "tbi-phy"; 315 }; 316 }; 317 mdio@3720 { 318 #address-cells = <1>; 319 #size-cells = <0>; 320 reg = <0x3720 0x38>; 321 compatible = "fsl,ucc-mdio"; 322 tbi8: tbi-phy@17 { 323 reg = <0x17>; 324 device_type = "tbi-phy"; 325 }; 326 }; 327 328 enet2: ucc@2200 { 329 device_type = "network"; 330 compatible = "ucc_geth"; 331 local-mac-address = [ 00 00 00 00 00 00 ]; 332 rx-clock-name = "none"; 333 tx-clock-name = "clk12"; 334 pio-handle = <&pio3>; 335 tbi-handle = <&tbi3>; 336 phy-handle = <&qe_phy2>; 337 phy-connection-type = "rgmii-id"; 338 }; 339 340 mdio@2320 { 341 #address-cells = <1>; 342 #size-cells = <0>; 343 reg = <0x2320 0x18>; 344 compatible = "fsl,ucc-mdio"; 345 tbi3: tbi-phy@11 { 346 reg = <0x11>; 347 device_type = "tbi-phy"; 348 }; 349 }; 350 351 enet1: ucc@3000 { 352 device_type = "network"; 353 compatible = "ucc_geth"; 354 local-mac-address = [ 00 00 00 00 00 00 ]; 355 rx-clock-name = "none"; 356 tx-clock-name = "clk17"; 357 pio-handle = <&pio2>; 358 tbi-handle = <&tbi2>; 359 phy-handle = <&qe_phy1>; 360 phy-connection-type = "rgmii-id"; 361 }; 362 363 mdio@3120 { 364 #address-cells = <1>; 365 #size-cells = <0>; 366 reg = <0x3120 0x18>; 367 compatible = "fsl,ucc-mdio"; 368 tbi2: tbi-phy@11 { 369 reg = <0x11>; 370 device_type = "tbi-phy"; 371 }; 372 }; 373 374 enet3: ucc@3200 { 375 device_type = "network"; 376 compatible = "ucc_geth"; 377 local-mac-address = [ 00 00 00 00 00 00 ]; 378 rx-clock-name = "none"; 379 tx-clock-name = "clk17"; 380 pio-handle = <&pio4>; 381 tbi-handle = <&tbi4>; 382 phy-handle = <&qe_phy3>; 383 phy-connection-type = "rgmii-id"; 384 }; 385 386 mdio@3320 { 387 #address-cells = <1>; 388 #size-cells = <0>; 389 reg = <0x3320 0x18>; 390 compatible = "fsl,ucc-mdio"; 391 tbi4: tbi-phy@11 { 392 reg = <0x11>; 393 device_type = "tbi-phy"; 394 }; 395 }; 396 397 enet5: ucc@3400 { 398 device_type = "network"; 399 compatible = "ucc_geth"; 400 local-mac-address = [ 00 00 00 00 00 00 ]; 401 rx-clock-name = "none"; 402 tx-clock-name = "none"; 403 tbi-handle = <&tbi6>; 404 phy-handle = <&qe_phy5>; 405 phy-connection-type = "sgmii"; 406 }; 407 408 enet7: ucc@3600 { 409 device_type = "network"; 410 compatible = "ucc_geth"; 411 local-mac-address = [ 00 00 00 00 00 00 ]; 412 rx-clock-name = "none"; 413 tx-clock-name = "none"; 414 tbi-handle = <&tbi8>; 415 phy-handle = <&qe_phy7>; 416 phy-connection-type = "sgmii"; 417 }; 418 }; 419 420 /* PCI Express */ 421 pci1: pcie@e000a000 { 422 reg = <0x0 0xe000a000 0x0 0x1000>; 423 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x10000000 424 0x1000000 0x0 0x00000000 0 0xe2800000 0x0 0x00800000>; 425 pcie@0 { 426 ranges = <0x2000000 0x0 0xa0000000 427 0x2000000 0x0 0xa0000000 428 0x0 0x10000000 429 430 0x1000000 0x0 0x0 431 0x1000000 0x0 0x0 432 0x0 0x800000>; 433 }; 434 }; 435 436 rio: rapidio@e00c00000 { 437 reg = <0x0 0xe00c0000 0x0 0x20000>; 438 port1 { 439 ranges = <0x0 0x0 0x0 0xc0000000 0x0 0x20000000>; 440 }; 441 port2 { 442 status = "disabled"; 443 }; 444 }; 445}; 446 447/include/ "fsl/mpc8569si-post.dtsi" 448