1/* 2 * T104xQDS Device Tree Source 3 * 4 * Copyright 2013 Freescale Semiconductor Inc. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are met: 8 * * Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * * Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * * Neither the name of Freescale Semiconductor nor the 14 * names of its contributors may be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * 18 * ALTERNATIVELY, this software may be distributed under the terms of the 19 * GNU General Public License ("GPL") as published by the Free Software 20 * Foundation, either version 2 of that License or (at your option) any 21 * later version. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY 24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY 27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35/ { 36 model = "fsl,T1040QDS"; 37 #address-cells = <2>; 38 #size-cells = <2>; 39 interrupt-parent = <&mpic>; 40 41 ifc: localbus@ffe124000 { 42 reg = <0xf 0xfe124000 0 0x2000>; 43 ranges = <0 0 0xf 0xe8000000 0x08000000 44 2 0 0xf 0xff800000 0x00010000 45 3 0 0xf 0xffdf0000 0x00008000>; 46 47 nor@0,0 { 48 #address-cells = <1>; 49 #size-cells = <1>; 50 compatible = "cfi-flash"; 51 reg = <0x0 0x0 0x8000000>; 52 53 bank-width = <2>; 54 device-width = <1>; 55 }; 56 57 nand@2,0 { 58 #address-cells = <1>; 59 #size-cells = <1>; 60 compatible = "fsl,ifc-nand"; 61 reg = <0x2 0x0 0x10000>; 62 }; 63 64 board-control@3,0 { 65 #address-cells = <1>; 66 #size-cells = <1>; 67 compatible = "fsl,fpga-qixis"; 68 reg = <3 0 0x300>; 69 }; 70 }; 71 72 memory { 73 device_type = "memory"; 74 }; 75 76 dcsr: dcsr@f00000000 { 77 ranges = <0x00000000 0xf 0x00000000 0x01072000>; 78 }; 79 80 soc: soc@ffe000000 { 81 ranges = <0x00000000 0xf 0xfe000000 0x1000000>; 82 reg = <0xf 0xfe000000 0 0x00001000>; 83 84 spi@110000 { 85 flash@0 { 86 #address-cells = <1>; 87 #size-cells = <1>; 88 compatible = "micron,n25q128a11"; 89 reg = <0>; 90 spi-max-frequency = <10000000>; /* input clock */ 91 }; 92 }; 93 94 i2c@118000 { 95 pca9547@77 { 96 compatible = "philips,pca9547"; 97 reg = <0x77>; 98 }; 99 rtc@68 { 100 compatible = "dallas,ds3232"; 101 reg = <0x68>; 102 interrupts = <0x1 0x1 0 0>; 103 }; 104 }; 105 }; 106 107 pci0: pcie@ffe240000 { 108 reg = <0xf 0xfe240000 0 0x10000>; 109 ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x10000000 110 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>; 111 pcie@0 { 112 ranges = <0x02000000 0 0xe0000000 113 0x02000000 0 0xe0000000 114 0 0x10000000 115 116 0x01000000 0 0x00000000 117 0x01000000 0 0x00000000 118 0 0x00010000>; 119 }; 120 }; 121 122 pci1: pcie@ffe250000 { 123 reg = <0xf 0xfe250000 0 0x10000>; 124 ranges = <0x02000000 0x0 0xe0000000 0xc 0x10000000 0x0 0x10000000 125 0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>; 126 pcie@0 { 127 ranges = <0x02000000 0 0xe0000000 128 0x02000000 0 0xe0000000 129 0 0x10000000 130 131 0x01000000 0 0x00000000 132 0x01000000 0 0x00000000 133 0 0x00010000>; 134 }; 135 }; 136 137 pci2: pcie@ffe260000 { 138 reg = <0xf 0xfe260000 0 0x10000>; 139 ranges = <0x02000000 0 0xe0000000 0xc 0x20000000 0 0x10000000 140 0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>; 141 pcie@0 { 142 ranges = <0x02000000 0 0xe0000000 143 0x02000000 0 0xe0000000 144 0 0x10000000 145 146 0x01000000 0 0x00000000 147 0x01000000 0 0x00000000 148 0 0x00010000>; 149 }; 150 }; 151 152 pci3: pcie@ffe270000 { 153 reg = <0xf 0xfe270000 0 0x10000>; 154 ranges = <0x02000000 0 0xe0000000 0xc 0x30000000 0 0x10000000 155 0x01000000 0 0x00000000 0xf 0xf8030000 0 0x00010000>; 156 pcie@0 { 157 ranges = <0x02000000 0 0xe0000000 158 0x02000000 0 0xe0000000 159 0 0x10000000 160 161 0x01000000 0 0x00000000 162 0x01000000 0 0x00000000 163 0 0x00010000>; 164 }; 165 }; 166}; 167