1 /*
2 * Renesas Technology Corp. SH7786 Urquell Support.
3 *
4 * Copyright (C) 2008 Kuninori Morimoto <morimoto.kuninori@renesas.com>
5 * Copyright (C) 2009, 2010 Paul Mundt
6 *
7 * Based on board-sh7785lcr.c
8 * Copyright (C) 2008 Yoshihiro Shimoda
9 *
10 * This file is subject to the terms and conditions of the GNU General Public
11 * License. See the file "COPYING" in the main directory of this archive
12 * for more details.
13 */
14 #include <linux/init.h>
15 #include <linux/platform_device.h>
16 #include <linux/fb.h>
17 #include <linux/smc91x.h>
18 #include <linux/mtd/physmap.h>
19 #include <linux/delay.h>
20 #include <linux/gpio.h>
21 #include <linux/irq.h>
22 #include <linux/clk.h>
23 #include <linux/sh_intc.h>
24 #include <mach/urquell.h>
25 #include <cpu/sh7786.h>
26 #include <asm/heartbeat.h>
27 #include <asm/sizes.h>
28 #include <asm/smp-ops.h>
29
30 /*
31 * bit 1234 5678
32 *----------------------------
33 * SW1 0101 0010 -> Pck 33MHz version
34 * (1101 0010) Pck 66MHz version
35 * SW2 0x1x xxxx -> little endian
36 * 29bit mode
37 * SW47 0001 1000 -> CS0 : on-board flash
38 * CS1 : SRAM, registers, LAN, PCMCIA
39 * 38400 bps for SCIF1
40 *
41 * Address
42 * 0x00000000 - 0x04000000 (CS0) Nor Flash
43 * 0x04000000 - 0x04200000 (CS1) SRAM
44 * 0x05000000 - 0x05800000 (CS1) on board register
45 * 0x05800000 - 0x06000000 (CS1) LAN91C111
46 * 0x06000000 - 0x06400000 (CS1) PCMCIA
47 * 0x08000000 - 0x10000000 (CS2-CS3) DDR3
48 * 0x10000000 - 0x14000000 (CS4) PCIe
49 * 0x14000000 - 0x14800000 (CS5) Core0 LRAM/URAM
50 * 0x14800000 - 0x15000000 (CS5) Core1 LRAM/URAM
51 * 0x18000000 - 0x1C000000 (CS6) ATA/NAND-Flash
52 * 0x1C000000 - (CS7) SH7786 Control register
53 */
54
55 /* HeartBeat */
56 static struct resource heartbeat_resource = {
57 .start = BOARDREG(SLEDR),
58 .end = BOARDREG(SLEDR),
59 .flags = IORESOURCE_MEM | IORESOURCE_MEM_16BIT,
60 };
61
62 static struct platform_device heartbeat_device = {
63 .name = "heartbeat",
64 .id = -1,
65 .num_resources = 1,
66 .resource = &heartbeat_resource,
67 };
68
69 /* LAN91C111 */
70 static struct smc91x_platdata smc91x_info = {
71 .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
72 };
73
74 static struct resource smc91x_eth_resources[] = {
75 [0] = {
76 .name = "SMC91C111" ,
77 .start = 0x05800300,
78 .end = 0x0580030f,
79 .flags = IORESOURCE_MEM,
80 },
81 [1] = {
82 .start = evt2irq(0x360),
83 .flags = IORESOURCE_IRQ,
84 },
85 };
86
87 static struct platform_device smc91x_eth_device = {
88 .name = "smc91x",
89 .num_resources = ARRAY_SIZE(smc91x_eth_resources),
90 .resource = smc91x_eth_resources,
91 .dev = {
92 .platform_data = &smc91x_info,
93 },
94 };
95
96 /* Nor Flash */
97 static struct mtd_partition nor_flash_partitions[] = {
98 {
99 .name = "loader",
100 .offset = 0x00000000,
101 .size = SZ_512K,
102 .mask_flags = MTD_WRITEABLE, /* Read-only */
103 },
104 {
105 .name = "bootenv",
106 .offset = MTDPART_OFS_APPEND,
107 .size = SZ_512K,
108 .mask_flags = MTD_WRITEABLE, /* Read-only */
109 },
110 {
111 .name = "kernel",
112 .offset = MTDPART_OFS_APPEND,
113 .size = SZ_4M,
114 },
115 {
116 .name = "data",
117 .offset = MTDPART_OFS_APPEND,
118 .size = MTDPART_SIZ_FULL,
119 },
120 };
121
122 static struct physmap_flash_data nor_flash_data = {
123 .width = 2,
124 .parts = nor_flash_partitions,
125 .nr_parts = ARRAY_SIZE(nor_flash_partitions),
126 };
127
128 static struct resource nor_flash_resources[] = {
129 [0] = {
130 .start = NOR_FLASH_ADDR,
131 .end = NOR_FLASH_ADDR + NOR_FLASH_SIZE - 1,
132 .flags = IORESOURCE_MEM,
133 }
134 };
135
136 static struct platform_device nor_flash_device = {
137 .name = "physmap-flash",
138 .dev = {
139 .platform_data = &nor_flash_data,
140 },
141 .num_resources = ARRAY_SIZE(nor_flash_resources),
142 .resource = nor_flash_resources,
143 };
144
145 static struct platform_device *urquell_devices[] __initdata = {
146 &heartbeat_device,
147 &smc91x_eth_device,
148 &nor_flash_device,
149 };
150
urquell_devices_setup(void)151 static int __init urquell_devices_setup(void)
152 {
153 /* USB */
154 gpio_request(GPIO_FN_USB_OVC0, NULL);
155 gpio_request(GPIO_FN_USB_PENC0, NULL);
156
157 /* enable LAN */
158 __raw_writew(__raw_readw(UBOARDREG(IRL2MSKR)) & ~0x00000001,
159 UBOARDREG(IRL2MSKR));
160
161 return platform_add_devices(urquell_devices,
162 ARRAY_SIZE(urquell_devices));
163 }
164 device_initcall(urquell_devices_setup);
165
urquell_power_off(void)166 static void urquell_power_off(void)
167 {
168 __raw_writew(0xa5a5, UBOARDREG(SRSTR));
169 }
170
urquell_init_irq(void)171 static void __init urquell_init_irq(void)
172 {
173 plat_irq_setup_pins(IRQ_MODE_IRL3210_MASK);
174 }
175
urquell_mode_pins(void)176 static int urquell_mode_pins(void)
177 {
178 return __raw_readw(UBOARDREG(MDSWMR));
179 }
180
urquell_clk_init(void)181 static int urquell_clk_init(void)
182 {
183 struct clk *clk;
184 int ret;
185
186 /*
187 * Only handle the EXTAL case, anyone interfacing a crystal
188 * resonator will need to provide their own input clock.
189 */
190 if (test_mode_pin(MODE_PIN9))
191 return -EINVAL;
192
193 clk = clk_get(NULL, "extal");
194 if (IS_ERR(clk))
195 return PTR_ERR(clk);
196 ret = clk_set_rate(clk, 33333333);
197 clk_put(clk);
198
199 return ret;
200 }
201
202 /* Initialize the board */
urquell_setup(char ** cmdline_p)203 static void __init urquell_setup(char **cmdline_p)
204 {
205 printk(KERN_INFO "Renesas Technology Corp. Urquell support.\n");
206
207 pm_power_off = urquell_power_off;
208
209 register_smp_ops(&shx3_smp_ops);
210 }
211
212 /*
213 * The Machine Vector
214 */
215 static struct sh_machine_vector mv_urquell __initmv = {
216 .mv_name = "Urquell",
217 .mv_setup = urquell_setup,
218 .mv_init_irq = urquell_init_irq,
219 .mv_mode_pins = urquell_mode_pins,
220 .mv_clk_init = urquell_clk_init,
221 };
222