1 /* 2 * Intel Atom SOC Power Management Controller Header File 3 * Copyright (c) 2014, Intel Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms and conditions of the GNU General Public License, 7 * version 2, as published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 */ 15 16 #ifndef PMC_ATOM_H 17 #define PMC_ATOM_H 18 19 /* ValleyView Power Control Unit PCI Device ID */ 20 #define PCI_DEVICE_ID_VLV_PMC 0x0F1C 21 22 /* PMC Memory mapped IO registers */ 23 #define PMC_BASE_ADDR_OFFSET 0x44 24 #define PMC_BASE_ADDR_MASK 0xFFFFFE00 25 #define PMC_MMIO_REG_LEN 0x100 26 #define PMC_REG_BIT_WIDTH 32 27 28 /* BIOS uses FUNC_DIS to disable specific function */ 29 #define PMC_FUNC_DIS 0x34 30 #define PMC_FUNC_DIS_2 0x38 31 32 /* S0ix wake event control */ 33 #define PMC_S0IX_WAKE_EN 0x3C 34 35 #define BIT_LPC_CLOCK_RUN BIT(4) 36 #define BIT_SHARED_IRQ_GPSC BIT(5) 37 #define BIT_ORED_DEDICATED_IRQ_GPSS BIT(18) 38 #define BIT_ORED_DEDICATED_IRQ_GPSC BIT(19) 39 #define BIT_SHARED_IRQ_GPSS BIT(20) 40 41 #define PMC_WAKE_EN_SETTING ~(BIT_LPC_CLOCK_RUN | \ 42 BIT_SHARED_IRQ_GPSC | \ 43 BIT_ORED_DEDICATED_IRQ_GPSS | \ 44 BIT_ORED_DEDICATED_IRQ_GPSC | \ 45 BIT_SHARED_IRQ_GPSS) 46 47 /* The timers acumulate time spent in sleep state */ 48 #define PMC_S0IR_TMR 0x80 49 #define PMC_S0I1_TMR 0x84 50 #define PMC_S0I2_TMR 0x88 51 #define PMC_S0I3_TMR 0x8C 52 #define PMC_S0_TMR 0x90 53 /* Sleep state counter is in units of of 32us */ 54 #define PMC_TMR_SHIFT 5 55 56 /* These registers reflect D3 status of functions */ 57 #define PMC_D3_STS_0 0xA0 58 59 #define BIT_LPSS1_F0_DMA BIT(0) 60 #define BIT_LPSS1_F1_PWM1 BIT(1) 61 #define BIT_LPSS1_F2_PWM2 BIT(2) 62 #define BIT_LPSS1_F3_HSUART1 BIT(3) 63 #define BIT_LPSS1_F4_HSUART2 BIT(4) 64 #define BIT_LPSS1_F5_SPI BIT(5) 65 #define BIT_LPSS1_F6_XXX BIT(6) 66 #define BIT_LPSS1_F7_XXX BIT(7) 67 #define BIT_SCC_EMMC BIT(8) 68 #define BIT_SCC_SDIO BIT(9) 69 #define BIT_SCC_SDCARD BIT(10) 70 #define BIT_SCC_MIPI BIT(11) 71 #define BIT_HDA BIT(12) 72 #define BIT_LPE BIT(13) 73 #define BIT_OTG BIT(14) 74 #define BIT_USH BIT(15) 75 #define BIT_GBE BIT(16) 76 #define BIT_SATA BIT(17) 77 #define BIT_USB_EHCI BIT(18) 78 #define BIT_SEC BIT(19) 79 #define BIT_PCIE_PORT0 BIT(20) 80 #define BIT_PCIE_PORT1 BIT(21) 81 #define BIT_PCIE_PORT2 BIT(22) 82 #define BIT_PCIE_PORT3 BIT(23) 83 #define BIT_LPSS2_F0_DMA BIT(24) 84 #define BIT_LPSS2_F1_I2C1 BIT(25) 85 #define BIT_LPSS2_F2_I2C2 BIT(26) 86 #define BIT_LPSS2_F3_I2C3 BIT(27) 87 #define BIT_LPSS2_F4_I2C4 BIT(28) 88 #define BIT_LPSS2_F5_I2C5 BIT(29) 89 #define BIT_LPSS2_F6_I2C6 BIT(30) 90 #define BIT_LPSS2_F7_I2C7 BIT(31) 91 92 #define PMC_D3_STS_1 0xA4 93 #define BIT_SMB BIT(0) 94 #define BIT_OTG_SS_PHY BIT(1) 95 #define BIT_USH_SS_PHY BIT(2) 96 #define BIT_DFX BIT(3) 97 98 /* PMC I/O Registers */ 99 #define ACPI_BASE_ADDR_OFFSET 0x40 100 #define ACPI_BASE_ADDR_MASK 0xFFFFFE00 101 #define ACPI_MMIO_REG_LEN 0x100 102 103 #define PM1_CNT 0x4 104 #define SLEEP_TYPE_MASK 0xFFFFECFF 105 #define SLEEP_TYPE_S5 0x1C00 106 #define SLEEP_ENABLE 0x2000 107 #endif /* PMC_ATOM_H */ 108