1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * SGI UV APIC functions (note: not an Intel compatible APIC)
7 *
8 * Copyright (C) 2007-2014 Silicon Graphics, Inc. All rights reserved.
9 */
10 #include <linux/cpumask.h>
11 #include <linux/hardirq.h>
12 #include <linux/proc_fs.h>
13 #include <linux/threads.h>
14 #include <linux/kernel.h>
15 #include <linux/module.h>
16 #include <linux/string.h>
17 #include <linux/ctype.h>
18 #include <linux/sched.h>
19 #include <linux/timer.h>
20 #include <linux/slab.h>
21 #include <linux/cpu.h>
22 #include <linux/init.h>
23 #include <linux/io.h>
24 #include <linux/pci.h>
25 #include <linux/kdebug.h>
26 #include <linux/delay.h>
27 #include <linux/crash_dump.h>
28 #include <linux/reboot.h>
29
30 #include <asm/uv/uv_mmrs.h>
31 #include <asm/uv/uv_hub.h>
32 #include <asm/current.h>
33 #include <asm/pgtable.h>
34 #include <asm/uv/bios.h>
35 #include <asm/uv/uv.h>
36 #include <asm/apic.h>
37 #include <asm/ipi.h>
38 #include <asm/smp.h>
39 #include <asm/x86_init.h>
40 #include <asm/nmi.h>
41
42 DEFINE_PER_CPU(int, x2apic_extra_bits);
43
44 #define PR_DEVEL(fmt, args...) pr_devel("%s: " fmt, __func__, args)
45
46 static enum uv_system_type uv_system_type;
47 static u64 gru_start_paddr, gru_end_paddr;
48 static u64 gru_dist_base, gru_first_node_paddr = -1LL, gru_last_node_paddr;
49 static u64 gru_dist_lmask, gru_dist_umask;
50 static union uvh_apicid uvh_apicid;
51 int uv_min_hub_revision_id;
52 EXPORT_SYMBOL_GPL(uv_min_hub_revision_id);
53 unsigned int uv_apicid_hibits;
54 EXPORT_SYMBOL_GPL(uv_apicid_hibits);
55
56 static struct apic apic_x2apic_uv_x;
57
uv_early_read_mmr(unsigned long addr)58 static unsigned long __init uv_early_read_mmr(unsigned long addr)
59 {
60 unsigned long val, *mmr;
61
62 mmr = early_ioremap(UV_LOCAL_MMR_BASE | addr, sizeof(*mmr));
63 val = *mmr;
64 early_iounmap(mmr, sizeof(*mmr));
65 return val;
66 }
67
is_GRU_range(u64 start,u64 end)68 static inline bool is_GRU_range(u64 start, u64 end)
69 {
70 if (gru_dist_base) {
71 u64 su = start & gru_dist_umask; /* upper (incl pnode) bits */
72 u64 sl = start & gru_dist_lmask; /* base offset bits */
73 u64 eu = end & gru_dist_umask;
74 u64 el = end & gru_dist_lmask;
75
76 /* Must reside completely within a single GRU range */
77 return (sl == gru_dist_base && el == gru_dist_base &&
78 su >= gru_first_node_paddr &&
79 su <= gru_last_node_paddr &&
80 eu == su);
81 } else {
82 return start >= gru_start_paddr && end <= gru_end_paddr;
83 }
84 }
85
uv_is_untracked_pat_range(u64 start,u64 end)86 static bool uv_is_untracked_pat_range(u64 start, u64 end)
87 {
88 return is_ISA_range(start, end) || is_GRU_range(start, end);
89 }
90
early_get_pnodeid(void)91 static int __init early_get_pnodeid(void)
92 {
93 union uvh_node_id_u node_id;
94 union uvh_rh_gam_config_mmr_u m_n_config;
95 int pnode;
96
97 /* Currently, all blades have same revision number */
98 node_id.v = uv_early_read_mmr(UVH_NODE_ID);
99 m_n_config.v = uv_early_read_mmr(UVH_RH_GAM_CONFIG_MMR);
100 uv_min_hub_revision_id = node_id.s.revision;
101
102 switch (node_id.s.part_number) {
103 case UV2_HUB_PART_NUMBER:
104 case UV2_HUB_PART_NUMBER_X:
105 uv_min_hub_revision_id += UV2_HUB_REVISION_BASE - 1;
106 break;
107 case UV3_HUB_PART_NUMBER:
108 case UV3_HUB_PART_NUMBER_X:
109 uv_min_hub_revision_id += UV3_HUB_REVISION_BASE;
110 break;
111 }
112
113 uv_hub_info->hub_revision = uv_min_hub_revision_id;
114 pnode = (node_id.s.node_id >> 1) & ((1 << m_n_config.s.n_skt) - 1);
115 return pnode;
116 }
117
early_get_apic_pnode_shift(void)118 static void __init early_get_apic_pnode_shift(void)
119 {
120 uvh_apicid.v = uv_early_read_mmr(UVH_APICID);
121 if (!uvh_apicid.v)
122 /*
123 * Old bios, use default value
124 */
125 uvh_apicid.s.pnode_shift = UV_APIC_PNODE_SHIFT;
126 }
127
128 /*
129 * Add an extra bit as dictated by bios to the destination apicid of
130 * interrupts potentially passing through the UV HUB. This prevents
131 * a deadlock between interrupts and IO port operations.
132 */
uv_set_apicid_hibit(void)133 static void __init uv_set_apicid_hibit(void)
134 {
135 union uv1h_lb_target_physical_apic_id_mask_u apicid_mask;
136
137 if (is_uv1_hub()) {
138 apicid_mask.v =
139 uv_early_read_mmr(UV1H_LB_TARGET_PHYSICAL_APIC_ID_MASK);
140 uv_apicid_hibits =
141 apicid_mask.s1.bit_enables & UV_APICID_HIBIT_MASK;
142 }
143 }
144
uv_acpi_madt_oem_check(char * oem_id,char * oem_table_id)145 static int __init uv_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
146 {
147 int pnodeid, is_uv1, is_uv2, is_uv3;
148
149 is_uv1 = !strcmp(oem_id, "SGI");
150 is_uv2 = !strcmp(oem_id, "SGI2");
151 is_uv3 = !strncmp(oem_id, "SGI3", 4); /* there are varieties of UV3 */
152 if (is_uv1 || is_uv2 || is_uv3) {
153 uv_hub_info->hub_revision =
154 (is_uv1 ? UV1_HUB_REVISION_BASE :
155 (is_uv2 ? UV2_HUB_REVISION_BASE :
156 UV3_HUB_REVISION_BASE));
157 pnodeid = early_get_pnodeid();
158 early_get_apic_pnode_shift();
159 x86_platform.is_untracked_pat_range = uv_is_untracked_pat_range;
160 x86_platform.nmi_init = uv_nmi_init;
161 if (!strcmp(oem_table_id, "UVL"))
162 uv_system_type = UV_LEGACY_APIC;
163 else if (!strcmp(oem_table_id, "UVX"))
164 uv_system_type = UV_X2APIC;
165 else if (!strcmp(oem_table_id, "UVH")) {
166 __this_cpu_write(x2apic_extra_bits,
167 pnodeid << uvh_apicid.s.pnode_shift);
168 uv_system_type = UV_NON_UNIQUE_APIC;
169 uv_set_apicid_hibit();
170 return 1;
171 }
172 }
173 return 0;
174 }
175
get_uv_system_type(void)176 enum uv_system_type get_uv_system_type(void)
177 {
178 return uv_system_type;
179 }
180
is_uv_system(void)181 int is_uv_system(void)
182 {
183 return uv_system_type != UV_NONE;
184 }
185 EXPORT_SYMBOL_GPL(is_uv_system);
186
187 DEFINE_PER_CPU(struct uv_hub_info_s, __uv_hub_info);
188 EXPORT_PER_CPU_SYMBOL_GPL(__uv_hub_info);
189
190 struct uv_blade_info *uv_blade_info;
191 EXPORT_SYMBOL_GPL(uv_blade_info);
192
193 short *uv_node_to_blade;
194 EXPORT_SYMBOL_GPL(uv_node_to_blade);
195
196 short *uv_cpu_to_blade;
197 EXPORT_SYMBOL_GPL(uv_cpu_to_blade);
198
199 short uv_possible_blades;
200 EXPORT_SYMBOL_GPL(uv_possible_blades);
201
202 unsigned long sn_rtc_cycles_per_second;
203 EXPORT_SYMBOL(sn_rtc_cycles_per_second);
204
uv_wakeup_secondary(int phys_apicid,unsigned long start_rip)205 static int uv_wakeup_secondary(int phys_apicid, unsigned long start_rip)
206 {
207 unsigned long val;
208 int pnode;
209
210 pnode = uv_apicid_to_pnode(phys_apicid);
211 phys_apicid |= uv_apicid_hibits;
212 val = (1UL << UVH_IPI_INT_SEND_SHFT) |
213 (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
214 ((start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
215 APIC_DM_INIT;
216 uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
217
218 val = (1UL << UVH_IPI_INT_SEND_SHFT) |
219 (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
220 ((start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
221 APIC_DM_STARTUP;
222 uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
223
224 atomic_set(&init_deasserted, 1);
225 return 0;
226 }
227
uv_send_IPI_one(int cpu,int vector)228 static void uv_send_IPI_one(int cpu, int vector)
229 {
230 unsigned long apicid;
231 int pnode;
232
233 apicid = per_cpu(x86_cpu_to_apicid, cpu);
234 pnode = uv_apicid_to_pnode(apicid);
235 uv_hub_send_ipi(pnode, apicid, vector);
236 }
237
uv_send_IPI_mask(const struct cpumask * mask,int vector)238 static void uv_send_IPI_mask(const struct cpumask *mask, int vector)
239 {
240 unsigned int cpu;
241
242 for_each_cpu(cpu, mask)
243 uv_send_IPI_one(cpu, vector);
244 }
245
uv_send_IPI_mask_allbutself(const struct cpumask * mask,int vector)246 static void uv_send_IPI_mask_allbutself(const struct cpumask *mask, int vector)
247 {
248 unsigned int this_cpu = smp_processor_id();
249 unsigned int cpu;
250
251 for_each_cpu(cpu, mask) {
252 if (cpu != this_cpu)
253 uv_send_IPI_one(cpu, vector);
254 }
255 }
256
uv_send_IPI_allbutself(int vector)257 static void uv_send_IPI_allbutself(int vector)
258 {
259 unsigned int this_cpu = smp_processor_id();
260 unsigned int cpu;
261
262 for_each_online_cpu(cpu) {
263 if (cpu != this_cpu)
264 uv_send_IPI_one(cpu, vector);
265 }
266 }
267
uv_send_IPI_all(int vector)268 static void uv_send_IPI_all(int vector)
269 {
270 uv_send_IPI_mask(cpu_online_mask, vector);
271 }
272
uv_apic_id_valid(int apicid)273 static int uv_apic_id_valid(int apicid)
274 {
275 return 1;
276 }
277
uv_apic_id_registered(void)278 static int uv_apic_id_registered(void)
279 {
280 return 1;
281 }
282
uv_init_apic_ldr(void)283 static void uv_init_apic_ldr(void)
284 {
285 }
286
287 static int
uv_cpu_mask_to_apicid_and(const struct cpumask * cpumask,const struct cpumask * andmask,unsigned int * apicid)288 uv_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
289 const struct cpumask *andmask,
290 unsigned int *apicid)
291 {
292 int unsigned cpu;
293
294 /*
295 * We're using fixed IRQ delivery, can only return one phys APIC ID.
296 * May as well be the first.
297 */
298 for_each_cpu_and(cpu, cpumask, andmask) {
299 if (cpumask_test_cpu(cpu, cpu_online_mask))
300 break;
301 }
302
303 if (likely(cpu < nr_cpu_ids)) {
304 *apicid = per_cpu(x86_cpu_to_apicid, cpu) | uv_apicid_hibits;
305 return 0;
306 }
307
308 return -EINVAL;
309 }
310
x2apic_get_apic_id(unsigned long x)311 static unsigned int x2apic_get_apic_id(unsigned long x)
312 {
313 unsigned int id;
314
315 WARN_ON(preemptible() && num_online_cpus() > 1);
316 id = x | __this_cpu_read(x2apic_extra_bits);
317
318 return id;
319 }
320
set_apic_id(unsigned int id)321 static unsigned long set_apic_id(unsigned int id)
322 {
323 unsigned long x;
324
325 /* maskout x2apic_extra_bits ? */
326 x = id;
327 return x;
328 }
329
uv_read_apic_id(void)330 static unsigned int uv_read_apic_id(void)
331 {
332
333 return x2apic_get_apic_id(apic_read(APIC_ID));
334 }
335
uv_phys_pkg_id(int initial_apicid,int index_msb)336 static int uv_phys_pkg_id(int initial_apicid, int index_msb)
337 {
338 return uv_read_apic_id() >> index_msb;
339 }
340
uv_send_IPI_self(int vector)341 static void uv_send_IPI_self(int vector)
342 {
343 apic_write(APIC_SELF_IPI, vector);
344 }
345
uv_probe(void)346 static int uv_probe(void)
347 {
348 return apic == &apic_x2apic_uv_x;
349 }
350
351 static struct apic __refdata apic_x2apic_uv_x = {
352
353 .name = "UV large system",
354 .probe = uv_probe,
355 .acpi_madt_oem_check = uv_acpi_madt_oem_check,
356 .apic_id_valid = uv_apic_id_valid,
357 .apic_id_registered = uv_apic_id_registered,
358
359 .irq_delivery_mode = dest_Fixed,
360 .irq_dest_mode = 0, /* physical */
361
362 .target_cpus = online_target_cpus,
363 .disable_esr = 0,
364 .dest_logical = APIC_DEST_LOGICAL,
365 .check_apicid_used = NULL,
366
367 .vector_allocation_domain = default_vector_allocation_domain,
368 .init_apic_ldr = uv_init_apic_ldr,
369
370 .ioapic_phys_id_map = NULL,
371 .setup_apic_routing = NULL,
372 .cpu_present_to_apicid = default_cpu_present_to_apicid,
373 .apicid_to_cpu_present = NULL,
374 .check_phys_apicid_present = default_check_phys_apicid_present,
375 .phys_pkg_id = uv_phys_pkg_id,
376
377 .get_apic_id = x2apic_get_apic_id,
378 .set_apic_id = set_apic_id,
379 .apic_id_mask = 0xFFFFFFFFu,
380
381 .cpu_mask_to_apicid_and = uv_cpu_mask_to_apicid_and,
382
383 .send_IPI_mask = uv_send_IPI_mask,
384 .send_IPI_mask_allbutself = uv_send_IPI_mask_allbutself,
385 .send_IPI_allbutself = uv_send_IPI_allbutself,
386 .send_IPI_all = uv_send_IPI_all,
387 .send_IPI_self = uv_send_IPI_self,
388
389 .wakeup_secondary_cpu = uv_wakeup_secondary,
390 .wait_for_init_deassert = false,
391 .inquire_remote_apic = NULL,
392
393 .read = native_apic_msr_read,
394 .write = native_apic_msr_write,
395 .eoi_write = native_apic_msr_eoi_write,
396 .icr_read = native_x2apic_icr_read,
397 .icr_write = native_x2apic_icr_write,
398 .wait_icr_idle = native_x2apic_wait_icr_idle,
399 .safe_wait_icr_idle = native_safe_x2apic_wait_icr_idle,
400 };
401
set_x2apic_extra_bits(int pnode)402 static void set_x2apic_extra_bits(int pnode)
403 {
404 __this_cpu_write(x2apic_extra_bits, pnode << uvh_apicid.s.pnode_shift);
405 }
406
407 /*
408 * Called on boot cpu.
409 */
boot_pnode_to_blade(int pnode)410 static __init int boot_pnode_to_blade(int pnode)
411 {
412 int blade;
413
414 for (blade = 0; blade < uv_num_possible_blades(); blade++)
415 if (pnode == uv_blade_info[blade].pnode)
416 return blade;
417 BUG();
418 }
419
420 struct redir_addr {
421 unsigned long redirect;
422 unsigned long alias;
423 };
424
425 #define DEST_SHIFT UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT
426
427 static __initdata struct redir_addr redir_addrs[] = {
428 {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR, UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR},
429 {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR, UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR},
430 {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR, UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR},
431 };
432
get_n_lshift(int m_val)433 static unsigned char get_n_lshift(int m_val)
434 {
435 union uv3h_gr0_gam_gr_config_u m_gr_config;
436
437 if (is_uv1_hub())
438 return m_val;
439
440 if (is_uv2_hub())
441 return m_val == 40 ? 40 : 39;
442
443 m_gr_config.v = uv_read_local_mmr(UV3H_GR0_GAM_GR_CONFIG);
444 return m_gr_config.s3.m_skt;
445 }
446
get_lowmem_redirect(unsigned long * base,unsigned long * size)447 static __init void get_lowmem_redirect(unsigned long *base, unsigned long *size)
448 {
449 union uvh_rh_gam_alias210_overlay_config_2_mmr_u alias;
450 union uvh_rh_gam_alias210_redirect_config_2_mmr_u redirect;
451 int i;
452
453 for (i = 0; i < ARRAY_SIZE(redir_addrs); i++) {
454 alias.v = uv_read_local_mmr(redir_addrs[i].alias);
455 if (alias.s.enable && alias.s.base == 0) {
456 *size = (1UL << alias.s.m_alias);
457 redirect.v = uv_read_local_mmr(redir_addrs[i].redirect);
458 *base = (unsigned long)redirect.s.dest_base << DEST_SHIFT;
459 return;
460 }
461 }
462 *base = *size = 0;
463 }
464
465 enum map_type {map_wb, map_uc};
466
map_high(char * id,unsigned long base,int pshift,int bshift,int max_pnode,enum map_type map_type)467 static __init void map_high(char *id, unsigned long base, int pshift,
468 int bshift, int max_pnode, enum map_type map_type)
469 {
470 unsigned long bytes, paddr;
471
472 paddr = base << pshift;
473 bytes = (1UL << bshift) * (max_pnode + 1);
474 if (!paddr) {
475 pr_info("UV: Map %s_HI base address NULL\n", id);
476 return;
477 }
478 pr_debug("UV: Map %s_HI 0x%lx - 0x%lx\n", id, paddr, paddr + bytes);
479 if (map_type == map_uc)
480 init_extra_mapping_uc(paddr, bytes);
481 else
482 init_extra_mapping_wb(paddr, bytes);
483 }
484
map_gru_distributed(unsigned long c)485 static __init void map_gru_distributed(unsigned long c)
486 {
487 union uvh_rh_gam_gru_overlay_config_mmr_u gru;
488 u64 paddr;
489 unsigned long bytes;
490 int nid;
491
492 gru.v = c;
493 /* only base bits 42:28 relevant in dist mode */
494 gru_dist_base = gru.v & 0x000007fff0000000UL;
495 if (!gru_dist_base) {
496 pr_info("UV: Map GRU_DIST base address NULL\n");
497 return;
498 }
499 bytes = 1UL << UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT;
500 gru_dist_lmask = ((1UL << uv_hub_info->m_val) - 1) & ~(bytes - 1);
501 gru_dist_umask = ~((1UL << uv_hub_info->m_val) - 1);
502 gru_dist_base &= gru_dist_lmask; /* Clear bits above M */
503 for_each_online_node(nid) {
504 paddr = ((u64)uv_node_to_pnode(nid) << uv_hub_info->m_val) |
505 gru_dist_base;
506 init_extra_mapping_wb(paddr, bytes);
507 gru_first_node_paddr = min(paddr, gru_first_node_paddr);
508 gru_last_node_paddr = max(paddr, gru_last_node_paddr);
509 }
510 /* Save upper (63:M) bits of address only for is_GRU_range */
511 gru_first_node_paddr &= gru_dist_umask;
512 gru_last_node_paddr &= gru_dist_umask;
513 pr_debug("UV: Map GRU_DIST base 0x%016llx 0x%016llx - 0x%016llx\n",
514 gru_dist_base, gru_first_node_paddr, gru_last_node_paddr);
515 }
516
map_gru_high(int max_pnode)517 static __init void map_gru_high(int max_pnode)
518 {
519 union uvh_rh_gam_gru_overlay_config_mmr_u gru;
520 int shift = UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT;
521
522 gru.v = uv_read_local_mmr(UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR);
523 if (!gru.s.enable) {
524 pr_info("UV: GRU disabled\n");
525 return;
526 }
527
528 if (is_uv3_hub() && gru.s3.mode) {
529 map_gru_distributed(gru.v);
530 return;
531 }
532 map_high("GRU", gru.s.base, shift, shift, max_pnode, map_wb);
533 gru_start_paddr = ((u64)gru.s.base << shift);
534 gru_end_paddr = gru_start_paddr + (1UL << shift) * (max_pnode + 1);
535 }
536
map_mmr_high(int max_pnode)537 static __init void map_mmr_high(int max_pnode)
538 {
539 union uvh_rh_gam_mmr_overlay_config_mmr_u mmr;
540 int shift = UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT;
541
542 mmr.v = uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR);
543 if (mmr.s.enable)
544 map_high("MMR", mmr.s.base, shift, shift, max_pnode, map_uc);
545 else
546 pr_info("UV: MMR disabled\n");
547 }
548
549 /*
550 * This commonality works because both 0 & 1 versions of the MMIOH OVERLAY
551 * and REDIRECT MMR regs are exactly the same on UV3.
552 */
553 struct mmioh_config {
554 unsigned long overlay;
555 unsigned long redirect;
556 char *id;
557 };
558
559 static __initdata struct mmioh_config mmiohs[] = {
560 {
561 UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR,
562 UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR,
563 "MMIOH0"
564 },
565 {
566 UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR,
567 UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR,
568 "MMIOH1"
569 },
570 };
571
map_mmioh_high_uv3(int index,int min_pnode,int max_pnode)572 static __init void map_mmioh_high_uv3(int index, int min_pnode, int max_pnode)
573 {
574 union uv3h_rh_gam_mmioh_overlay_config0_mmr_u overlay;
575 unsigned long mmr;
576 unsigned long base;
577 int i, n, shift, m_io, max_io;
578 int nasid, lnasid, fi, li;
579 char *id;
580
581 id = mmiohs[index].id;
582 overlay.v = uv_read_local_mmr(mmiohs[index].overlay);
583 pr_info("UV: %s overlay 0x%lx base:0x%x m_io:%d\n",
584 id, overlay.v, overlay.s3.base, overlay.s3.m_io);
585 if (!overlay.s3.enable) {
586 pr_info("UV: %s disabled\n", id);
587 return;
588 }
589
590 shift = UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_BASE_SHFT;
591 base = (unsigned long)overlay.s3.base;
592 m_io = overlay.s3.m_io;
593 mmr = mmiohs[index].redirect;
594 n = UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_DEPTH;
595 min_pnode *= 2; /* convert to NASID */
596 max_pnode *= 2;
597 max_io = lnasid = fi = li = -1;
598
599 for (i = 0; i < n; i++) {
600 union uv3h_rh_gam_mmioh_redirect_config0_mmr_u redirect;
601
602 redirect.v = uv_read_local_mmr(mmr + i * 8);
603 nasid = redirect.s3.nasid;
604 if (nasid < min_pnode || max_pnode < nasid)
605 nasid = -1; /* invalid NASID */
606
607 if (nasid == lnasid) {
608 li = i;
609 if (i != n-1) /* last entry check */
610 continue;
611 }
612
613 /* check if we have a cached (or last) redirect to print */
614 if (lnasid != -1 || (i == n-1 && nasid != -1)) {
615 unsigned long addr1, addr2;
616 int f, l;
617
618 if (lnasid == -1) {
619 f = l = i;
620 lnasid = nasid;
621 } else {
622 f = fi;
623 l = li;
624 }
625 addr1 = (base << shift) +
626 f * (unsigned long)(1 << m_io);
627 addr2 = (base << shift) +
628 (l + 1) * (unsigned long)(1 << m_io);
629 pr_info("UV: %s[%03d..%03d] NASID 0x%04x ADDR 0x%016lx - 0x%016lx\n",
630 id, fi, li, lnasid, addr1, addr2);
631 if (max_io < l)
632 max_io = l;
633 }
634 fi = li = i;
635 lnasid = nasid;
636 }
637
638 pr_info("UV: %s base:0x%lx shift:%d M_IO:%d MAX_IO:%d\n",
639 id, base, shift, m_io, max_io);
640
641 if (max_io >= 0)
642 map_high(id, base, shift, m_io, max_io, map_uc);
643 }
644
map_mmioh_high(int min_pnode,int max_pnode)645 static __init void map_mmioh_high(int min_pnode, int max_pnode)
646 {
647 union uvh_rh_gam_mmioh_overlay_config_mmr_u mmioh;
648 unsigned long mmr, base;
649 int shift, enable, m_io, n_io;
650
651 if (is_uv3_hub()) {
652 /* Map both MMIOH Regions */
653 map_mmioh_high_uv3(0, min_pnode, max_pnode);
654 map_mmioh_high_uv3(1, min_pnode, max_pnode);
655 return;
656 }
657
658 if (is_uv1_hub()) {
659 mmr = UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR;
660 shift = UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT;
661 mmioh.v = uv_read_local_mmr(mmr);
662 enable = !!mmioh.s1.enable;
663 base = mmioh.s1.base;
664 m_io = mmioh.s1.m_io;
665 n_io = mmioh.s1.n_io;
666 } else if (is_uv2_hub()) {
667 mmr = UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR;
668 shift = UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT;
669 mmioh.v = uv_read_local_mmr(mmr);
670 enable = !!mmioh.s2.enable;
671 base = mmioh.s2.base;
672 m_io = mmioh.s2.m_io;
673 n_io = mmioh.s2.n_io;
674 } else
675 return;
676
677 if (enable) {
678 max_pnode &= (1 << n_io) - 1;
679 pr_info(
680 "UV: base:0x%lx shift:%d N_IO:%d M_IO:%d max_pnode:0x%x\n",
681 base, shift, m_io, n_io, max_pnode);
682 map_high("MMIOH", base, shift, m_io, max_pnode, map_uc);
683 } else {
684 pr_info("UV: MMIOH disabled\n");
685 }
686 }
687
map_low_mmrs(void)688 static __init void map_low_mmrs(void)
689 {
690 init_extra_mapping_uc(UV_GLOBAL_MMR32_BASE, UV_GLOBAL_MMR32_SIZE);
691 init_extra_mapping_uc(UV_LOCAL_MMR_BASE, UV_LOCAL_MMR_SIZE);
692 }
693
uv_rtc_init(void)694 static __init void uv_rtc_init(void)
695 {
696 long status;
697 u64 ticks_per_sec;
698
699 status = uv_bios_freq_base(BIOS_FREQ_BASE_REALTIME_CLOCK,
700 &ticks_per_sec);
701 if (status != BIOS_STATUS_SUCCESS || ticks_per_sec < 100000) {
702 printk(KERN_WARNING
703 "unable to determine platform RTC clock frequency, "
704 "guessing.\n");
705 /* BIOS gives wrong value for clock freq. so guess */
706 sn_rtc_cycles_per_second = 1000000000000UL / 30000UL;
707 } else
708 sn_rtc_cycles_per_second = ticks_per_sec;
709 }
710
711 /*
712 * percpu heartbeat timer
713 */
uv_heartbeat(unsigned long ignored)714 static void uv_heartbeat(unsigned long ignored)
715 {
716 struct timer_list *timer = &uv_hub_info->scir.timer;
717 unsigned char bits = uv_hub_info->scir.state;
718
719 /* flip heartbeat bit */
720 bits ^= SCIR_CPU_HEARTBEAT;
721
722 /* is this cpu idle? */
723 if (idle_cpu(raw_smp_processor_id()))
724 bits &= ~SCIR_CPU_ACTIVITY;
725 else
726 bits |= SCIR_CPU_ACTIVITY;
727
728 /* update system controller interface reg */
729 uv_set_scir_bits(bits);
730
731 /* enable next timer period */
732 mod_timer_pinned(timer, jiffies + SCIR_CPU_HB_INTERVAL);
733 }
734
uv_heartbeat_enable(int cpu)735 static void uv_heartbeat_enable(int cpu)
736 {
737 while (!uv_cpu_hub_info(cpu)->scir.enabled) {
738 struct timer_list *timer = &uv_cpu_hub_info(cpu)->scir.timer;
739
740 uv_set_cpu_scir_bits(cpu, SCIR_CPU_HEARTBEAT|SCIR_CPU_ACTIVITY);
741 setup_timer(timer, uv_heartbeat, cpu);
742 timer->expires = jiffies + SCIR_CPU_HB_INTERVAL;
743 add_timer_on(timer, cpu);
744 uv_cpu_hub_info(cpu)->scir.enabled = 1;
745
746 /* also ensure that boot cpu is enabled */
747 cpu = 0;
748 }
749 }
750
751 #ifdef CONFIG_HOTPLUG_CPU
uv_heartbeat_disable(int cpu)752 static void uv_heartbeat_disable(int cpu)
753 {
754 if (uv_cpu_hub_info(cpu)->scir.enabled) {
755 uv_cpu_hub_info(cpu)->scir.enabled = 0;
756 del_timer(&uv_cpu_hub_info(cpu)->scir.timer);
757 }
758 uv_set_cpu_scir_bits(cpu, 0xff);
759 }
760
761 /*
762 * cpu hotplug notifier
763 */
uv_scir_cpu_notify(struct notifier_block * self,unsigned long action,void * hcpu)764 static int uv_scir_cpu_notify(struct notifier_block *self, unsigned long action,
765 void *hcpu)
766 {
767 long cpu = (long)hcpu;
768
769 switch (action) {
770 case CPU_ONLINE:
771 uv_heartbeat_enable(cpu);
772 break;
773 case CPU_DOWN_PREPARE:
774 uv_heartbeat_disable(cpu);
775 break;
776 default:
777 break;
778 }
779 return NOTIFY_OK;
780 }
781
uv_scir_register_cpu_notifier(void)782 static __init void uv_scir_register_cpu_notifier(void)
783 {
784 hotcpu_notifier(uv_scir_cpu_notify, 0);
785 }
786
787 #else /* !CONFIG_HOTPLUG_CPU */
788
uv_scir_register_cpu_notifier(void)789 static __init void uv_scir_register_cpu_notifier(void)
790 {
791 }
792
uv_init_heartbeat(void)793 static __init int uv_init_heartbeat(void)
794 {
795 int cpu;
796
797 if (is_uv_system())
798 for_each_online_cpu(cpu)
799 uv_heartbeat_enable(cpu);
800 return 0;
801 }
802
803 late_initcall(uv_init_heartbeat);
804
805 #endif /* !CONFIG_HOTPLUG_CPU */
806
807 /* Direct Legacy VGA I/O traffic to designated IOH */
uv_set_vga_state(struct pci_dev * pdev,bool decode,unsigned int command_bits,u32 flags)808 int uv_set_vga_state(struct pci_dev *pdev, bool decode,
809 unsigned int command_bits, u32 flags)
810 {
811 int domain, bus, rc;
812
813 PR_DEVEL("devfn %x decode %d cmd %x flags %d\n",
814 pdev->devfn, decode, command_bits, flags);
815
816 if (!(flags & PCI_VGA_STATE_CHANGE_BRIDGE))
817 return 0;
818
819 if ((command_bits & PCI_COMMAND_IO) == 0)
820 return 0;
821
822 domain = pci_domain_nr(pdev->bus);
823 bus = pdev->bus->number;
824
825 rc = uv_bios_set_legacy_vga_target(decode, domain, bus);
826 PR_DEVEL("vga decode %d %x:%x, rc: %d\n", decode, domain, bus, rc);
827
828 return rc;
829 }
830
831 /*
832 * Called on each cpu to initialize the per_cpu UV data area.
833 * FIXME: hotplug not supported yet
834 */
uv_cpu_init(void)835 void uv_cpu_init(void)
836 {
837 /* CPU 0 initilization will be done via uv_system_init. */
838 if (!uv_blade_info)
839 return;
840
841 uv_blade_info[uv_numa_blade_id()].nr_online_cpus++;
842
843 if (get_uv_system_type() == UV_NON_UNIQUE_APIC)
844 set_x2apic_extra_bits(uv_hub_info->pnode);
845 }
846
uv_system_init(void)847 void __init uv_system_init(void)
848 {
849 union uvh_rh_gam_config_mmr_u m_n_config;
850 union uvh_node_id_u node_id;
851 unsigned long gnode_upper, lowmem_redir_base, lowmem_redir_size;
852 int bytes, nid, cpu, lcpu, pnode, blade, i, j, m_val, n_val;
853 int gnode_extra, min_pnode = 999999, max_pnode = -1;
854 unsigned long mmr_base, present, paddr;
855 unsigned short pnode_mask;
856 unsigned char n_lshift;
857 char *hub = (is_uv1_hub() ? "UV1" :
858 (is_uv2_hub() ? "UV2" :
859 "UV3"));
860
861 pr_info("UV: Found %s hub\n", hub);
862 map_low_mmrs();
863
864 m_n_config.v = uv_read_local_mmr(UVH_RH_GAM_CONFIG_MMR );
865 m_val = m_n_config.s.m_skt;
866 n_val = m_n_config.s.n_skt;
867 pnode_mask = (1 << n_val) - 1;
868 n_lshift = get_n_lshift(m_val);
869 mmr_base =
870 uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR) &
871 ~UV_MMR_ENABLE;
872
873 node_id.v = uv_read_local_mmr(UVH_NODE_ID);
874 gnode_extra = (node_id.s.node_id & ~((1 << n_val) - 1)) >> 1;
875 gnode_upper = ((unsigned long)gnode_extra << m_val);
876 pr_info("UV: N:%d M:%d pnode_mask:0x%x gnode_upper/extra:0x%lx/0x%x n_lshift 0x%x\n",
877 n_val, m_val, pnode_mask, gnode_upper, gnode_extra,
878 n_lshift);
879
880 pr_info("UV: global MMR base 0x%lx\n", mmr_base);
881
882 for(i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++)
883 uv_possible_blades +=
884 hweight64(uv_read_local_mmr( UVH_NODE_PRESENT_TABLE + i * 8));
885
886 /* uv_num_possible_blades() is really the hub count */
887 pr_info("UV: Found %d blades, %d hubs\n",
888 is_uv1_hub() ? uv_num_possible_blades() :
889 (uv_num_possible_blades() + 1) / 2,
890 uv_num_possible_blades());
891
892 bytes = sizeof(struct uv_blade_info) * uv_num_possible_blades();
893 uv_blade_info = kzalloc(bytes, GFP_KERNEL);
894 BUG_ON(!uv_blade_info);
895
896 for (blade = 0; blade < uv_num_possible_blades(); blade++)
897 uv_blade_info[blade].memory_nid = -1;
898
899 get_lowmem_redirect(&lowmem_redir_base, &lowmem_redir_size);
900
901 bytes = sizeof(uv_node_to_blade[0]) * num_possible_nodes();
902 uv_node_to_blade = kmalloc(bytes, GFP_KERNEL);
903 BUG_ON(!uv_node_to_blade);
904 memset(uv_node_to_blade, 255, bytes);
905
906 bytes = sizeof(uv_cpu_to_blade[0]) * num_possible_cpus();
907 uv_cpu_to_blade = kmalloc(bytes, GFP_KERNEL);
908 BUG_ON(!uv_cpu_to_blade);
909 memset(uv_cpu_to_blade, 255, bytes);
910
911 blade = 0;
912 for (i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++) {
913 present = uv_read_local_mmr(UVH_NODE_PRESENT_TABLE + i * 8);
914 for (j = 0; j < 64; j++) {
915 if (!test_bit(j, &present))
916 continue;
917 pnode = (i * 64 + j) & pnode_mask;
918 uv_blade_info[blade].pnode = pnode;
919 uv_blade_info[blade].nr_possible_cpus = 0;
920 uv_blade_info[blade].nr_online_cpus = 0;
921 spin_lock_init(&uv_blade_info[blade].nmi_lock);
922 min_pnode = min(pnode, min_pnode);
923 max_pnode = max(pnode, max_pnode);
924 blade++;
925 }
926 }
927
928 uv_bios_init();
929 uv_bios_get_sn_info(0, &uv_type, &sn_partition_id, &sn_coherency_id,
930 &sn_region_size, &system_serial_number);
931 uv_rtc_init();
932
933 for_each_present_cpu(cpu) {
934 int apicid = per_cpu(x86_cpu_to_apicid, cpu);
935
936 nid = cpu_to_node(cpu);
937 /*
938 * apic_pnode_shift must be set before calling uv_apicid_to_pnode();
939 */
940 uv_cpu_hub_info(cpu)->pnode_mask = pnode_mask;
941 uv_cpu_hub_info(cpu)->apic_pnode_shift = uvh_apicid.s.pnode_shift;
942 uv_cpu_hub_info(cpu)->hub_revision = uv_hub_info->hub_revision;
943
944 uv_cpu_hub_info(cpu)->m_shift = 64 - m_val;
945 uv_cpu_hub_info(cpu)->n_lshift = n_lshift;
946
947 pnode = uv_apicid_to_pnode(apicid);
948 blade = boot_pnode_to_blade(pnode);
949 lcpu = uv_blade_info[blade].nr_possible_cpus;
950 uv_blade_info[blade].nr_possible_cpus++;
951
952 /* Any node on the blade, else will contain -1. */
953 uv_blade_info[blade].memory_nid = nid;
954
955 uv_cpu_hub_info(cpu)->lowmem_remap_base = lowmem_redir_base;
956 uv_cpu_hub_info(cpu)->lowmem_remap_top = lowmem_redir_size;
957 uv_cpu_hub_info(cpu)->m_val = m_val;
958 uv_cpu_hub_info(cpu)->n_val = n_val;
959 uv_cpu_hub_info(cpu)->numa_blade_id = blade;
960 uv_cpu_hub_info(cpu)->blade_processor_id = lcpu;
961 uv_cpu_hub_info(cpu)->pnode = pnode;
962 uv_cpu_hub_info(cpu)->gpa_mask = (1UL << (m_val + n_val)) - 1;
963 uv_cpu_hub_info(cpu)->gnode_upper = gnode_upper;
964 uv_cpu_hub_info(cpu)->gnode_extra = gnode_extra;
965 uv_cpu_hub_info(cpu)->global_mmr_base = mmr_base;
966 uv_cpu_hub_info(cpu)->coherency_domain_number = sn_coherency_id;
967 uv_cpu_hub_info(cpu)->scir.offset = uv_scir_offset(apicid);
968 uv_node_to_blade[nid] = blade;
969 uv_cpu_to_blade[cpu] = blade;
970 }
971
972 /* Add blade/pnode info for nodes without cpus */
973 for_each_online_node(nid) {
974 if (uv_node_to_blade[nid] >= 0)
975 continue;
976 paddr = node_start_pfn(nid) << PAGE_SHIFT;
977 pnode = uv_gpa_to_pnode(uv_soc_phys_ram_to_gpa(paddr));
978 blade = boot_pnode_to_blade(pnode);
979 uv_node_to_blade[nid] = blade;
980 }
981
982 map_gru_high(max_pnode);
983 map_mmr_high(max_pnode);
984 map_mmioh_high(min_pnode, max_pnode);
985
986 uv_nmi_setup();
987 uv_cpu_init();
988 uv_scir_register_cpu_notifier();
989 proc_mkdir("sgi_uv", NULL);
990
991 /* register Legacy VGA I/O redirection handler */
992 pci_register_set_vga_state(uv_set_vga_state);
993
994 /*
995 * For a kdump kernel the reset must be BOOT_ACPI, not BOOT_EFI, as
996 * EFI is not enabled in the kdump kernel.
997 */
998 if (is_kdump_kernel())
999 reboot_type = BOOT_ACPI;
1000 }
1001
1002 apic_driver(apic_x2apic_uv_x);
1003