1 /*
2 * Intel CPU Microcode Update Driver for Linux
3 *
4 * Copyright (C) 2000-2006 Tigran Aivazian <tigran@aivazian.fsnet.co.uk>
5 * 2006 Shaohua Li <shaohua.li@intel.com>
6 *
7 * This driver allows to upgrade microcode on Intel processors
8 * belonging to IA-32 family - PentiumPro, Pentium II,
9 * Pentium III, Xeon, Pentium 4, etc.
10 *
11 * Reference: Section 8.11 of Volume 3a, IA-32 Intel? Architecture
12 * Software Developer's Manual
13 * Order Number 253668 or free download from:
14 *
15 * http://developer.intel.com/Assets/PDF/manual/253668.pdf
16 *
17 * For more information, go to http://www.urbanmyth.org/microcode
18 *
19 * This program is free software; you can redistribute it and/or
20 * modify it under the terms of the GNU General Public License
21 * as published by the Free Software Foundation; either version
22 * 2 of the License, or (at your option) any later version.
23 *
24 * 1.0 16 Feb 2000, Tigran Aivazian <tigran@sco.com>
25 * Initial release.
26 * 1.01 18 Feb 2000, Tigran Aivazian <tigran@sco.com>
27 * Added read() support + cleanups.
28 * 1.02 21 Feb 2000, Tigran Aivazian <tigran@sco.com>
29 * Added 'device trimming' support. open(O_WRONLY) zeroes
30 * and frees the saved copy of applied microcode.
31 * 1.03 29 Feb 2000, Tigran Aivazian <tigran@sco.com>
32 * Made to use devfs (/dev/cpu/microcode) + cleanups.
33 * 1.04 06 Jun 2000, Simon Trimmer <simon@veritas.com>
34 * Added misc device support (now uses both devfs and misc).
35 * Added MICROCODE_IOCFREE ioctl to clear memory.
36 * 1.05 09 Jun 2000, Simon Trimmer <simon@veritas.com>
37 * Messages for error cases (non Intel & no suitable microcode).
38 * 1.06 03 Aug 2000, Tigran Aivazian <tigran@veritas.com>
39 * Removed ->release(). Removed exclusive open and status bitmap.
40 * Added microcode_rwsem to serialize read()/write()/ioctl().
41 * Removed global kernel lock usage.
42 * 1.07 07 Sep 2000, Tigran Aivazian <tigran@veritas.com>
43 * Write 0 to 0x8B msr and then cpuid before reading revision,
44 * so that it works even if there were no update done by the
45 * BIOS. Otherwise, reading from 0x8B gives junk (which happened
46 * to be 0 on my machine which is why it worked even when I
47 * disabled update by the BIOS)
48 * Thanks to Eric W. Biederman <ebiederman@lnxi.com> for the fix.
49 * 1.08 11 Dec 2000, Richard Schaal <richard.schaal@intel.com> and
50 * Tigran Aivazian <tigran@veritas.com>
51 * Intel Pentium 4 processor support and bugfixes.
52 * 1.09 30 Oct 2001, Tigran Aivazian <tigran@veritas.com>
53 * Bugfix for HT (Hyper-Threading) enabled processors
54 * whereby processor resources are shared by all logical processors
55 * in a single CPU package.
56 * 1.10 28 Feb 2002 Asit K Mallick <asit.k.mallick@intel.com> and
57 * Tigran Aivazian <tigran@veritas.com>,
58 * Serialize updates as required on HT processors due to
59 * speculative nature of implementation.
60 * 1.11 22 Mar 2002 Tigran Aivazian <tigran@veritas.com>
61 * Fix the panic when writing zero-length microcode chunk.
62 * 1.12 29 Sep 2003 Nitin Kamble <nitin.a.kamble@intel.com>,
63 * Jun Nakajima <jun.nakajima@intel.com>
64 * Support for the microcode updates in the new format.
65 * 1.13 10 Oct 2003 Tigran Aivazian <tigran@veritas.com>
66 * Removed ->read() method and obsoleted MICROCODE_IOCFREE ioctl
67 * because we no longer hold a copy of applied microcode
68 * in kernel memory.
69 * 1.14 25 Jun 2004 Tigran Aivazian <tigran@veritas.com>
70 * Fix sigmatch() macro to handle old CPUs with pf == 0.
71 * Thanks to Stuart Swales for pointing out this bug.
72 */
73
74 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
75
76 #include <linux/firmware.h>
77 #include <linux/uaccess.h>
78 #include <linux/kernel.h>
79 #include <linux/module.h>
80 #include <linux/vmalloc.h>
81
82 #include <asm/microcode_intel.h>
83 #include <asm/processor.h>
84 #include <asm/msr.h>
85
86 MODULE_DESCRIPTION("Microcode Update Driver");
87 MODULE_AUTHOR("Tigran Aivazian <tigran@aivazian.fsnet.co.uk>");
88 MODULE_LICENSE("GPL");
89
90 /* last level cache size per core */
91 static int llc_size_per_core;
92
collect_cpu_info(int cpu_num,struct cpu_signature * csig)93 static int collect_cpu_info(int cpu_num, struct cpu_signature *csig)
94 {
95 struct cpuinfo_x86 *c = &cpu_data(cpu_num);
96 unsigned int val[2];
97
98 memset(csig, 0, sizeof(*csig));
99
100 csig->sig = cpuid_eax(0x00000001);
101
102 if ((c->x86_model >= 5) || (c->x86 > 6)) {
103 /* get processor flags from MSR 0x17 */
104 rdmsr(MSR_IA32_PLATFORM_ID, val[0], val[1]);
105 csig->pf = 1 << ((val[1] >> 18) & 7);
106 }
107
108 csig->rev = c->microcode;
109 pr_info("CPU%d sig=0x%x, pf=0x%x, revision=0x%x\n",
110 cpu_num, csig->sig, csig->pf, csig->rev);
111
112 return 0;
113 }
114
115 /*
116 * return 0 - no update found
117 * return 1 - found update
118 */
get_matching_mc(struct microcode_intel * mc_intel,int cpu)119 static int get_matching_mc(struct microcode_intel *mc_intel, int cpu)
120 {
121 struct cpu_signature cpu_sig;
122 unsigned int csig, cpf, crev;
123
124 collect_cpu_info(cpu, &cpu_sig);
125
126 csig = cpu_sig.sig;
127 cpf = cpu_sig.pf;
128 crev = cpu_sig.rev;
129
130 return get_matching_microcode(csig, cpf, mc_intel, crev);
131 }
132
apply_microcode_intel(int cpu)133 static int apply_microcode_intel(int cpu)
134 {
135 struct microcode_intel *mc_intel;
136 struct ucode_cpu_info *uci;
137 unsigned int val[2];
138 int cpu_num = raw_smp_processor_id();
139 struct cpuinfo_x86 *c = &cpu_data(cpu_num);
140
141 uci = ucode_cpu_info + cpu;
142 mc_intel = uci->mc;
143
144 /* We should bind the task to the CPU */
145 BUG_ON(cpu_num != cpu);
146
147 if (mc_intel == NULL)
148 return 0;
149
150 /*
151 * Microcode on this CPU could be updated earlier. Only apply the
152 * microcode patch in mc_intel when it is newer than the one on this
153 * CPU.
154 */
155 if (get_matching_mc(mc_intel, cpu) == 0)
156 return 0;
157
158 /* write microcode via MSR 0x79 */
159 wrmsr(MSR_IA32_UCODE_WRITE,
160 (unsigned long) mc_intel->bits,
161 (unsigned long) mc_intel->bits >> 16 >> 16);
162 wrmsr(MSR_IA32_UCODE_REV, 0, 0);
163
164 /* As documented in the SDM: Do a CPUID 1 here */
165 sync_core();
166
167 /* get the current revision from MSR 0x8B */
168 rdmsr(MSR_IA32_UCODE_REV, val[0], val[1]);
169
170 if (val[1] != mc_intel->hdr.rev) {
171 pr_err("CPU%d update to revision 0x%x failed\n",
172 cpu_num, mc_intel->hdr.rev);
173 return -1;
174 }
175 pr_info("CPU%d updated to revision 0x%x, date = %04x-%02x-%02x\n",
176 cpu_num, val[1],
177 mc_intel->hdr.date & 0xffff,
178 mc_intel->hdr.date >> 24,
179 (mc_intel->hdr.date >> 16) & 0xff);
180
181 uci->cpu_sig.rev = val[1];
182 c->microcode = val[1];
183
184 return 0;
185 }
186
generic_load_microcode(int cpu,void * data,size_t size,int (* get_ucode_data)(void *,const void *,size_t))187 static enum ucode_state generic_load_microcode(int cpu, void *data, size_t size,
188 int (*get_ucode_data)(void *, const void *, size_t))
189 {
190 struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
191 u8 *ucode_ptr = data, *new_mc = NULL, *mc = NULL;
192 int new_rev = uci->cpu_sig.rev;
193 unsigned int leftover = size;
194 enum ucode_state state = UCODE_OK;
195 unsigned int curr_mc_size = 0;
196 unsigned int csig, cpf;
197
198 while (leftover) {
199 struct microcode_header_intel mc_header;
200 unsigned int mc_size;
201
202 if (get_ucode_data(&mc_header, ucode_ptr, sizeof(mc_header)))
203 break;
204
205 mc_size = get_totalsize(&mc_header);
206 if (!mc_size || mc_size > leftover) {
207 pr_err("error! Bad data in microcode data file\n");
208 break;
209 }
210
211 /* For performance reasons, reuse mc area when possible */
212 if (!mc || mc_size > curr_mc_size) {
213 vfree(mc);
214 mc = vmalloc(mc_size);
215 if (!mc)
216 break;
217 curr_mc_size = mc_size;
218 }
219
220 if (get_ucode_data(mc, ucode_ptr, mc_size) ||
221 microcode_sanity_check(mc, 1) < 0) {
222 break;
223 }
224
225 csig = uci->cpu_sig.sig;
226 cpf = uci->cpu_sig.pf;
227 if (get_matching_microcode(csig, cpf, mc, new_rev)) {
228 vfree(new_mc);
229 new_rev = mc_header.rev;
230 new_mc = mc;
231 mc = NULL; /* trigger new vmalloc */
232 }
233
234 ucode_ptr += mc_size;
235 leftover -= mc_size;
236 }
237
238 vfree(mc);
239
240 if (leftover) {
241 vfree(new_mc);
242 state = UCODE_ERROR;
243 goto out;
244 }
245
246 if (!new_mc) {
247 state = UCODE_NFOUND;
248 goto out;
249 }
250
251 vfree(uci->mc);
252 uci->mc = (struct microcode_intel *)new_mc;
253
254 /*
255 * If early loading microcode is supported, save this mc into
256 * permanent memory. So it will be loaded early when a CPU is hot added
257 * or resumes.
258 */
259 save_mc_for_early(new_mc);
260
261 pr_debug("CPU%d found a matching microcode update with version 0x%x (current=0x%x)\n",
262 cpu, new_rev, uci->cpu_sig.rev);
263 out:
264 return state;
265 }
266
get_ucode_fw(void * to,const void * from,size_t n)267 static int get_ucode_fw(void *to, const void *from, size_t n)
268 {
269 memcpy(to, from, n);
270 return 0;
271 }
272
is_blacklisted(unsigned int cpu)273 static bool is_blacklisted(unsigned int cpu)
274 {
275 struct cpuinfo_x86 *c = &cpu_data(cpu);
276
277 /*
278 * Late loading on model 79 with microcode revision less than 0x0b000021
279 * and LLC size per core bigger than 2.5MB may result in a system hang.
280 * This behavior is documented in item BDF90, #334165 (Intel Xeon
281 * Processor E7-8800/4800 v4 Product Family).
282 */
283 if (c->x86 == 6 &&
284 c->x86_model == 79 &&
285 c->x86_mask == 0x01 &&
286 llc_size_per_core > 2621440 &&
287 c->microcode < 0x0b000021) {
288 pr_err_once("Erratum BDF90: late loading with revision < 0x0b000021 (0x%x) disabled.\n", c->microcode);
289 pr_err_once("Please consider either early loading through initrd/built-in or a potential BIOS update.\n");
290 return true;
291 }
292
293 return false;
294 }
295
request_microcode_fw(int cpu,struct device * device,bool refresh_fw)296 static enum ucode_state request_microcode_fw(int cpu, struct device *device,
297 bool refresh_fw)
298 {
299 char name[30];
300 struct cpuinfo_x86 *c = &cpu_data(cpu);
301 const struct firmware *firmware;
302 enum ucode_state ret;
303
304 if (is_blacklisted(cpu))
305 return UCODE_NFOUND;
306
307 sprintf(name, "intel-ucode/%02x-%02x-%02x",
308 c->x86, c->x86_model, c->x86_mask);
309
310 if (request_firmware_direct(&firmware, name, device)) {
311 pr_debug("data file %s load failed\n", name);
312 return UCODE_NFOUND;
313 }
314
315 ret = generic_load_microcode(cpu, (void *)firmware->data,
316 firmware->size, &get_ucode_fw);
317
318 release_firmware(firmware);
319
320 return ret;
321 }
322
get_ucode_user(void * to,const void * from,size_t n)323 static int get_ucode_user(void *to, const void *from, size_t n)
324 {
325 return copy_from_user(to, from, n);
326 }
327
328 static enum ucode_state
request_microcode_user(int cpu,const void __user * buf,size_t size)329 request_microcode_user(int cpu, const void __user *buf, size_t size)
330 {
331 if (is_blacklisted(cpu))
332 return UCODE_NFOUND;
333
334 return generic_load_microcode(cpu, (void *)buf, size, &get_ucode_user);
335 }
336
microcode_fini_cpu(int cpu)337 static void microcode_fini_cpu(int cpu)
338 {
339 struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
340
341 vfree(uci->mc);
342 uci->mc = NULL;
343 }
344
345 static struct microcode_ops microcode_intel_ops = {
346 .request_microcode_user = request_microcode_user,
347 .request_microcode_fw = request_microcode_fw,
348 .collect_cpu_info = collect_cpu_info,
349 .apply_microcode = apply_microcode_intel,
350 .microcode_fini_cpu = microcode_fini_cpu,
351 };
352
calc_llc_size_per_core(struct cpuinfo_x86 * c)353 static int __init calc_llc_size_per_core(struct cpuinfo_x86 *c)
354 {
355 u64 llc_size = c->x86_cache_size * 1024;
356
357 do_div(llc_size, c->x86_max_cores);
358
359 return (int)llc_size;
360 }
361
init_intel_microcode(void)362 struct microcode_ops * __init init_intel_microcode(void)
363 {
364 struct cpuinfo_x86 *c = &cpu_data(0);
365
366 if (c->x86_vendor != X86_VENDOR_INTEL || c->x86 < 6 ||
367 cpu_has(c, X86_FEATURE_IA64)) {
368 pr_err("Intel CPU family 0x%x not supported\n", c->x86);
369 return NULL;
370 }
371
372 llc_size_per_core = calc_llc_size_per_core(c);
373
374 return µcode_intel_ops;
375 }
376
377