1 #include <linux/perf_event.h>
2 #include <linux/types.h>
3
4 #include <asm/perf_event.h>
5 #include <asm/msr.h>
6 #include <asm/insn.h>
7
8 #include "perf_event.h"
9
10 enum {
11 LBR_FORMAT_32 = 0x00,
12 LBR_FORMAT_LIP = 0x01,
13 LBR_FORMAT_EIP = 0x02,
14 LBR_FORMAT_EIP_FLAGS = 0x03,
15 LBR_FORMAT_EIP_FLAGS2 = 0x04,
16 LBR_FORMAT_MAX_KNOWN = LBR_FORMAT_EIP_FLAGS2,
17 };
18
19 static enum {
20 LBR_EIP_FLAGS = 1,
21 LBR_TSX = 2,
22 } lbr_desc[LBR_FORMAT_MAX_KNOWN + 1] = {
23 [LBR_FORMAT_EIP_FLAGS] = LBR_EIP_FLAGS,
24 [LBR_FORMAT_EIP_FLAGS2] = LBR_EIP_FLAGS | LBR_TSX,
25 };
26
27 /*
28 * Intel LBR_SELECT bits
29 * Intel Vol3a, April 2011, Section 16.7 Table 16-10
30 *
31 * Hardware branch filter (not available on all CPUs)
32 */
33 #define LBR_KERNEL_BIT 0 /* do not capture at ring0 */
34 #define LBR_USER_BIT 1 /* do not capture at ring > 0 */
35 #define LBR_JCC_BIT 2 /* do not capture conditional branches */
36 #define LBR_REL_CALL_BIT 3 /* do not capture relative calls */
37 #define LBR_IND_CALL_BIT 4 /* do not capture indirect calls */
38 #define LBR_RETURN_BIT 5 /* do not capture near returns */
39 #define LBR_IND_JMP_BIT 6 /* do not capture indirect jumps */
40 #define LBR_REL_JMP_BIT 7 /* do not capture relative jumps */
41 #define LBR_FAR_BIT 8 /* do not capture far branches */
42
43 #define LBR_KERNEL (1 << LBR_KERNEL_BIT)
44 #define LBR_USER (1 << LBR_USER_BIT)
45 #define LBR_JCC (1 << LBR_JCC_BIT)
46 #define LBR_REL_CALL (1 << LBR_REL_CALL_BIT)
47 #define LBR_IND_CALL (1 << LBR_IND_CALL_BIT)
48 #define LBR_RETURN (1 << LBR_RETURN_BIT)
49 #define LBR_REL_JMP (1 << LBR_REL_JMP_BIT)
50 #define LBR_IND_JMP (1 << LBR_IND_JMP_BIT)
51 #define LBR_FAR (1 << LBR_FAR_BIT)
52
53 #define LBR_PLM (LBR_KERNEL | LBR_USER)
54
55 #define LBR_SEL_MASK 0x1ff /* valid bits in LBR_SELECT */
56 #define LBR_NOT_SUPP -1 /* LBR filter not supported */
57 #define LBR_IGN 0 /* ignored */
58
59 #define LBR_ANY \
60 (LBR_JCC |\
61 LBR_REL_CALL |\
62 LBR_IND_CALL |\
63 LBR_RETURN |\
64 LBR_REL_JMP |\
65 LBR_IND_JMP |\
66 LBR_FAR)
67
68 #define LBR_FROM_FLAG_MISPRED (1ULL << 63)
69 #define LBR_FROM_FLAG_IN_TX (1ULL << 62)
70 #define LBR_FROM_FLAG_ABORT (1ULL << 61)
71
72 #define for_each_branch_sample_type(x) \
73 for ((x) = PERF_SAMPLE_BRANCH_USER; \
74 (x) < PERF_SAMPLE_BRANCH_MAX; (x) <<= 1)
75
76 /*
77 * x86control flow change classification
78 * x86control flow changes include branches, interrupts, traps, faults
79 */
80 enum {
81 X86_BR_NONE = 0, /* unknown */
82
83 X86_BR_USER = 1 << 0, /* branch target is user */
84 X86_BR_KERNEL = 1 << 1, /* branch target is kernel */
85
86 X86_BR_CALL = 1 << 2, /* call */
87 X86_BR_RET = 1 << 3, /* return */
88 X86_BR_SYSCALL = 1 << 4, /* syscall */
89 X86_BR_SYSRET = 1 << 5, /* syscall return */
90 X86_BR_INT = 1 << 6, /* sw interrupt */
91 X86_BR_IRET = 1 << 7, /* return from interrupt */
92 X86_BR_JCC = 1 << 8, /* conditional */
93 X86_BR_JMP = 1 << 9, /* jump */
94 X86_BR_IRQ = 1 << 10,/* hw interrupt or trap or fault */
95 X86_BR_IND_CALL = 1 << 11,/* indirect calls */
96 X86_BR_ABORT = 1 << 12,/* transaction abort */
97 X86_BR_IN_TX = 1 << 13,/* in transaction */
98 X86_BR_NO_TX = 1 << 14,/* not in transaction */
99 };
100
101 #define X86_BR_PLM (X86_BR_USER | X86_BR_KERNEL)
102 #define X86_BR_ANYTX (X86_BR_NO_TX | X86_BR_IN_TX)
103
104 #define X86_BR_ANY \
105 (X86_BR_CALL |\
106 X86_BR_RET |\
107 X86_BR_SYSCALL |\
108 X86_BR_SYSRET |\
109 X86_BR_INT |\
110 X86_BR_IRET |\
111 X86_BR_JCC |\
112 X86_BR_JMP |\
113 X86_BR_IRQ |\
114 X86_BR_ABORT |\
115 X86_BR_IND_CALL)
116
117 #define X86_BR_ALL (X86_BR_PLM | X86_BR_ANY)
118
119 #define X86_BR_ANY_CALL \
120 (X86_BR_CALL |\
121 X86_BR_IND_CALL |\
122 X86_BR_SYSCALL |\
123 X86_BR_IRQ |\
124 X86_BR_INT)
125
126 static void intel_pmu_lbr_filter(struct cpu_hw_events *cpuc);
127
128 /*
129 * We only support LBR implementations that have FREEZE_LBRS_ON_PMI
130 * otherwise it becomes near impossible to get a reliable stack.
131 */
132
__intel_pmu_lbr_enable(void)133 static void __intel_pmu_lbr_enable(void)
134 {
135 u64 debugctl;
136 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
137
138 if (cpuc->lbr_sel)
139 wrmsrl(MSR_LBR_SELECT, cpuc->lbr_sel->config);
140
141 rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
142 debugctl |= (DEBUGCTLMSR_LBR | DEBUGCTLMSR_FREEZE_LBRS_ON_PMI);
143 wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
144 }
145
__intel_pmu_lbr_disable(void)146 static void __intel_pmu_lbr_disable(void)
147 {
148 u64 debugctl;
149
150 rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
151 debugctl &= ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_FREEZE_LBRS_ON_PMI);
152 wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
153 }
154
intel_pmu_lbr_reset_32(void)155 static void intel_pmu_lbr_reset_32(void)
156 {
157 int i;
158
159 for (i = 0; i < x86_pmu.lbr_nr; i++)
160 wrmsrl(x86_pmu.lbr_from + i, 0);
161 }
162
intel_pmu_lbr_reset_64(void)163 static void intel_pmu_lbr_reset_64(void)
164 {
165 int i;
166
167 for (i = 0; i < x86_pmu.lbr_nr; i++) {
168 wrmsrl(x86_pmu.lbr_from + i, 0);
169 wrmsrl(x86_pmu.lbr_to + i, 0);
170 }
171 }
172
intel_pmu_lbr_reset(void)173 void intel_pmu_lbr_reset(void)
174 {
175 if (!x86_pmu.lbr_nr)
176 return;
177
178 if (x86_pmu.intel_cap.lbr_format == LBR_FORMAT_32)
179 intel_pmu_lbr_reset_32();
180 else
181 intel_pmu_lbr_reset_64();
182 }
183
intel_pmu_lbr_enable(struct perf_event * event)184 void intel_pmu_lbr_enable(struct perf_event *event)
185 {
186 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
187
188 if (!x86_pmu.lbr_nr)
189 return;
190
191 /*
192 * Reset the LBR stack if we changed task context to
193 * avoid data leaks.
194 */
195 if (event->ctx->task && cpuc->lbr_context != event->ctx) {
196 intel_pmu_lbr_reset();
197 cpuc->lbr_context = event->ctx;
198 }
199 cpuc->br_sel = event->hw.branch_reg.reg;
200
201 cpuc->lbr_users++;
202 }
203
intel_pmu_lbr_disable(struct perf_event * event)204 void intel_pmu_lbr_disable(struct perf_event *event)
205 {
206 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
207
208 if (!x86_pmu.lbr_nr)
209 return;
210
211 cpuc->lbr_users--;
212 WARN_ON_ONCE(cpuc->lbr_users < 0);
213
214 if (cpuc->enabled && !cpuc->lbr_users) {
215 __intel_pmu_lbr_disable();
216 /* avoid stale pointer */
217 cpuc->lbr_context = NULL;
218 }
219 }
220
intel_pmu_lbr_enable_all(void)221 void intel_pmu_lbr_enable_all(void)
222 {
223 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
224
225 if (cpuc->lbr_users)
226 __intel_pmu_lbr_enable();
227 }
228
intel_pmu_lbr_disable_all(void)229 void intel_pmu_lbr_disable_all(void)
230 {
231 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
232
233 if (cpuc->lbr_users)
234 __intel_pmu_lbr_disable();
235 }
236
237 /*
238 * TOS = most recently recorded branch
239 */
intel_pmu_lbr_tos(void)240 static inline u64 intel_pmu_lbr_tos(void)
241 {
242 u64 tos;
243
244 rdmsrl(x86_pmu.lbr_tos, tos);
245
246 return tos;
247 }
248
intel_pmu_lbr_read_32(struct cpu_hw_events * cpuc)249 static void intel_pmu_lbr_read_32(struct cpu_hw_events *cpuc)
250 {
251 unsigned long mask = x86_pmu.lbr_nr - 1;
252 u64 tos = intel_pmu_lbr_tos();
253 int i;
254
255 for (i = 0; i < x86_pmu.lbr_nr; i++) {
256 unsigned long lbr_idx = (tos - i) & mask;
257 union {
258 struct {
259 u32 from;
260 u32 to;
261 };
262 u64 lbr;
263 } msr_lastbranch;
264
265 rdmsrl(x86_pmu.lbr_from + lbr_idx, msr_lastbranch.lbr);
266
267 cpuc->lbr_entries[i].from = msr_lastbranch.from;
268 cpuc->lbr_entries[i].to = msr_lastbranch.to;
269 cpuc->lbr_entries[i].mispred = 0;
270 cpuc->lbr_entries[i].predicted = 0;
271 cpuc->lbr_entries[i].in_tx = 0;
272 cpuc->lbr_entries[i].abort = 0;
273 cpuc->lbr_entries[i].reserved = 0;
274 }
275 cpuc->lbr_stack.nr = i;
276 }
277
278 /*
279 * Due to lack of segmentation in Linux the effective address (offset)
280 * is the same as the linear address, allowing us to merge the LIP and EIP
281 * LBR formats.
282 */
intel_pmu_lbr_read_64(struct cpu_hw_events * cpuc)283 static void intel_pmu_lbr_read_64(struct cpu_hw_events *cpuc)
284 {
285 unsigned long mask = x86_pmu.lbr_nr - 1;
286 int lbr_format = x86_pmu.intel_cap.lbr_format;
287 u64 tos = intel_pmu_lbr_tos();
288 int i;
289 int out = 0;
290
291 for (i = 0; i < x86_pmu.lbr_nr; i++) {
292 unsigned long lbr_idx = (tos - i) & mask;
293 u64 from, to, mis = 0, pred = 0, in_tx = 0, abort = 0;
294 int skip = 0;
295 int lbr_flags = lbr_desc[lbr_format];
296
297 rdmsrl(x86_pmu.lbr_from + lbr_idx, from);
298 rdmsrl(x86_pmu.lbr_to + lbr_idx, to);
299
300 if (lbr_flags & LBR_EIP_FLAGS) {
301 mis = !!(from & LBR_FROM_FLAG_MISPRED);
302 pred = !mis;
303 skip = 1;
304 }
305 if (lbr_flags & LBR_TSX) {
306 in_tx = !!(from & LBR_FROM_FLAG_IN_TX);
307 abort = !!(from & LBR_FROM_FLAG_ABORT);
308 skip = 3;
309 }
310 from = (u64)((((s64)from) << skip) >> skip);
311
312 /*
313 * Some CPUs report duplicated abort records,
314 * with the second entry not having an abort bit set.
315 * Skip them here. This loop runs backwards,
316 * so we need to undo the previous record.
317 * If the abort just happened outside the window
318 * the extra entry cannot be removed.
319 */
320 if (abort && x86_pmu.lbr_double_abort && out > 0)
321 out--;
322
323 cpuc->lbr_entries[out].from = from;
324 cpuc->lbr_entries[out].to = to;
325 cpuc->lbr_entries[out].mispred = mis;
326 cpuc->lbr_entries[out].predicted = pred;
327 cpuc->lbr_entries[out].in_tx = in_tx;
328 cpuc->lbr_entries[out].abort = abort;
329 cpuc->lbr_entries[out].reserved = 0;
330 out++;
331 }
332 cpuc->lbr_stack.nr = out;
333 }
334
intel_pmu_lbr_read(void)335 void intel_pmu_lbr_read(void)
336 {
337 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
338
339 if (!cpuc->lbr_users)
340 return;
341
342 if (x86_pmu.intel_cap.lbr_format == LBR_FORMAT_32)
343 intel_pmu_lbr_read_32(cpuc);
344 else
345 intel_pmu_lbr_read_64(cpuc);
346
347 intel_pmu_lbr_filter(cpuc);
348 }
349
350 /*
351 * SW filter is used:
352 * - in case there is no HW filter
353 * - in case the HW filter has errata or limitations
354 */
intel_pmu_setup_sw_lbr_filter(struct perf_event * event)355 static void intel_pmu_setup_sw_lbr_filter(struct perf_event *event)
356 {
357 u64 br_type = event->attr.branch_sample_type;
358 int mask = 0;
359
360 if (br_type & PERF_SAMPLE_BRANCH_USER)
361 mask |= X86_BR_USER;
362
363 if (br_type & PERF_SAMPLE_BRANCH_KERNEL)
364 mask |= X86_BR_KERNEL;
365
366 /* we ignore BRANCH_HV here */
367
368 if (br_type & PERF_SAMPLE_BRANCH_ANY)
369 mask |= X86_BR_ANY;
370
371 if (br_type & PERF_SAMPLE_BRANCH_ANY_CALL)
372 mask |= X86_BR_ANY_CALL;
373
374 if (br_type & PERF_SAMPLE_BRANCH_ANY_RETURN)
375 mask |= X86_BR_RET | X86_BR_IRET | X86_BR_SYSRET;
376
377 if (br_type & PERF_SAMPLE_BRANCH_IND_CALL)
378 mask |= X86_BR_IND_CALL;
379
380 if (br_type & PERF_SAMPLE_BRANCH_ABORT_TX)
381 mask |= X86_BR_ABORT;
382
383 if (br_type & PERF_SAMPLE_BRANCH_IN_TX)
384 mask |= X86_BR_IN_TX;
385
386 if (br_type & PERF_SAMPLE_BRANCH_NO_TX)
387 mask |= X86_BR_NO_TX;
388
389 if (br_type & PERF_SAMPLE_BRANCH_COND)
390 mask |= X86_BR_JCC;
391
392 /*
393 * stash actual user request into reg, it may
394 * be used by fixup code for some CPU
395 */
396 event->hw.branch_reg.reg = mask;
397 }
398
399 /*
400 * setup the HW LBR filter
401 * Used only when available, may not be enough to disambiguate
402 * all branches, may need the help of the SW filter
403 */
intel_pmu_setup_hw_lbr_filter(struct perf_event * event)404 static int intel_pmu_setup_hw_lbr_filter(struct perf_event *event)
405 {
406 struct hw_perf_event_extra *reg;
407 u64 br_type = event->attr.branch_sample_type;
408 u64 mask = 0, m;
409 u64 v;
410
411 for_each_branch_sample_type(m) {
412 if (!(br_type & m))
413 continue;
414
415 v = x86_pmu.lbr_sel_map[m];
416 if (v == LBR_NOT_SUPP)
417 return -EOPNOTSUPP;
418
419 if (v != LBR_IGN)
420 mask |= v;
421 }
422 reg = &event->hw.branch_reg;
423 reg->idx = EXTRA_REG_LBR;
424
425 /* LBR_SELECT operates in suppress mode so invert mask */
426 reg->config = ~mask & x86_pmu.lbr_sel_mask;
427
428 return 0;
429 }
430
intel_pmu_setup_lbr_filter(struct perf_event * event)431 int intel_pmu_setup_lbr_filter(struct perf_event *event)
432 {
433 int ret = 0;
434
435 /*
436 * no LBR on this PMU
437 */
438 if (!x86_pmu.lbr_nr)
439 return -EOPNOTSUPP;
440
441 /*
442 * setup SW LBR filter
443 */
444 intel_pmu_setup_sw_lbr_filter(event);
445
446 /*
447 * setup HW LBR filter, if any
448 */
449 if (x86_pmu.lbr_sel_map)
450 ret = intel_pmu_setup_hw_lbr_filter(event);
451
452 return ret;
453 }
454
455 /*
456 * return the type of control flow change at address "from"
457 * intruction is not necessarily a branch (in case of interrupt).
458 *
459 * The branch type returned also includes the priv level of the
460 * target of the control flow change (X86_BR_USER, X86_BR_KERNEL).
461 *
462 * If a branch type is unknown OR the instruction cannot be
463 * decoded (e.g., text page not present), then X86_BR_NONE is
464 * returned.
465 */
branch_type(unsigned long from,unsigned long to,int abort)466 static int branch_type(unsigned long from, unsigned long to, int abort)
467 {
468 struct insn insn;
469 void *addr;
470 int bytes, size = MAX_INSN_SIZE;
471 int ret = X86_BR_NONE;
472 int ext, to_plm, from_plm;
473 u8 buf[MAX_INSN_SIZE];
474 int is64 = 0;
475
476 to_plm = kernel_ip(to) ? X86_BR_KERNEL : X86_BR_USER;
477 from_plm = kernel_ip(from) ? X86_BR_KERNEL : X86_BR_USER;
478
479 /*
480 * maybe zero if lbr did not fill up after a reset by the time
481 * we get a PMU interrupt
482 */
483 if (from == 0 || to == 0)
484 return X86_BR_NONE;
485
486 if (abort)
487 return X86_BR_ABORT | to_plm;
488
489 if (from_plm == X86_BR_USER) {
490 /*
491 * can happen if measuring at the user level only
492 * and we interrupt in a kernel thread, e.g., idle.
493 */
494 if (!current->mm)
495 return X86_BR_NONE;
496
497 /* may fail if text not present */
498 bytes = copy_from_user_nmi(buf, (void __user *)from, size);
499 if (bytes != 0)
500 return X86_BR_NONE;
501
502 addr = buf;
503 } else {
504 /*
505 * The LBR logs any address in the IP, even if the IP just
506 * faulted. This means userspace can control the from address.
507 * Ensure we don't blindy read any address by validating it is
508 * a known text address.
509 */
510 if (kernel_text_address(from))
511 addr = (void *)from;
512 else
513 return X86_BR_NONE;
514 }
515
516 /*
517 * decoder needs to know the ABI especially
518 * on 64-bit systems running 32-bit apps
519 */
520 #ifdef CONFIG_X86_64
521 is64 = kernel_ip((unsigned long)addr) || !test_thread_flag(TIF_IA32);
522 #endif
523 insn_init(&insn, addr, is64);
524 insn_get_opcode(&insn);
525
526 switch (insn.opcode.bytes[0]) {
527 case 0xf:
528 switch (insn.opcode.bytes[1]) {
529 case 0x05: /* syscall */
530 case 0x34: /* sysenter */
531 ret = X86_BR_SYSCALL;
532 break;
533 case 0x07: /* sysret */
534 case 0x35: /* sysexit */
535 ret = X86_BR_SYSRET;
536 break;
537 case 0x80 ... 0x8f: /* conditional */
538 ret = X86_BR_JCC;
539 break;
540 default:
541 ret = X86_BR_NONE;
542 }
543 break;
544 case 0x70 ... 0x7f: /* conditional */
545 ret = X86_BR_JCC;
546 break;
547 case 0xc2: /* near ret */
548 case 0xc3: /* near ret */
549 case 0xca: /* far ret */
550 case 0xcb: /* far ret */
551 ret = X86_BR_RET;
552 break;
553 case 0xcf: /* iret */
554 ret = X86_BR_IRET;
555 break;
556 case 0xcc ... 0xce: /* int */
557 ret = X86_BR_INT;
558 break;
559 case 0xe8: /* call near rel */
560 case 0x9a: /* call far absolute */
561 ret = X86_BR_CALL;
562 break;
563 case 0xe0 ... 0xe3: /* loop jmp */
564 ret = X86_BR_JCC;
565 break;
566 case 0xe9 ... 0xeb: /* jmp */
567 ret = X86_BR_JMP;
568 break;
569 case 0xff: /* call near absolute, call far absolute ind */
570 insn_get_modrm(&insn);
571 ext = (insn.modrm.bytes[0] >> 3) & 0x7;
572 switch (ext) {
573 case 2: /* near ind call */
574 case 3: /* far ind call */
575 ret = X86_BR_IND_CALL;
576 break;
577 case 4:
578 case 5:
579 ret = X86_BR_JMP;
580 break;
581 }
582 break;
583 default:
584 ret = X86_BR_NONE;
585 }
586 /*
587 * interrupts, traps, faults (and thus ring transition) may
588 * occur on any instructions. Thus, to classify them correctly,
589 * we need to first look at the from and to priv levels. If they
590 * are different and to is in the kernel, then it indicates
591 * a ring transition. If the from instruction is not a ring
592 * transition instr (syscall, systenter, int), then it means
593 * it was a irq, trap or fault.
594 *
595 * we have no way of detecting kernel to kernel faults.
596 */
597 if (from_plm == X86_BR_USER && to_plm == X86_BR_KERNEL
598 && ret != X86_BR_SYSCALL && ret != X86_BR_INT)
599 ret = X86_BR_IRQ;
600
601 /*
602 * branch priv level determined by target as
603 * is done by HW when LBR_SELECT is implemented
604 */
605 if (ret != X86_BR_NONE)
606 ret |= to_plm;
607
608 return ret;
609 }
610
611 /*
612 * implement actual branch filter based on user demand.
613 * Hardware may not exactly satisfy that request, thus
614 * we need to inspect opcodes. Mismatched branches are
615 * discarded. Therefore, the number of branches returned
616 * in PERF_SAMPLE_BRANCH_STACK sample may vary.
617 */
618 static void
intel_pmu_lbr_filter(struct cpu_hw_events * cpuc)619 intel_pmu_lbr_filter(struct cpu_hw_events *cpuc)
620 {
621 u64 from, to;
622 int br_sel = cpuc->br_sel;
623 int i, j, type;
624 bool compress = false;
625
626 /* if sampling all branches, then nothing to filter */
627 if ((br_sel & X86_BR_ALL) == X86_BR_ALL)
628 return;
629
630 for (i = 0; i < cpuc->lbr_stack.nr; i++) {
631
632 from = cpuc->lbr_entries[i].from;
633 to = cpuc->lbr_entries[i].to;
634
635 type = branch_type(from, to, cpuc->lbr_entries[i].abort);
636 if (type != X86_BR_NONE && (br_sel & X86_BR_ANYTX)) {
637 if (cpuc->lbr_entries[i].in_tx)
638 type |= X86_BR_IN_TX;
639 else
640 type |= X86_BR_NO_TX;
641 }
642
643 /* if type does not correspond, then discard */
644 if (type == X86_BR_NONE || (br_sel & type) != type) {
645 cpuc->lbr_entries[i].from = 0;
646 compress = true;
647 }
648 }
649
650 if (!compress)
651 return;
652
653 /* remove all entries with from=0 */
654 for (i = 0; i < cpuc->lbr_stack.nr; ) {
655 if (!cpuc->lbr_entries[i].from) {
656 j = i;
657 while (++j < cpuc->lbr_stack.nr)
658 cpuc->lbr_entries[j-1] = cpuc->lbr_entries[j];
659 cpuc->lbr_stack.nr--;
660 if (!cpuc->lbr_entries[i].from)
661 continue;
662 }
663 i++;
664 }
665 }
666
667 /*
668 * Map interface branch filters onto LBR filters
669 */
670 static const int nhm_lbr_sel_map[PERF_SAMPLE_BRANCH_MAX] = {
671 [PERF_SAMPLE_BRANCH_ANY] = LBR_ANY,
672 [PERF_SAMPLE_BRANCH_USER] = LBR_USER,
673 [PERF_SAMPLE_BRANCH_KERNEL] = LBR_KERNEL,
674 [PERF_SAMPLE_BRANCH_HV] = LBR_IGN,
675 [PERF_SAMPLE_BRANCH_ANY_RETURN] = LBR_RETURN | LBR_REL_JMP
676 | LBR_IND_JMP | LBR_FAR,
677 /*
678 * NHM/WSM erratum: must include REL_JMP+IND_JMP to get CALL branches
679 */
680 [PERF_SAMPLE_BRANCH_ANY_CALL] =
681 LBR_REL_CALL | LBR_IND_CALL | LBR_REL_JMP | LBR_IND_JMP | LBR_FAR,
682 /*
683 * NHM/WSM erratum: must include IND_JMP to capture IND_CALL
684 */
685 [PERF_SAMPLE_BRANCH_IND_CALL] = LBR_IND_CALL | LBR_IND_JMP,
686 [PERF_SAMPLE_BRANCH_COND] = LBR_JCC,
687 };
688
689 static const int snb_lbr_sel_map[PERF_SAMPLE_BRANCH_MAX] = {
690 [PERF_SAMPLE_BRANCH_ANY] = LBR_ANY,
691 [PERF_SAMPLE_BRANCH_USER] = LBR_USER,
692 [PERF_SAMPLE_BRANCH_KERNEL] = LBR_KERNEL,
693 [PERF_SAMPLE_BRANCH_HV] = LBR_IGN,
694 [PERF_SAMPLE_BRANCH_ANY_RETURN] = LBR_RETURN | LBR_FAR,
695 [PERF_SAMPLE_BRANCH_ANY_CALL] = LBR_REL_CALL | LBR_IND_CALL
696 | LBR_FAR,
697 [PERF_SAMPLE_BRANCH_IND_CALL] = LBR_IND_CALL,
698 [PERF_SAMPLE_BRANCH_COND] = LBR_JCC,
699 };
700
701 /* core */
intel_pmu_lbr_init_core(void)702 void __init intel_pmu_lbr_init_core(void)
703 {
704 x86_pmu.lbr_nr = 4;
705 x86_pmu.lbr_tos = MSR_LBR_TOS;
706 x86_pmu.lbr_from = MSR_LBR_CORE_FROM;
707 x86_pmu.lbr_to = MSR_LBR_CORE_TO;
708
709 /*
710 * SW branch filter usage:
711 * - compensate for lack of HW filter
712 */
713 pr_cont("4-deep LBR, ");
714 }
715
716 /* nehalem/westmere */
intel_pmu_lbr_init_nhm(void)717 void __init intel_pmu_lbr_init_nhm(void)
718 {
719 x86_pmu.lbr_nr = 16;
720 x86_pmu.lbr_tos = MSR_LBR_TOS;
721 x86_pmu.lbr_from = MSR_LBR_NHM_FROM;
722 x86_pmu.lbr_to = MSR_LBR_NHM_TO;
723
724 x86_pmu.lbr_sel_mask = LBR_SEL_MASK;
725 x86_pmu.lbr_sel_map = nhm_lbr_sel_map;
726
727 /*
728 * SW branch filter usage:
729 * - workaround LBR_SEL errata (see above)
730 * - support syscall, sysret capture.
731 * That requires LBR_FAR but that means far
732 * jmp need to be filtered out
733 */
734 pr_cont("16-deep LBR, ");
735 }
736
737 /* sandy bridge */
intel_pmu_lbr_init_snb(void)738 void __init intel_pmu_lbr_init_snb(void)
739 {
740 x86_pmu.lbr_nr = 16;
741 x86_pmu.lbr_tos = MSR_LBR_TOS;
742 x86_pmu.lbr_from = MSR_LBR_NHM_FROM;
743 x86_pmu.lbr_to = MSR_LBR_NHM_TO;
744
745 x86_pmu.lbr_sel_mask = LBR_SEL_MASK;
746 x86_pmu.lbr_sel_map = snb_lbr_sel_map;
747
748 /*
749 * SW branch filter usage:
750 * - support syscall, sysret capture.
751 * That requires LBR_FAR but that means far
752 * jmp need to be filtered out
753 */
754 pr_cont("16-deep LBR, ");
755 }
756
757 /* atom */
intel_pmu_lbr_init_atom(void)758 void __init intel_pmu_lbr_init_atom(void)
759 {
760 /*
761 * only models starting at stepping 10 seems
762 * to have an operational LBR which can freeze
763 * on PMU interrupt
764 */
765 if (boot_cpu_data.x86_model == 28
766 && boot_cpu_data.x86_mask < 10) {
767 pr_cont("LBR disabled due to erratum");
768 return;
769 }
770
771 x86_pmu.lbr_nr = 8;
772 x86_pmu.lbr_tos = MSR_LBR_TOS;
773 x86_pmu.lbr_from = MSR_LBR_CORE_FROM;
774 x86_pmu.lbr_to = MSR_LBR_CORE_TO;
775
776 /*
777 * SW branch filter usage:
778 * - compensate for lack of HW filter
779 */
780 pr_cont("8-deep LBR, ");
781 }
782