1 /*
2 * ahci.c - AHCI SATA support
3 *
4 * Maintained by: Tejun Heo <tj@kernel.org>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
32 *
33 */
34
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/blkdev.h>
39 #include <linux/delay.h>
40 #include <linux/interrupt.h>
41 #include <linux/dma-mapping.h>
42 #include <linux/device.h>
43 #include <linux/dmi.h>
44 #include <linux/gfp.h>
45 #include <scsi/scsi_host.h>
46 #include <scsi/scsi_cmnd.h>
47 #include <linux/libata.h>
48 #include "ahci.h"
49
50 #define DRV_NAME "ahci"
51 #define DRV_VERSION "3.0"
52
53 enum {
54 AHCI_PCI_BAR_STA2X11 = 0,
55 AHCI_PCI_BAR_ENMOTUS = 2,
56 AHCI_PCI_BAR_STANDARD = 5,
57 };
58
59 enum board_ids {
60 /* board IDs by feature in alphabetical order */
61 board_ahci,
62 board_ahci_ign_iferr,
63 board_ahci_nomsi,
64 board_ahci_noncq,
65 board_ahci_nosntf,
66 board_ahci_yes_fbs,
67
68 /* board IDs for specific chipsets in alphabetical order */
69 board_ahci_avn,
70 board_ahci_mcp65,
71 board_ahci_mcp77,
72 board_ahci_mcp89,
73 board_ahci_mv,
74 board_ahci_sb600,
75 board_ahci_sb700, /* for SB700 and SB800 */
76 board_ahci_vt8251,
77
78 /* aliases */
79 board_ahci_mcp_linux = board_ahci_mcp65,
80 board_ahci_mcp67 = board_ahci_mcp65,
81 board_ahci_mcp73 = board_ahci_mcp65,
82 board_ahci_mcp79 = board_ahci_mcp77,
83 };
84
85 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
86 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
87 unsigned long deadline);
88 static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class,
89 unsigned long deadline);
90 static void ahci_mcp89_apple_enable(struct pci_dev *pdev);
91 static bool is_mcp89_apple(struct pci_dev *pdev);
92 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
93 unsigned long deadline);
94 #ifdef CONFIG_PM
95 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
96 static int ahci_pci_device_resume(struct pci_dev *pdev);
97 #endif
98
99 static struct scsi_host_template ahci_sht = {
100 AHCI_SHT("ahci"),
101 };
102
103 static struct ata_port_operations ahci_vt8251_ops = {
104 .inherits = &ahci_ops,
105 .hardreset = ahci_vt8251_hardreset,
106 };
107
108 static struct ata_port_operations ahci_p5wdh_ops = {
109 .inherits = &ahci_ops,
110 .hardreset = ahci_p5wdh_hardreset,
111 };
112
113 static struct ata_port_operations ahci_avn_ops = {
114 .inherits = &ahci_ops,
115 .hardreset = ahci_avn_hardreset,
116 };
117
118 static const struct ata_port_info ahci_port_info[] = {
119 /* by features */
120 [board_ahci] = {
121 .flags = AHCI_FLAG_COMMON,
122 .pio_mask = ATA_PIO4,
123 .udma_mask = ATA_UDMA6,
124 .port_ops = &ahci_ops,
125 },
126 [board_ahci_ign_iferr] = {
127 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
128 .flags = AHCI_FLAG_COMMON,
129 .pio_mask = ATA_PIO4,
130 .udma_mask = ATA_UDMA6,
131 .port_ops = &ahci_ops,
132 },
133 [board_ahci_nomsi] = {
134 AHCI_HFLAGS (AHCI_HFLAG_NO_MSI),
135 .flags = AHCI_FLAG_COMMON,
136 .pio_mask = ATA_PIO4,
137 .udma_mask = ATA_UDMA6,
138 .port_ops = &ahci_ops,
139 },
140 [board_ahci_noncq] = {
141 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ),
142 .flags = AHCI_FLAG_COMMON,
143 .pio_mask = ATA_PIO4,
144 .udma_mask = ATA_UDMA6,
145 .port_ops = &ahci_ops,
146 },
147 [board_ahci_nosntf] = {
148 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF),
149 .flags = AHCI_FLAG_COMMON,
150 .pio_mask = ATA_PIO4,
151 .udma_mask = ATA_UDMA6,
152 .port_ops = &ahci_ops,
153 },
154 [board_ahci_yes_fbs] = {
155 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS),
156 .flags = AHCI_FLAG_COMMON,
157 .pio_mask = ATA_PIO4,
158 .udma_mask = ATA_UDMA6,
159 .port_ops = &ahci_ops,
160 },
161 /* by chipsets */
162 [board_ahci_avn] = {
163 .flags = AHCI_FLAG_COMMON,
164 .pio_mask = ATA_PIO4,
165 .udma_mask = ATA_UDMA6,
166 .port_ops = &ahci_avn_ops,
167 },
168 [board_ahci_mcp65] = {
169 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
170 AHCI_HFLAG_YES_NCQ),
171 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
172 .pio_mask = ATA_PIO4,
173 .udma_mask = ATA_UDMA6,
174 .port_ops = &ahci_ops,
175 },
176 [board_ahci_mcp77] = {
177 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
178 .flags = AHCI_FLAG_COMMON,
179 .pio_mask = ATA_PIO4,
180 .udma_mask = ATA_UDMA6,
181 .port_ops = &ahci_ops,
182 },
183 [board_ahci_mcp89] = {
184 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA),
185 .flags = AHCI_FLAG_COMMON,
186 .pio_mask = ATA_PIO4,
187 .udma_mask = ATA_UDMA6,
188 .port_ops = &ahci_ops,
189 },
190 [board_ahci_mv] = {
191 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
192 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
193 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
194 .pio_mask = ATA_PIO4,
195 .udma_mask = ATA_UDMA6,
196 .port_ops = &ahci_ops,
197 },
198 [board_ahci_sb600] = {
199 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
200 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
201 AHCI_HFLAG_32BIT_ONLY),
202 .flags = AHCI_FLAG_COMMON,
203 .pio_mask = ATA_PIO4,
204 .udma_mask = ATA_UDMA6,
205 .port_ops = &ahci_pmp_retry_srst_ops,
206 },
207 [board_ahci_sb700] = { /* for SB700 and SB800 */
208 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
209 .flags = AHCI_FLAG_COMMON,
210 .pio_mask = ATA_PIO4,
211 .udma_mask = ATA_UDMA6,
212 .port_ops = &ahci_pmp_retry_srst_ops,
213 },
214 [board_ahci_vt8251] = {
215 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
216 .flags = AHCI_FLAG_COMMON,
217 .pio_mask = ATA_PIO4,
218 .udma_mask = ATA_UDMA6,
219 .port_ops = &ahci_vt8251_ops,
220 },
221 };
222
223 static const struct pci_device_id ahci_pci_tbl[] = {
224 /* Intel */
225 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
226 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
227 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
228 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
229 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
230 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
231 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
232 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
233 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
234 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
235 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
236 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */
237 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
238 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
239 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
240 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
241 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
242 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
243 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
244 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
245 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
246 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
247 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
248 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
249 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
250 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
251 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
252 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
253 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
254 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
255 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
256 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
257 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
258 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
259 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
260 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
261 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci }, /* PCH AHCI */
262 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
263 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH RAID */
264 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
265 { PCI_VDEVICE(INTEL, 0x19b0), board_ahci }, /* DNV AHCI */
266 { PCI_VDEVICE(INTEL, 0x19b1), board_ahci }, /* DNV AHCI */
267 { PCI_VDEVICE(INTEL, 0x19b2), board_ahci }, /* DNV AHCI */
268 { PCI_VDEVICE(INTEL, 0x19b3), board_ahci }, /* DNV AHCI */
269 { PCI_VDEVICE(INTEL, 0x19b4), board_ahci }, /* DNV AHCI */
270 { PCI_VDEVICE(INTEL, 0x19b5), board_ahci }, /* DNV AHCI */
271 { PCI_VDEVICE(INTEL, 0x19b6), board_ahci }, /* DNV AHCI */
272 { PCI_VDEVICE(INTEL, 0x19b7), board_ahci }, /* DNV AHCI */
273 { PCI_VDEVICE(INTEL, 0x19bE), board_ahci }, /* DNV AHCI */
274 { PCI_VDEVICE(INTEL, 0x19bF), board_ahci }, /* DNV AHCI */
275 { PCI_VDEVICE(INTEL, 0x19c0), board_ahci }, /* DNV AHCI */
276 { PCI_VDEVICE(INTEL, 0x19c1), board_ahci }, /* DNV AHCI */
277 { PCI_VDEVICE(INTEL, 0x19c2), board_ahci }, /* DNV AHCI */
278 { PCI_VDEVICE(INTEL, 0x19c3), board_ahci }, /* DNV AHCI */
279 { PCI_VDEVICE(INTEL, 0x19c4), board_ahci }, /* DNV AHCI */
280 { PCI_VDEVICE(INTEL, 0x19c5), board_ahci }, /* DNV AHCI */
281 { PCI_VDEVICE(INTEL, 0x19c6), board_ahci }, /* DNV AHCI */
282 { PCI_VDEVICE(INTEL, 0x19c7), board_ahci }, /* DNV AHCI */
283 { PCI_VDEVICE(INTEL, 0x19cE), board_ahci }, /* DNV AHCI */
284 { PCI_VDEVICE(INTEL, 0x19cF), board_ahci }, /* DNV AHCI */
285 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
286 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci }, /* CPT AHCI */
287 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
288 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci }, /* CPT RAID */
289 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
290 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
291 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
292 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */
293 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */
294 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */
295 { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
296 { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */
297 { PCI_VDEVICE(INTEL, 0x1e03), board_ahci }, /* Panther Point AHCI */
298 { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */
299 { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */
300 { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */
301 { PCI_VDEVICE(INTEL, 0x1e07), board_ahci }, /* Panther Point RAID */
302 { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */
303 { PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */
304 { PCI_VDEVICE(INTEL, 0x8c03), board_ahci }, /* Lynx Point AHCI */
305 { PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */
306 { PCI_VDEVICE(INTEL, 0x8c05), board_ahci }, /* Lynx Point RAID */
307 { PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */
308 { PCI_VDEVICE(INTEL, 0x8c07), board_ahci }, /* Lynx Point RAID */
309 { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */
310 { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci }, /* Lynx Point RAID */
311 { PCI_VDEVICE(INTEL, 0x9c02), board_ahci }, /* Lynx Point-LP AHCI */
312 { PCI_VDEVICE(INTEL, 0x9c03), board_ahci }, /* Lynx Point-LP AHCI */
313 { PCI_VDEVICE(INTEL, 0x9c04), board_ahci }, /* Lynx Point-LP RAID */
314 { PCI_VDEVICE(INTEL, 0x9c05), board_ahci }, /* Lynx Point-LP RAID */
315 { PCI_VDEVICE(INTEL, 0x9c06), board_ahci }, /* Lynx Point-LP RAID */
316 { PCI_VDEVICE(INTEL, 0x9c07), board_ahci }, /* Lynx Point-LP RAID */
317 { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci }, /* Lynx Point-LP RAID */
318 { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci }, /* Lynx Point-LP RAID */
319 { PCI_VDEVICE(INTEL, 0x1f22), board_ahci }, /* Avoton AHCI */
320 { PCI_VDEVICE(INTEL, 0x1f23), board_ahci }, /* Avoton AHCI */
321 { PCI_VDEVICE(INTEL, 0x1f24), board_ahci }, /* Avoton RAID */
322 { PCI_VDEVICE(INTEL, 0x1f25), board_ahci }, /* Avoton RAID */
323 { PCI_VDEVICE(INTEL, 0x1f26), board_ahci }, /* Avoton RAID */
324 { PCI_VDEVICE(INTEL, 0x1f27), board_ahci }, /* Avoton RAID */
325 { PCI_VDEVICE(INTEL, 0x1f2e), board_ahci }, /* Avoton RAID */
326 { PCI_VDEVICE(INTEL, 0x1f2f), board_ahci }, /* Avoton RAID */
327 { PCI_VDEVICE(INTEL, 0x1f32), board_ahci_avn }, /* Avoton AHCI */
328 { PCI_VDEVICE(INTEL, 0x1f33), board_ahci_avn }, /* Avoton AHCI */
329 { PCI_VDEVICE(INTEL, 0x1f34), board_ahci_avn }, /* Avoton RAID */
330 { PCI_VDEVICE(INTEL, 0x1f35), board_ahci_avn }, /* Avoton RAID */
331 { PCI_VDEVICE(INTEL, 0x1f36), board_ahci_avn }, /* Avoton RAID */
332 { PCI_VDEVICE(INTEL, 0x1f37), board_ahci_avn }, /* Avoton RAID */
333 { PCI_VDEVICE(INTEL, 0x1f3e), board_ahci_avn }, /* Avoton RAID */
334 { PCI_VDEVICE(INTEL, 0x1f3f), board_ahci_avn }, /* Avoton RAID */
335 { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Wellsburg RAID */
336 { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Wellsburg RAID */
337 { PCI_VDEVICE(INTEL, 0x8d02), board_ahci }, /* Wellsburg AHCI */
338 { PCI_VDEVICE(INTEL, 0x8d04), board_ahci }, /* Wellsburg RAID */
339 { PCI_VDEVICE(INTEL, 0x8d06), board_ahci }, /* Wellsburg RAID */
340 { PCI_VDEVICE(INTEL, 0x8d0e), board_ahci }, /* Wellsburg RAID */
341 { PCI_VDEVICE(INTEL, 0x8d62), board_ahci }, /* Wellsburg AHCI */
342 { PCI_VDEVICE(INTEL, 0x8d64), board_ahci }, /* Wellsburg RAID */
343 { PCI_VDEVICE(INTEL, 0x8d66), board_ahci }, /* Wellsburg RAID */
344 { PCI_VDEVICE(INTEL, 0x8d6e), board_ahci }, /* Wellsburg RAID */
345 { PCI_VDEVICE(INTEL, 0x23a3), board_ahci }, /* Coleto Creek AHCI */
346 { PCI_VDEVICE(INTEL, 0x9c83), board_ahci }, /* Wildcat Point-LP AHCI */
347 { PCI_VDEVICE(INTEL, 0x9c85), board_ahci }, /* Wildcat Point-LP RAID */
348 { PCI_VDEVICE(INTEL, 0x9c87), board_ahci }, /* Wildcat Point-LP RAID */
349 { PCI_VDEVICE(INTEL, 0x9c8f), board_ahci }, /* Wildcat Point-LP RAID */
350 { PCI_VDEVICE(INTEL, 0x8c82), board_ahci }, /* 9 Series AHCI */
351 { PCI_VDEVICE(INTEL, 0x8c83), board_ahci }, /* 9 Series AHCI */
352 { PCI_VDEVICE(INTEL, 0x8c84), board_ahci }, /* 9 Series RAID */
353 { PCI_VDEVICE(INTEL, 0x8c85), board_ahci }, /* 9 Series RAID */
354 { PCI_VDEVICE(INTEL, 0x8c86), board_ahci }, /* 9 Series RAID */
355 { PCI_VDEVICE(INTEL, 0x8c87), board_ahci }, /* 9 Series RAID */
356 { PCI_VDEVICE(INTEL, 0x8c8e), board_ahci }, /* 9 Series RAID */
357 { PCI_VDEVICE(INTEL, 0x8c8f), board_ahci }, /* 9 Series RAID */
358 { PCI_VDEVICE(INTEL, 0x9d03), board_ahci }, /* Sunrise Point-LP AHCI */
359 { PCI_VDEVICE(INTEL, 0x9d05), board_ahci }, /* Sunrise Point-LP RAID */
360 { PCI_VDEVICE(INTEL, 0x9d07), board_ahci }, /* Sunrise Point-LP RAID */
361 { PCI_VDEVICE(INTEL, 0xa103), board_ahci }, /* Sunrise Point-H AHCI */
362 { PCI_VDEVICE(INTEL, 0xa103), board_ahci }, /* Sunrise Point-H RAID */
363 { PCI_VDEVICE(INTEL, 0xa105), board_ahci }, /* Sunrise Point-H RAID */
364 { PCI_VDEVICE(INTEL, 0xa107), board_ahci }, /* Sunrise Point-H RAID */
365 { PCI_VDEVICE(INTEL, 0xa10f), board_ahci }, /* Sunrise Point-H RAID */
366 { PCI_VDEVICE(INTEL, 0x2822), board_ahci }, /* Lewisburg RAID*/
367 { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Lewisburg AHCI*/
368 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* Lewisburg RAID*/
369 { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Lewisburg RAID*/
370 { PCI_VDEVICE(INTEL, 0xa182), board_ahci }, /* Lewisburg AHCI*/
371 { PCI_VDEVICE(INTEL, 0xa184), board_ahci }, /* Lewisburg RAID*/
372 { PCI_VDEVICE(INTEL, 0xa186), board_ahci }, /* Lewisburg RAID*/
373 { PCI_VDEVICE(INTEL, 0xa18e), board_ahci }, /* Lewisburg RAID*/
374 { PCI_VDEVICE(INTEL, 0xa1d2), board_ahci }, /* Lewisburg RAID*/
375 { PCI_VDEVICE(INTEL, 0xa1d6), board_ahci }, /* Lewisburg RAID*/
376 { PCI_VDEVICE(INTEL, 0xa202), board_ahci }, /* Lewisburg AHCI*/
377 { PCI_VDEVICE(INTEL, 0xa204), board_ahci }, /* Lewisburg RAID*/
378 { PCI_VDEVICE(INTEL, 0xa206), board_ahci }, /* Lewisburg RAID*/
379 { PCI_VDEVICE(INTEL, 0xa20e), board_ahci }, /* Lewisburg RAID*/
380 { PCI_VDEVICE(INTEL, 0xa252), board_ahci }, /* Lewisburg RAID*/
381 { PCI_VDEVICE(INTEL, 0xa256), board_ahci }, /* Lewisburg RAID*/
382
383 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
384 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
385 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
386 /* JMicron 362B and 362C have an AHCI function with IDE class code */
387 { PCI_VDEVICE(JMICRON, 0x2362), board_ahci_ign_iferr },
388 { PCI_VDEVICE(JMICRON, 0x236f), board_ahci_ign_iferr },
389
390 /* ATI */
391 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
392 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
393 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
394 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
395 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
396 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
397 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
398
399 /* AMD */
400 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
401 { PCI_VDEVICE(AMD, 0x7900), board_ahci }, /* AMD CZ */
402 /* AMD is using RAID class only for ahci controllers */
403 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
404 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
405
406 /* VIA */
407 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
408 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
409
410 /* NVIDIA */
411 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
412 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
413 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
414 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
415 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
416 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
417 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
418 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
419 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */
420 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */
421 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */
422 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */
423 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */
424 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */
425 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */
426 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */
427 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */
428 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */
429 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */
430 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */
431 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */
432 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */
433 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */
434 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */
435 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */
436 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */
437 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */
438 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */
439 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */
440 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */
441 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */
442 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */
443 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */
444 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */
445 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */
446 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */
447 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */
448 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */
449 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */
450 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */
451 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */
452 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */
453 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */
454 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */
455 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */
456 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */
457 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */
458 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */
459 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */
460 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */
461 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */
462 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */
463 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */
464 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */
465 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */
466 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */
467 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */
468 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */
469 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */
470 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */
471 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */
472 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */
473 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */
474 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */
475 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */
476 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */
477 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */
478 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */
479 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */
480 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */
481 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */
482 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */
483 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */
484 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */
485 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */
486 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */
487 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */
488 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */
489 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */
490 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */
491 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */
492 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */
493 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */
494 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */
495
496 /* SiS */
497 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
498 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
499 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
500
501 /* ST Microelectronics */
502 { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci }, /* ST ConneXt */
503
504 /* Marvell */
505 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
506 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
507 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9123),
508 .class = PCI_CLASS_STORAGE_SATA_AHCI,
509 .class_mask = 0xffffff,
510 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */
511 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9125),
512 .driver_data = board_ahci_yes_fbs }, /* 88se9125 */
513 { PCI_DEVICE_SUB(PCI_VENDOR_ID_MARVELL_EXT, 0x9178,
514 PCI_VENDOR_ID_MARVELL_EXT, 0x9170),
515 .driver_data = board_ahci_yes_fbs }, /* 88se9170 */
516 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x917a),
517 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
518 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9172),
519 .driver_data = board_ahci_yes_fbs }, /* 88se9182 */
520 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9182),
521 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
522 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9192),
523 .driver_data = board_ahci_yes_fbs }, /* 88se9172 on some Gigabyte */
524 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0),
525 .driver_data = board_ahci_yes_fbs },
526 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a3),
527 .driver_data = board_ahci_yes_fbs },
528 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9230),
529 .driver_data = board_ahci_yes_fbs },
530 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0642),
531 .driver_data = board_ahci_yes_fbs },
532
533 /* Promise */
534 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
535 { PCI_VDEVICE(PROMISE, 0x3781), board_ahci }, /* FastTrak TX8660 ahci-mode */
536
537 /* Asmedia */
538 { PCI_VDEVICE(ASMEDIA, 0x0601), board_ahci }, /* ASM1060 */
539 { PCI_VDEVICE(ASMEDIA, 0x0602), board_ahci }, /* ASM1060 */
540 { PCI_VDEVICE(ASMEDIA, 0x0611), board_ahci }, /* ASM1061 */
541 { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci }, /* ASM1062 */
542
543 /*
544 * Samsung SSDs found on some macbooks. NCQ times out if MSI is
545 * enabled. https://bugzilla.kernel.org/show_bug.cgi?id=60731
546 */
547 { PCI_VDEVICE(SAMSUNG, 0x1600), board_ahci_nomsi },
548 { PCI_VDEVICE(SAMSUNG, 0xa800), board_ahci_nomsi },
549
550 /* Enmotus */
551 { PCI_DEVICE(0x1c44, 0x8000), board_ahci },
552
553 /* Generic, PCI class code for AHCI */
554 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
555 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
556
557 { } /* terminate list */
558 };
559
560
561 static struct pci_driver ahci_pci_driver = {
562 .name = DRV_NAME,
563 .id_table = ahci_pci_tbl,
564 .probe = ahci_init_one,
565 .remove = ata_pci_remove_one,
566 #ifdef CONFIG_PM
567 .suspend = ahci_pci_device_suspend,
568 .resume = ahci_pci_device_resume,
569 #endif
570 };
571
572 #if defined(CONFIG_PATA_MARVELL) || defined(CONFIG_PATA_MARVELL_MODULE)
573 static int marvell_enable;
574 #else
575 static int marvell_enable = 1;
576 #endif
577 module_param(marvell_enable, int, 0644);
578 MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
579
580
ahci_pci_save_initial_config(struct pci_dev * pdev,struct ahci_host_priv * hpriv)581 static void ahci_pci_save_initial_config(struct pci_dev *pdev,
582 struct ahci_host_priv *hpriv)
583 {
584 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
585 dev_info(&pdev->dev, "JMB361 has only one port\n");
586 hpriv->force_port_map = 1;
587 }
588
589 /*
590 * Temporary Marvell 6145 hack: PATA port presence
591 * is asserted through the standard AHCI port
592 * presence register, as bit 4 (counting from 0)
593 */
594 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
595 if (pdev->device == 0x6121)
596 hpriv->mask_port_map = 0x3;
597 else
598 hpriv->mask_port_map = 0xf;
599 dev_info(&pdev->dev,
600 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
601 }
602
603 ahci_save_initial_config(&pdev->dev, hpriv);
604 }
605
ahci_pci_reset_controller(struct ata_host * host)606 static int ahci_pci_reset_controller(struct ata_host *host)
607 {
608 struct pci_dev *pdev = to_pci_dev(host->dev);
609
610 ahci_reset_controller(host);
611
612 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
613 struct ahci_host_priv *hpriv = host->private_data;
614 u16 tmp16;
615
616 /* configure PCS */
617 pci_read_config_word(pdev, 0x92, &tmp16);
618 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
619 tmp16 |= hpriv->port_map;
620 pci_write_config_word(pdev, 0x92, tmp16);
621 }
622 }
623
624 return 0;
625 }
626
ahci_pci_init_controller(struct ata_host * host)627 static void ahci_pci_init_controller(struct ata_host *host)
628 {
629 struct ahci_host_priv *hpriv = host->private_data;
630 struct pci_dev *pdev = to_pci_dev(host->dev);
631 void __iomem *port_mmio;
632 u32 tmp;
633 int mv;
634
635 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
636 if (pdev->device == 0x6121)
637 mv = 2;
638 else
639 mv = 4;
640 port_mmio = __ahci_port_base(host, mv);
641
642 writel(0, port_mmio + PORT_IRQ_MASK);
643
644 /* clear port IRQ */
645 tmp = readl(port_mmio + PORT_IRQ_STAT);
646 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
647 if (tmp)
648 writel(tmp, port_mmio + PORT_IRQ_STAT);
649 }
650
651 ahci_init_controller(host);
652 }
653
ahci_vt8251_hardreset(struct ata_link * link,unsigned int * class,unsigned long deadline)654 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
655 unsigned long deadline)
656 {
657 struct ata_port *ap = link->ap;
658 struct ahci_host_priv *hpriv = ap->host->private_data;
659 bool online;
660 int rc;
661
662 DPRINTK("ENTER\n");
663
664 ahci_stop_engine(ap);
665
666 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
667 deadline, &online, NULL);
668
669 hpriv->start_engine(ap);
670
671 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
672
673 /* vt8251 doesn't clear BSY on signature FIS reception,
674 * request follow-up softreset.
675 */
676 return online ? -EAGAIN : rc;
677 }
678
ahci_p5wdh_hardreset(struct ata_link * link,unsigned int * class,unsigned long deadline)679 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
680 unsigned long deadline)
681 {
682 struct ata_port *ap = link->ap;
683 struct ahci_port_priv *pp = ap->private_data;
684 struct ahci_host_priv *hpriv = ap->host->private_data;
685 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
686 struct ata_taskfile tf;
687 bool online;
688 int rc;
689
690 ahci_stop_engine(ap);
691
692 /* clear D2H reception area to properly wait for D2H FIS */
693 ata_tf_init(link->device, &tf);
694 tf.command = ATA_BUSY;
695 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
696
697 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
698 deadline, &online, NULL);
699
700 hpriv->start_engine(ap);
701
702 /* The pseudo configuration device on SIMG4726 attached to
703 * ASUS P5W-DH Deluxe doesn't send signature FIS after
704 * hardreset if no device is attached to the first downstream
705 * port && the pseudo device locks up on SRST w/ PMP==0. To
706 * work around this, wait for !BSY only briefly. If BSY isn't
707 * cleared, perform CLO and proceed to IDENTIFY (achieved by
708 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
709 *
710 * Wait for two seconds. Devices attached to downstream port
711 * which can't process the following IDENTIFY after this will
712 * have to be reset again. For most cases, this should
713 * suffice while making probing snappish enough.
714 */
715 if (online) {
716 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
717 ahci_check_ready);
718 if (rc)
719 ahci_kick_engine(ap);
720 }
721 return rc;
722 }
723
724 /*
725 * ahci_avn_hardreset - attempt more aggressive recovery of Avoton ports.
726 *
727 * It has been observed with some SSDs that the timing of events in the
728 * link synchronization phase can leave the port in a state that can not
729 * be recovered by a SATA-hard-reset alone. The failing signature is
730 * SStatus.DET stuck at 1 ("Device presence detected but Phy
731 * communication not established"). It was found that unloading and
732 * reloading the driver when this problem occurs allows the drive
733 * connection to be recovered (DET advanced to 0x3). The critical
734 * component of reloading the driver is that the port state machines are
735 * reset by bouncing "port enable" in the AHCI PCS configuration
736 * register. So, reproduce that effect by bouncing a port whenever we
737 * see DET==1 after a reset.
738 */
ahci_avn_hardreset(struct ata_link * link,unsigned int * class,unsigned long deadline)739 static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class,
740 unsigned long deadline)
741 {
742 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
743 struct ata_port *ap = link->ap;
744 struct ahci_port_priv *pp = ap->private_data;
745 struct ahci_host_priv *hpriv = ap->host->private_data;
746 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
747 unsigned long tmo = deadline - jiffies;
748 struct ata_taskfile tf;
749 bool online;
750 int rc, i;
751
752 DPRINTK("ENTER\n");
753
754 ahci_stop_engine(ap);
755
756 for (i = 0; i < 2; i++) {
757 u16 val;
758 u32 sstatus;
759 int port = ap->port_no;
760 struct ata_host *host = ap->host;
761 struct pci_dev *pdev = to_pci_dev(host->dev);
762
763 /* clear D2H reception area to properly wait for D2H FIS */
764 ata_tf_init(link->device, &tf);
765 tf.command = ATA_BUSY;
766 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
767
768 rc = sata_link_hardreset(link, timing, deadline, &online,
769 ahci_check_ready);
770
771 if (sata_scr_read(link, SCR_STATUS, &sstatus) != 0 ||
772 (sstatus & 0xf) != 1)
773 break;
774
775 ata_link_printk(link, KERN_INFO, "avn bounce port%d\n",
776 port);
777
778 pci_read_config_word(pdev, 0x92, &val);
779 val &= ~(1 << port);
780 pci_write_config_word(pdev, 0x92, val);
781 ata_msleep(ap, 1000);
782 val |= 1 << port;
783 pci_write_config_word(pdev, 0x92, val);
784 deadline += tmo;
785 }
786
787 hpriv->start_engine(ap);
788
789 if (online)
790 *class = ahci_dev_classify(ap);
791
792 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
793 return rc;
794 }
795
796
797 #ifdef CONFIG_PM
ahci_pci_device_suspend(struct pci_dev * pdev,pm_message_t mesg)798 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
799 {
800 struct ata_host *host = pci_get_drvdata(pdev);
801 struct ahci_host_priv *hpriv = host->private_data;
802 void __iomem *mmio = hpriv->mmio;
803 u32 ctl;
804
805 if (mesg.event & PM_EVENT_SUSPEND &&
806 hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
807 dev_err(&pdev->dev,
808 "BIOS update required for suspend/resume\n");
809 return -EIO;
810 }
811
812 if (mesg.event & PM_EVENT_SLEEP) {
813 /* AHCI spec rev1.1 section 8.3.3:
814 * Software must disable interrupts prior to requesting a
815 * transition of the HBA to D3 state.
816 */
817 ctl = readl(mmio + HOST_CTL);
818 ctl &= ~HOST_IRQ_EN;
819 writel(ctl, mmio + HOST_CTL);
820 readl(mmio + HOST_CTL); /* flush */
821 }
822
823 return ata_pci_device_suspend(pdev, mesg);
824 }
825
ahci_pci_device_resume(struct pci_dev * pdev)826 static int ahci_pci_device_resume(struct pci_dev *pdev)
827 {
828 struct ata_host *host = pci_get_drvdata(pdev);
829 int rc;
830
831 rc = ata_pci_device_do_resume(pdev);
832 if (rc)
833 return rc;
834
835 /* Apple BIOS helpfully mangles the registers on resume */
836 if (is_mcp89_apple(pdev))
837 ahci_mcp89_apple_enable(pdev);
838
839 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
840 rc = ahci_pci_reset_controller(host);
841 if (rc)
842 return rc;
843
844 ahci_pci_init_controller(host);
845 }
846
847 ata_host_resume(host);
848
849 return 0;
850 }
851 #endif
852
ahci_configure_dma_masks(struct pci_dev * pdev,int using_dac)853 static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
854 {
855 int rc;
856
857 /*
858 * If the device fixup already set the dma_mask to some non-standard
859 * value, don't extend it here. This happens on STA2X11, for example.
860 */
861 if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32))
862 return 0;
863
864 if (using_dac &&
865 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
866 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
867 if (rc) {
868 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
869 if (rc) {
870 dev_err(&pdev->dev,
871 "64-bit DMA enable failed\n");
872 return rc;
873 }
874 }
875 } else {
876 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
877 if (rc) {
878 dev_err(&pdev->dev, "32-bit DMA enable failed\n");
879 return rc;
880 }
881 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
882 if (rc) {
883 dev_err(&pdev->dev,
884 "32-bit consistent DMA enable failed\n");
885 return rc;
886 }
887 }
888 return 0;
889 }
890
ahci_pci_print_info(struct ata_host * host)891 static void ahci_pci_print_info(struct ata_host *host)
892 {
893 struct pci_dev *pdev = to_pci_dev(host->dev);
894 u16 cc;
895 const char *scc_s;
896
897 pci_read_config_word(pdev, 0x0a, &cc);
898 if (cc == PCI_CLASS_STORAGE_IDE)
899 scc_s = "IDE";
900 else if (cc == PCI_CLASS_STORAGE_SATA)
901 scc_s = "SATA";
902 else if (cc == PCI_CLASS_STORAGE_RAID)
903 scc_s = "RAID";
904 else
905 scc_s = "unknown";
906
907 ahci_print_info(host, scc_s);
908 }
909
910 /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
911 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
912 * support PMP and the 4726 either directly exports the device
913 * attached to the first downstream port or acts as a hardware storage
914 * controller and emulate a single ATA device (can be RAID 0/1 or some
915 * other configuration).
916 *
917 * When there's no device attached to the first downstream port of the
918 * 4726, "Config Disk" appears, which is a pseudo ATA device to
919 * configure the 4726. However, ATA emulation of the device is very
920 * lame. It doesn't send signature D2H Reg FIS after the initial
921 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
922 *
923 * The following function works around the problem by always using
924 * hardreset on the port and not depending on receiving signature FIS
925 * afterward. If signature FIS isn't received soon, ATA class is
926 * assumed without follow-up softreset.
927 */
ahci_p5wdh_workaround(struct ata_host * host)928 static void ahci_p5wdh_workaround(struct ata_host *host)
929 {
930 static const struct dmi_system_id sysids[] = {
931 {
932 .ident = "P5W DH Deluxe",
933 .matches = {
934 DMI_MATCH(DMI_SYS_VENDOR,
935 "ASUSTEK COMPUTER INC"),
936 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
937 },
938 },
939 { }
940 };
941 struct pci_dev *pdev = to_pci_dev(host->dev);
942
943 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
944 dmi_check_system(sysids)) {
945 struct ata_port *ap = host->ports[1];
946
947 dev_info(&pdev->dev,
948 "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n");
949
950 ap->ops = &ahci_p5wdh_ops;
951 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
952 }
953 }
954
955 /*
956 * Macbook7,1 firmware forcibly disables MCP89 AHCI and changes PCI ID when
957 * booting in BIOS compatibility mode. We restore the registers but not ID.
958 */
ahci_mcp89_apple_enable(struct pci_dev * pdev)959 static void ahci_mcp89_apple_enable(struct pci_dev *pdev)
960 {
961 u32 val;
962
963 printk(KERN_INFO "ahci: enabling MCP89 AHCI mode\n");
964
965 pci_read_config_dword(pdev, 0xf8, &val);
966 val |= 1 << 0x1b;
967 /* the following changes the device ID, but appears not to affect function */
968 /* val = (val & ~0xf0000000) | 0x80000000; */
969 pci_write_config_dword(pdev, 0xf8, val);
970
971 pci_read_config_dword(pdev, 0x54c, &val);
972 val |= 1 << 0xc;
973 pci_write_config_dword(pdev, 0x54c, val);
974
975 pci_read_config_dword(pdev, 0x4a4, &val);
976 val &= 0xff;
977 val |= 0x01060100;
978 pci_write_config_dword(pdev, 0x4a4, val);
979
980 pci_read_config_dword(pdev, 0x54c, &val);
981 val &= ~(1 << 0xc);
982 pci_write_config_dword(pdev, 0x54c, val);
983
984 pci_read_config_dword(pdev, 0xf8, &val);
985 val &= ~(1 << 0x1b);
986 pci_write_config_dword(pdev, 0xf8, val);
987 }
988
is_mcp89_apple(struct pci_dev * pdev)989 static bool is_mcp89_apple(struct pci_dev *pdev)
990 {
991 return pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
992 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
993 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
994 pdev->subsystem_device == 0xcb89;
995 }
996
997 /* only some SB600 ahci controllers can do 64bit DMA */
ahci_sb600_enable_64bit(struct pci_dev * pdev)998 static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
999 {
1000 static const struct dmi_system_id sysids[] = {
1001 /*
1002 * The oldest version known to be broken is 0901 and
1003 * working is 1501 which was released on 2007-10-26.
1004 * Enable 64bit DMA on 1501 and anything newer.
1005 *
1006 * Please read bko#9412 for more info.
1007 */
1008 {
1009 .ident = "ASUS M2A-VM",
1010 .matches = {
1011 DMI_MATCH(DMI_BOARD_VENDOR,
1012 "ASUSTeK Computer INC."),
1013 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
1014 },
1015 .driver_data = "20071026", /* yyyymmdd */
1016 },
1017 /*
1018 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
1019 * support 64bit DMA.
1020 *
1021 * BIOS versions earlier than 1.5 had the Manufacturer DMI
1022 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
1023 * This spelling mistake was fixed in BIOS version 1.5, so
1024 * 1.5 and later have the Manufacturer as
1025 * "MICRO-STAR INTERNATIONAL CO.,LTD".
1026 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
1027 *
1028 * BIOS versions earlier than 1.9 had a Board Product Name
1029 * DMI field of "MS-7376". This was changed to be
1030 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
1031 * match on DMI_BOARD_NAME of "MS-7376".
1032 */
1033 {
1034 .ident = "MSI K9A2 Platinum",
1035 .matches = {
1036 DMI_MATCH(DMI_BOARD_VENDOR,
1037 "MICRO-STAR INTER"),
1038 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
1039 },
1040 },
1041 /*
1042 * All BIOS versions for the MSI K9AGM2 (MS-7327) support
1043 * 64bit DMA.
1044 *
1045 * This board also had the typo mentioned above in the
1046 * Manufacturer DMI field (fixed in BIOS version 1.5), so
1047 * match on DMI_BOARD_VENDOR of "MICRO-STAR INTER" again.
1048 */
1049 {
1050 .ident = "MSI K9AGM2",
1051 .matches = {
1052 DMI_MATCH(DMI_BOARD_VENDOR,
1053 "MICRO-STAR INTER"),
1054 DMI_MATCH(DMI_BOARD_NAME, "MS-7327"),
1055 },
1056 },
1057 /*
1058 * All BIOS versions for the Asus M3A support 64bit DMA.
1059 * (all release versions from 0301 to 1206 were tested)
1060 */
1061 {
1062 .ident = "ASUS M3A",
1063 .matches = {
1064 DMI_MATCH(DMI_BOARD_VENDOR,
1065 "ASUSTeK Computer INC."),
1066 DMI_MATCH(DMI_BOARD_NAME, "M3A"),
1067 },
1068 },
1069 { }
1070 };
1071 const struct dmi_system_id *match;
1072 int year, month, date;
1073 char buf[9];
1074
1075 match = dmi_first_match(sysids);
1076 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
1077 !match)
1078 return false;
1079
1080 if (!match->driver_data)
1081 goto enable_64bit;
1082
1083 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1084 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1085
1086 if (strcmp(buf, match->driver_data) >= 0)
1087 goto enable_64bit;
1088 else {
1089 dev_warn(&pdev->dev,
1090 "%s: BIOS too old, forcing 32bit DMA, update BIOS\n",
1091 match->ident);
1092 return false;
1093 }
1094
1095 enable_64bit:
1096 dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident);
1097 return true;
1098 }
1099
ahci_broken_system_poweroff(struct pci_dev * pdev)1100 static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
1101 {
1102 static const struct dmi_system_id broken_systems[] = {
1103 {
1104 .ident = "HP Compaq nx6310",
1105 .matches = {
1106 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1107 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
1108 },
1109 /* PCI slot number of the controller */
1110 .driver_data = (void *)0x1FUL,
1111 },
1112 {
1113 .ident = "HP Compaq 6720s",
1114 .matches = {
1115 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1116 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
1117 },
1118 /* PCI slot number of the controller */
1119 .driver_data = (void *)0x1FUL,
1120 },
1121
1122 { } /* terminate list */
1123 };
1124 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
1125
1126 if (dmi) {
1127 unsigned long slot = (unsigned long)dmi->driver_data;
1128 /* apply the quirk only to on-board controllers */
1129 return slot == PCI_SLOT(pdev->devfn);
1130 }
1131
1132 return false;
1133 }
1134
ahci_broken_suspend(struct pci_dev * pdev)1135 static bool ahci_broken_suspend(struct pci_dev *pdev)
1136 {
1137 static const struct dmi_system_id sysids[] = {
1138 /*
1139 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
1140 * to the harddisk doesn't become online after
1141 * resuming from STR. Warn and fail suspend.
1142 *
1143 * http://bugzilla.kernel.org/show_bug.cgi?id=12276
1144 *
1145 * Use dates instead of versions to match as HP is
1146 * apparently recycling both product and version
1147 * strings.
1148 *
1149 * http://bugzilla.kernel.org/show_bug.cgi?id=15462
1150 */
1151 {
1152 .ident = "dv4",
1153 .matches = {
1154 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1155 DMI_MATCH(DMI_PRODUCT_NAME,
1156 "HP Pavilion dv4 Notebook PC"),
1157 },
1158 .driver_data = "20090105", /* F.30 */
1159 },
1160 {
1161 .ident = "dv5",
1162 .matches = {
1163 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1164 DMI_MATCH(DMI_PRODUCT_NAME,
1165 "HP Pavilion dv5 Notebook PC"),
1166 },
1167 .driver_data = "20090506", /* F.16 */
1168 },
1169 {
1170 .ident = "dv6",
1171 .matches = {
1172 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1173 DMI_MATCH(DMI_PRODUCT_NAME,
1174 "HP Pavilion dv6 Notebook PC"),
1175 },
1176 .driver_data = "20090423", /* F.21 */
1177 },
1178 {
1179 .ident = "HDX18",
1180 .matches = {
1181 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1182 DMI_MATCH(DMI_PRODUCT_NAME,
1183 "HP HDX18 Notebook PC"),
1184 },
1185 .driver_data = "20090430", /* F.23 */
1186 },
1187 /*
1188 * Acer eMachines G725 has the same problem. BIOS
1189 * V1.03 is known to be broken. V3.04 is known to
1190 * work. Between, there are V1.06, V2.06 and V3.03
1191 * that we don't have much idea about. For now,
1192 * blacklist anything older than V3.04.
1193 *
1194 * http://bugzilla.kernel.org/show_bug.cgi?id=15104
1195 */
1196 {
1197 .ident = "G725",
1198 .matches = {
1199 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
1200 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
1201 },
1202 .driver_data = "20091216", /* V3.04 */
1203 },
1204 { } /* terminate list */
1205 };
1206 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1207 int year, month, date;
1208 char buf[9];
1209
1210 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
1211 return false;
1212
1213 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1214 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1215
1216 return strcmp(buf, dmi->driver_data) < 0;
1217 }
1218
ahci_broken_online(struct pci_dev * pdev)1219 static bool ahci_broken_online(struct pci_dev *pdev)
1220 {
1221 #define ENCODE_BUSDEVFN(bus, slot, func) \
1222 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
1223 static const struct dmi_system_id sysids[] = {
1224 /*
1225 * There are several gigabyte boards which use
1226 * SIMG5723s configured as hardware RAID. Certain
1227 * 5723 firmware revisions shipped there keep the link
1228 * online but fail to answer properly to SRST or
1229 * IDENTIFY when no device is attached downstream
1230 * causing libata to retry quite a few times leading
1231 * to excessive detection delay.
1232 *
1233 * As these firmwares respond to the second reset try
1234 * with invalid device signature, considering unknown
1235 * sig as offline works around the problem acceptably.
1236 */
1237 {
1238 .ident = "EP45-DQ6",
1239 .matches = {
1240 DMI_MATCH(DMI_BOARD_VENDOR,
1241 "Gigabyte Technology Co., Ltd."),
1242 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
1243 },
1244 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
1245 },
1246 {
1247 .ident = "EP45-DS5",
1248 .matches = {
1249 DMI_MATCH(DMI_BOARD_VENDOR,
1250 "Gigabyte Technology Co., Ltd."),
1251 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
1252 },
1253 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
1254 },
1255 { } /* terminate list */
1256 };
1257 #undef ENCODE_BUSDEVFN
1258 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1259 unsigned int val;
1260
1261 if (!dmi)
1262 return false;
1263
1264 val = (unsigned long)dmi->driver_data;
1265
1266 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
1267 }
1268
ahci_broken_devslp(struct pci_dev * pdev)1269 static bool ahci_broken_devslp(struct pci_dev *pdev)
1270 {
1271 /* device with broken DEVSLP but still showing SDS capability */
1272 static const struct pci_device_id ids[] = {
1273 { PCI_VDEVICE(INTEL, 0x0f23)}, /* Valleyview SoC */
1274 {}
1275 };
1276
1277 return pci_match_id(ids, pdev);
1278 }
1279
1280 #ifdef CONFIG_ATA_ACPI
ahci_gtf_filter_workaround(struct ata_host * host)1281 static void ahci_gtf_filter_workaround(struct ata_host *host)
1282 {
1283 static const struct dmi_system_id sysids[] = {
1284 /*
1285 * Aspire 3810T issues a bunch of SATA enable commands
1286 * via _GTF including an invalid one and one which is
1287 * rejected by the device. Among the successful ones
1288 * is FPDMA non-zero offset enable which when enabled
1289 * only on the drive side leads to NCQ command
1290 * failures. Filter it out.
1291 */
1292 {
1293 .ident = "Aspire 3810T",
1294 .matches = {
1295 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1296 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
1297 },
1298 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
1299 },
1300 { }
1301 };
1302 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1303 unsigned int filter;
1304 int i;
1305
1306 if (!dmi)
1307 return;
1308
1309 filter = (unsigned long)dmi->driver_data;
1310 dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n",
1311 filter, dmi->ident);
1312
1313 for (i = 0; i < host->n_ports; i++) {
1314 struct ata_port *ap = host->ports[i];
1315 struct ata_link *link;
1316 struct ata_device *dev;
1317
1318 ata_for_each_link(link, ap, EDGE)
1319 ata_for_each_dev(dev, link, ALL)
1320 dev->gtf_filter |= filter;
1321 }
1322 }
1323 #else
ahci_gtf_filter_workaround(struct ata_host * host)1324 static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1325 {}
1326 #endif
1327
ahci_init_interrupts(struct pci_dev * pdev,unsigned int n_ports,struct ahci_host_priv * hpriv)1328 static int ahci_init_interrupts(struct pci_dev *pdev, unsigned int n_ports,
1329 struct ahci_host_priv *hpriv)
1330 {
1331 int rc, nvec;
1332
1333 if (hpriv->flags & AHCI_HFLAG_NO_MSI)
1334 goto intx;
1335
1336 nvec = pci_msi_vec_count(pdev);
1337 if (nvec < 0)
1338 goto intx;
1339
1340 /*
1341 * If number of MSIs is less than number of ports then Sharing Last
1342 * Message mode could be enforced. In this case assume that advantage
1343 * of multipe MSIs is negated and use single MSI mode instead.
1344 */
1345 if (nvec < n_ports)
1346 goto single_msi;
1347
1348 rc = pci_enable_msi_exact(pdev, nvec);
1349 if (rc == -ENOSPC)
1350 goto single_msi;
1351 else if (rc < 0)
1352 goto intx;
1353
1354 /* fallback to single MSI mode if the controller enforced MRSM mode */
1355 if (readl(hpriv->mmio + HOST_CTL) & HOST_MRSM) {
1356 pci_disable_msi(pdev);
1357 printk(KERN_INFO "ahci: MRSM is on, fallback to single MSI\n");
1358 goto single_msi;
1359 }
1360
1361 if (nvec > 1)
1362 hpriv->flags |= AHCI_HFLAG_MULTI_MSI;
1363
1364 return nvec;
1365
1366 single_msi:
1367 if (pci_enable_msi(pdev))
1368 goto intx;
1369 return 1;
1370
1371 intx:
1372 pci_intx(pdev, 1);
1373 return 0;
1374 }
1375
ahci_init_one(struct pci_dev * pdev,const struct pci_device_id * ent)1376 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1377 {
1378 unsigned int board_id = ent->driver_data;
1379 struct ata_port_info pi = ahci_port_info[board_id];
1380 const struct ata_port_info *ppi[] = { &pi, NULL };
1381 struct device *dev = &pdev->dev;
1382 struct ahci_host_priv *hpriv;
1383 struct ata_host *host;
1384 int n_ports, i, rc;
1385 int ahci_pci_bar = AHCI_PCI_BAR_STANDARD;
1386
1387 VPRINTK("ENTER\n");
1388
1389 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1390
1391 ata_print_version_once(&pdev->dev, DRV_VERSION);
1392
1393 /* The AHCI driver can only drive the SATA ports, the PATA driver
1394 can drive them all so if both drivers are selected make sure
1395 AHCI stays out of the way */
1396 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1397 return -ENODEV;
1398
1399 /* Apple BIOS on MCP89 prevents us using AHCI */
1400 if (is_mcp89_apple(pdev))
1401 ahci_mcp89_apple_enable(pdev);
1402
1403 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
1404 * At the moment, we can only use the AHCI mode. Let the users know
1405 * that for SAS drives they're out of luck.
1406 */
1407 if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
1408 dev_info(&pdev->dev,
1409 "PDC42819 can only drive SATA devices with this driver\n");
1410
1411 /* Both Connext and Enmotus devices use non-standard BARs */
1412 if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06)
1413 ahci_pci_bar = AHCI_PCI_BAR_STA2X11;
1414 else if (pdev->vendor == 0x1c44 && pdev->device == 0x8000)
1415 ahci_pci_bar = AHCI_PCI_BAR_ENMOTUS;
1416
1417 /*
1418 * The JMicron chip 361/363 contains one SATA controller and one
1419 * PATA controller,for powering on these both controllers, we must
1420 * follow the sequence one by one, otherwise one of them can not be
1421 * powered on successfully, so here we disable the async suspend
1422 * method for these chips.
1423 */
1424 if (pdev->vendor == PCI_VENDOR_ID_JMICRON &&
1425 (pdev->device == PCI_DEVICE_ID_JMICRON_JMB363 ||
1426 pdev->device == PCI_DEVICE_ID_JMICRON_JMB361))
1427 device_disable_async_suspend(&pdev->dev);
1428
1429 /* acquire resources */
1430 rc = pcim_enable_device(pdev);
1431 if (rc)
1432 return rc;
1433
1434 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1435 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1436 u8 map;
1437
1438 /* ICH6s share the same PCI ID for both piix and ahci
1439 * modes. Enabling ahci mode while MAP indicates
1440 * combined mode is a bad idea. Yield to ata_piix.
1441 */
1442 pci_read_config_byte(pdev, ICH_MAP, &map);
1443 if (map & 0x3) {
1444 dev_info(&pdev->dev,
1445 "controller is in combined mode, can't enable AHCI mode\n");
1446 return -ENODEV;
1447 }
1448 }
1449
1450 /* AHCI controllers often implement SFF compatible interface.
1451 * Grab all PCI BARs just in case.
1452 */
1453 rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME);
1454 if (rc == -EBUSY)
1455 pcim_pin_device(pdev);
1456 if (rc)
1457 return rc;
1458
1459 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1460 if (!hpriv)
1461 return -ENOMEM;
1462 hpriv->flags |= (unsigned long)pi.private_data;
1463
1464 /* MCP65 revision A1 and A2 can't do MSI */
1465 if (board_id == board_ahci_mcp65 &&
1466 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1467 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1468
1469 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
1470 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1471 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1472
1473 /* only some SB600s can do 64bit DMA */
1474 if (ahci_sb600_enable_64bit(pdev))
1475 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
1476
1477 hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar];
1478
1479 /* must set flag prior to save config in order to take effect */
1480 if (ahci_broken_devslp(pdev))
1481 hpriv->flags |= AHCI_HFLAG_NO_DEVSLP;
1482
1483 /* save initial config */
1484 ahci_pci_save_initial_config(pdev, hpriv);
1485
1486 /* prepare host */
1487 if (hpriv->cap & HOST_CAP_NCQ) {
1488 pi.flags |= ATA_FLAG_NCQ;
1489 /*
1490 * Auto-activate optimization is supposed to be
1491 * supported on all AHCI controllers indicating NCQ
1492 * capability, but it seems to be broken on some
1493 * chipsets including NVIDIAs.
1494 */
1495 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
1496 pi.flags |= ATA_FLAG_FPDMA_AA;
1497
1498 /*
1499 * All AHCI controllers should be forward-compatible
1500 * with the new auxiliary field. This code should be
1501 * conditionalized if any buggy AHCI controllers are
1502 * encountered.
1503 */
1504 pi.flags |= ATA_FLAG_FPDMA_AUX;
1505 }
1506
1507 if (hpriv->cap & HOST_CAP_PMP)
1508 pi.flags |= ATA_FLAG_PMP;
1509
1510 ahci_set_em_messages(hpriv, &pi);
1511
1512 if (ahci_broken_system_poweroff(pdev)) {
1513 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1514 dev_info(&pdev->dev,
1515 "quirky BIOS, skipping spindown on poweroff\n");
1516 }
1517
1518 if (ahci_broken_suspend(pdev)) {
1519 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
1520 dev_warn(&pdev->dev,
1521 "BIOS update required for suspend/resume\n");
1522 }
1523
1524 if (ahci_broken_online(pdev)) {
1525 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1526 dev_info(&pdev->dev,
1527 "online status unreliable, applying workaround\n");
1528 }
1529
1530 /* CAP.NP sometimes indicate the index of the last enabled
1531 * port, at other times, that of the last possible port, so
1532 * determining the maximum port number requires looking at
1533 * both CAP.NP and port_map.
1534 */
1535 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1536
1537 ahci_init_interrupts(pdev, n_ports, hpriv);
1538
1539 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
1540 if (!host)
1541 return -ENOMEM;
1542 host->private_data = hpriv;
1543
1544 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
1545 host->flags |= ATA_HOST_PARALLEL_SCAN;
1546 else
1547 dev_info(&pdev->dev, "SSS flag set, parallel bus scan disabled\n");
1548
1549 if (pi.flags & ATA_FLAG_EM)
1550 ahci_reset_em(host);
1551
1552 for (i = 0; i < host->n_ports; i++) {
1553 struct ata_port *ap = host->ports[i];
1554
1555 ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar");
1556 ata_port_pbar_desc(ap, ahci_pci_bar,
1557 0x100 + ap->port_no * 0x80, "port");
1558
1559 /* set enclosure management message type */
1560 if (ap->flags & ATA_FLAG_EM)
1561 ap->em_message_type = hpriv->em_msg_type;
1562
1563
1564 /* disabled/not-implemented port */
1565 if (!(hpriv->port_map & (1 << i)))
1566 ap->ops = &ata_dummy_port_ops;
1567 }
1568
1569 /* apply workaround for ASUS P5W DH Deluxe mainboard */
1570 ahci_p5wdh_workaround(host);
1571
1572 /* apply gtf filter quirk */
1573 ahci_gtf_filter_workaround(host);
1574
1575 /* initialize adapter */
1576 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1577 if (rc)
1578 return rc;
1579
1580 rc = ahci_pci_reset_controller(host);
1581 if (rc)
1582 return rc;
1583
1584 ahci_pci_init_controller(host);
1585 ahci_pci_print_info(host);
1586
1587 pci_set_master(pdev);
1588
1589 return ahci_host_activate(host, pdev->irq, &ahci_sht);
1590 }
1591
1592 module_pci_driver(ahci_pci_driver);
1593
1594 MODULE_AUTHOR("Jeff Garzik");
1595 MODULE_DESCRIPTION("AHCI SATA low-level driver");
1596 MODULE_LICENSE("GPL");
1597 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
1598 MODULE_VERSION(DRV_VERSION);
1599