1 /*
2 * libahci.c - Common AHCI SATA low-level routines
3 *
4 * Maintained by: Tejun Heo <tj@kernel.org>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
32 *
33 */
34
35 #include <linux/kernel.h>
36 #include <linux/gfp.h>
37 #include <linux/module.h>
38 #include <linux/blkdev.h>
39 #include <linux/delay.h>
40 #include <linux/interrupt.h>
41 #include <linux/dma-mapping.h>
42 #include <linux/device.h>
43 #include <scsi/scsi_host.h>
44 #include <scsi/scsi_cmnd.h>
45 #include <linux/libata.h>
46 #include "ahci.h"
47 #include "libata.h"
48
49 static int ahci_skip_host_reset;
50 int ahci_ignore_sss;
51 EXPORT_SYMBOL_GPL(ahci_ignore_sss);
52
53 module_param_named(skip_host_reset, ahci_skip_host_reset, int, 0444);
54 MODULE_PARM_DESC(skip_host_reset, "skip global host reset (0=don't skip, 1=skip)");
55
56 module_param_named(ignore_sss, ahci_ignore_sss, int, 0444);
57 MODULE_PARM_DESC(ignore_sss, "Ignore staggered spinup flag (0=don't ignore, 1=ignore)");
58
59 static int ahci_set_lpm(struct ata_link *link, enum ata_lpm_policy policy,
60 unsigned hints);
61 static ssize_t ahci_led_show(struct ata_port *ap, char *buf);
62 static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
63 size_t size);
64 static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
65 ssize_t size);
66
67
68
69 static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val);
70 static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val);
71 static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc);
72 static int ahci_port_start(struct ata_port *ap);
73 static void ahci_port_stop(struct ata_port *ap);
74 static void ahci_qc_prep(struct ata_queued_cmd *qc);
75 static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc);
76 static void ahci_freeze(struct ata_port *ap);
77 static void ahci_thaw(struct ata_port *ap);
78 static void ahci_set_aggressive_devslp(struct ata_port *ap, bool sleep);
79 static void ahci_enable_fbs(struct ata_port *ap);
80 static void ahci_disable_fbs(struct ata_port *ap);
81 static void ahci_pmp_attach(struct ata_port *ap);
82 static void ahci_pmp_detach(struct ata_port *ap);
83 static int ahci_softreset(struct ata_link *link, unsigned int *class,
84 unsigned long deadline);
85 static int ahci_pmp_retry_softreset(struct ata_link *link, unsigned int *class,
86 unsigned long deadline);
87 static int ahci_hardreset(struct ata_link *link, unsigned int *class,
88 unsigned long deadline);
89 static void ahci_postreset(struct ata_link *link, unsigned int *class);
90 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
91 static void ahci_dev_config(struct ata_device *dev);
92 #ifdef CONFIG_PM
93 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);
94 #endif
95 static ssize_t ahci_activity_show(struct ata_device *dev, char *buf);
96 static ssize_t ahci_activity_store(struct ata_device *dev,
97 enum sw_activity val);
98 static void ahci_init_sw_activity(struct ata_link *link);
99
100 static ssize_t ahci_show_host_caps(struct device *dev,
101 struct device_attribute *attr, char *buf);
102 static ssize_t ahci_show_host_cap2(struct device *dev,
103 struct device_attribute *attr, char *buf);
104 static ssize_t ahci_show_host_version(struct device *dev,
105 struct device_attribute *attr, char *buf);
106 static ssize_t ahci_show_port_cmd(struct device *dev,
107 struct device_attribute *attr, char *buf);
108 static ssize_t ahci_read_em_buffer(struct device *dev,
109 struct device_attribute *attr, char *buf);
110 static ssize_t ahci_store_em_buffer(struct device *dev,
111 struct device_attribute *attr,
112 const char *buf, size_t size);
113 static ssize_t ahci_show_em_supported(struct device *dev,
114 struct device_attribute *attr, char *buf);
115
116 static DEVICE_ATTR(ahci_host_caps, S_IRUGO, ahci_show_host_caps, NULL);
117 static DEVICE_ATTR(ahci_host_cap2, S_IRUGO, ahci_show_host_cap2, NULL);
118 static DEVICE_ATTR(ahci_host_version, S_IRUGO, ahci_show_host_version, NULL);
119 static DEVICE_ATTR(ahci_port_cmd, S_IRUGO, ahci_show_port_cmd, NULL);
120 static DEVICE_ATTR(em_buffer, S_IWUSR | S_IRUGO,
121 ahci_read_em_buffer, ahci_store_em_buffer);
122 static DEVICE_ATTR(em_message_supported, S_IRUGO, ahci_show_em_supported, NULL);
123
124 struct device_attribute *ahci_shost_attrs[] = {
125 &dev_attr_link_power_management_policy,
126 &dev_attr_em_message_type,
127 &dev_attr_em_message,
128 &dev_attr_ahci_host_caps,
129 &dev_attr_ahci_host_cap2,
130 &dev_attr_ahci_host_version,
131 &dev_attr_ahci_port_cmd,
132 &dev_attr_em_buffer,
133 &dev_attr_em_message_supported,
134 NULL
135 };
136 EXPORT_SYMBOL_GPL(ahci_shost_attrs);
137
138 struct device_attribute *ahci_sdev_attrs[] = {
139 &dev_attr_sw_activity,
140 &dev_attr_unload_heads,
141 NULL
142 };
143 EXPORT_SYMBOL_GPL(ahci_sdev_attrs);
144
145 struct ata_port_operations ahci_ops = {
146 .inherits = &sata_pmp_port_ops,
147
148 .qc_defer = ahci_pmp_qc_defer,
149 .qc_prep = ahci_qc_prep,
150 .qc_issue = ahci_qc_issue,
151 .qc_fill_rtf = ahci_qc_fill_rtf,
152
153 .freeze = ahci_freeze,
154 .thaw = ahci_thaw,
155 .softreset = ahci_softreset,
156 .hardreset = ahci_hardreset,
157 .postreset = ahci_postreset,
158 .pmp_softreset = ahci_softreset,
159 .error_handler = ahci_error_handler,
160 .post_internal_cmd = ahci_post_internal_cmd,
161 .dev_config = ahci_dev_config,
162
163 .scr_read = ahci_scr_read,
164 .scr_write = ahci_scr_write,
165 .pmp_attach = ahci_pmp_attach,
166 .pmp_detach = ahci_pmp_detach,
167
168 .set_lpm = ahci_set_lpm,
169 .em_show = ahci_led_show,
170 .em_store = ahci_led_store,
171 .sw_activity_show = ahci_activity_show,
172 .sw_activity_store = ahci_activity_store,
173 .transmit_led_message = ahci_transmit_led_message,
174 #ifdef CONFIG_PM
175 .port_suspend = ahci_port_suspend,
176 .port_resume = ahci_port_resume,
177 #endif
178 .port_start = ahci_port_start,
179 .port_stop = ahci_port_stop,
180 };
181 EXPORT_SYMBOL_GPL(ahci_ops);
182
183 struct ata_port_operations ahci_pmp_retry_srst_ops = {
184 .inherits = &ahci_ops,
185 .softreset = ahci_pmp_retry_softreset,
186 };
187 EXPORT_SYMBOL_GPL(ahci_pmp_retry_srst_ops);
188
189 static bool ahci_em_messages __read_mostly = true;
190 EXPORT_SYMBOL_GPL(ahci_em_messages);
191 module_param(ahci_em_messages, bool, 0444);
192 /* add other LED protocol types when they become supported */
193 MODULE_PARM_DESC(ahci_em_messages,
194 "AHCI Enclosure Management Message control (0 = off, 1 = on)");
195
196 /* device sleep idle timeout in ms */
197 static int devslp_idle_timeout __read_mostly = 1000;
198 module_param(devslp_idle_timeout, int, 0644);
199 MODULE_PARM_DESC(devslp_idle_timeout, "device sleep idle timeout");
200
ahci_enable_ahci(void __iomem * mmio)201 static void ahci_enable_ahci(void __iomem *mmio)
202 {
203 int i;
204 u32 tmp;
205
206 /* turn on AHCI_EN */
207 tmp = readl(mmio + HOST_CTL);
208 if (tmp & HOST_AHCI_EN)
209 return;
210
211 /* Some controllers need AHCI_EN to be written multiple times.
212 * Try a few times before giving up.
213 */
214 for (i = 0; i < 5; i++) {
215 tmp |= HOST_AHCI_EN;
216 writel(tmp, mmio + HOST_CTL);
217 tmp = readl(mmio + HOST_CTL); /* flush && sanity check */
218 if (tmp & HOST_AHCI_EN)
219 return;
220 msleep(10);
221 }
222
223 WARN_ON(1);
224 }
225
ahci_show_host_caps(struct device * dev,struct device_attribute * attr,char * buf)226 static ssize_t ahci_show_host_caps(struct device *dev,
227 struct device_attribute *attr, char *buf)
228 {
229 struct Scsi_Host *shost = class_to_shost(dev);
230 struct ata_port *ap = ata_shost_to_port(shost);
231 struct ahci_host_priv *hpriv = ap->host->private_data;
232
233 return sprintf(buf, "%x\n", hpriv->cap);
234 }
235
ahci_show_host_cap2(struct device * dev,struct device_attribute * attr,char * buf)236 static ssize_t ahci_show_host_cap2(struct device *dev,
237 struct device_attribute *attr, char *buf)
238 {
239 struct Scsi_Host *shost = class_to_shost(dev);
240 struct ata_port *ap = ata_shost_to_port(shost);
241 struct ahci_host_priv *hpriv = ap->host->private_data;
242
243 return sprintf(buf, "%x\n", hpriv->cap2);
244 }
245
ahci_show_host_version(struct device * dev,struct device_attribute * attr,char * buf)246 static ssize_t ahci_show_host_version(struct device *dev,
247 struct device_attribute *attr, char *buf)
248 {
249 struct Scsi_Host *shost = class_to_shost(dev);
250 struct ata_port *ap = ata_shost_to_port(shost);
251 struct ahci_host_priv *hpriv = ap->host->private_data;
252 void __iomem *mmio = hpriv->mmio;
253
254 return sprintf(buf, "%x\n", readl(mmio + HOST_VERSION));
255 }
256
ahci_show_port_cmd(struct device * dev,struct device_attribute * attr,char * buf)257 static ssize_t ahci_show_port_cmd(struct device *dev,
258 struct device_attribute *attr, char *buf)
259 {
260 struct Scsi_Host *shost = class_to_shost(dev);
261 struct ata_port *ap = ata_shost_to_port(shost);
262 void __iomem *port_mmio = ahci_port_base(ap);
263
264 return sprintf(buf, "%x\n", readl(port_mmio + PORT_CMD));
265 }
266
ahci_read_em_buffer(struct device * dev,struct device_attribute * attr,char * buf)267 static ssize_t ahci_read_em_buffer(struct device *dev,
268 struct device_attribute *attr, char *buf)
269 {
270 struct Scsi_Host *shost = class_to_shost(dev);
271 struct ata_port *ap = ata_shost_to_port(shost);
272 struct ahci_host_priv *hpriv = ap->host->private_data;
273 void __iomem *mmio = hpriv->mmio;
274 void __iomem *em_mmio = mmio + hpriv->em_loc;
275 u32 em_ctl, msg;
276 unsigned long flags;
277 size_t count;
278 int i;
279
280 spin_lock_irqsave(ap->lock, flags);
281
282 em_ctl = readl(mmio + HOST_EM_CTL);
283 if (!(ap->flags & ATA_FLAG_EM) || em_ctl & EM_CTL_XMT ||
284 !(hpriv->em_msg_type & EM_MSG_TYPE_SGPIO)) {
285 spin_unlock_irqrestore(ap->lock, flags);
286 return -EINVAL;
287 }
288
289 if (!(em_ctl & EM_CTL_MR)) {
290 spin_unlock_irqrestore(ap->lock, flags);
291 return -EAGAIN;
292 }
293
294 if (!(em_ctl & EM_CTL_SMB))
295 em_mmio += hpriv->em_buf_sz;
296
297 count = hpriv->em_buf_sz;
298
299 /* the count should not be larger than PAGE_SIZE */
300 if (count > PAGE_SIZE) {
301 if (printk_ratelimit())
302 ata_port_warn(ap,
303 "EM read buffer size too large: "
304 "buffer size %u, page size %lu\n",
305 hpriv->em_buf_sz, PAGE_SIZE);
306 count = PAGE_SIZE;
307 }
308
309 for (i = 0; i < count; i += 4) {
310 msg = readl(em_mmio + i);
311 buf[i] = msg & 0xff;
312 buf[i + 1] = (msg >> 8) & 0xff;
313 buf[i + 2] = (msg >> 16) & 0xff;
314 buf[i + 3] = (msg >> 24) & 0xff;
315 }
316
317 spin_unlock_irqrestore(ap->lock, flags);
318
319 return i;
320 }
321
ahci_store_em_buffer(struct device * dev,struct device_attribute * attr,const char * buf,size_t size)322 static ssize_t ahci_store_em_buffer(struct device *dev,
323 struct device_attribute *attr,
324 const char *buf, size_t size)
325 {
326 struct Scsi_Host *shost = class_to_shost(dev);
327 struct ata_port *ap = ata_shost_to_port(shost);
328 struct ahci_host_priv *hpriv = ap->host->private_data;
329 void __iomem *mmio = hpriv->mmio;
330 void __iomem *em_mmio = mmio + hpriv->em_loc;
331 const unsigned char *msg_buf = buf;
332 u32 em_ctl, msg;
333 unsigned long flags;
334 int i;
335
336 /* check size validity */
337 if (!(ap->flags & ATA_FLAG_EM) ||
338 !(hpriv->em_msg_type & EM_MSG_TYPE_SGPIO) ||
339 size % 4 || size > hpriv->em_buf_sz)
340 return -EINVAL;
341
342 spin_lock_irqsave(ap->lock, flags);
343
344 em_ctl = readl(mmio + HOST_EM_CTL);
345 if (em_ctl & EM_CTL_TM) {
346 spin_unlock_irqrestore(ap->lock, flags);
347 return -EBUSY;
348 }
349
350 for (i = 0; i < size; i += 4) {
351 msg = msg_buf[i] | msg_buf[i + 1] << 8 |
352 msg_buf[i + 2] << 16 | msg_buf[i + 3] << 24;
353 writel(msg, em_mmio + i);
354 }
355
356 writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL);
357
358 spin_unlock_irqrestore(ap->lock, flags);
359
360 return size;
361 }
362
ahci_show_em_supported(struct device * dev,struct device_attribute * attr,char * buf)363 static ssize_t ahci_show_em_supported(struct device *dev,
364 struct device_attribute *attr, char *buf)
365 {
366 struct Scsi_Host *shost = class_to_shost(dev);
367 struct ata_port *ap = ata_shost_to_port(shost);
368 struct ahci_host_priv *hpriv = ap->host->private_data;
369 void __iomem *mmio = hpriv->mmio;
370 u32 em_ctl;
371
372 em_ctl = readl(mmio + HOST_EM_CTL);
373
374 return sprintf(buf, "%s%s%s%s\n",
375 em_ctl & EM_CTL_LED ? "led " : "",
376 em_ctl & EM_CTL_SAFTE ? "saf-te " : "",
377 em_ctl & EM_CTL_SES ? "ses-2 " : "",
378 em_ctl & EM_CTL_SGPIO ? "sgpio " : "");
379 }
380
381 /**
382 * ahci_save_initial_config - Save and fixup initial config values
383 * @dev: target AHCI device
384 * @hpriv: host private area to store config values
385 *
386 * Some registers containing configuration info might be setup by
387 * BIOS and might be cleared on reset. This function saves the
388 * initial values of those registers into @hpriv such that they
389 * can be restored after controller reset.
390 *
391 * If inconsistent, config values are fixed up by this function.
392 *
393 * If it is not set already this function sets hpriv->start_engine to
394 * ahci_start_engine.
395 *
396 * LOCKING:
397 * None.
398 */
ahci_save_initial_config(struct device * dev,struct ahci_host_priv * hpriv)399 void ahci_save_initial_config(struct device *dev, struct ahci_host_priv *hpriv)
400 {
401 void __iomem *mmio = hpriv->mmio;
402 u32 cap, cap2, vers, port_map;
403 int i;
404
405 /* make sure AHCI mode is enabled before accessing CAP */
406 ahci_enable_ahci(mmio);
407
408 /* Values prefixed with saved_ are written back to host after
409 * reset. Values without are used for driver operation.
410 */
411 hpriv->saved_cap = cap = readl(mmio + HOST_CAP);
412 hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL);
413
414 /* CAP2 register is only defined for AHCI 1.2 and later */
415 vers = readl(mmio + HOST_VERSION);
416 if ((vers >> 16) > 1 ||
417 ((vers >> 16) == 1 && (vers & 0xFFFF) >= 0x200))
418 hpriv->saved_cap2 = cap2 = readl(mmio + HOST_CAP2);
419 else
420 hpriv->saved_cap2 = cap2 = 0;
421
422 /* some chips have errata preventing 64bit use */
423 if ((cap & HOST_CAP_64) && (hpriv->flags & AHCI_HFLAG_32BIT_ONLY)) {
424 dev_info(dev, "controller can't do 64bit DMA, forcing 32bit\n");
425 cap &= ~HOST_CAP_64;
426 }
427
428 if ((cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_NO_NCQ)) {
429 dev_info(dev, "controller can't do NCQ, turning off CAP_NCQ\n");
430 cap &= ~HOST_CAP_NCQ;
431 }
432
433 if (!(cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_YES_NCQ)) {
434 dev_info(dev, "controller can do NCQ, turning on CAP_NCQ\n");
435 cap |= HOST_CAP_NCQ;
436 }
437
438 if ((cap & HOST_CAP_PMP) && (hpriv->flags & AHCI_HFLAG_NO_PMP)) {
439 dev_info(dev, "controller can't do PMP, turning off CAP_PMP\n");
440 cap &= ~HOST_CAP_PMP;
441 }
442
443 if ((cap & HOST_CAP_SNTF) && (hpriv->flags & AHCI_HFLAG_NO_SNTF)) {
444 dev_info(dev,
445 "controller can't do SNTF, turning off CAP_SNTF\n");
446 cap &= ~HOST_CAP_SNTF;
447 }
448
449 if ((cap2 & HOST_CAP2_SDS) && (hpriv->flags & AHCI_HFLAG_NO_DEVSLP)) {
450 dev_info(dev,
451 "controller can't do DEVSLP, turning off\n");
452 cap2 &= ~HOST_CAP2_SDS;
453 cap2 &= ~HOST_CAP2_SADM;
454 }
455
456 if (!(cap & HOST_CAP_FBS) && (hpriv->flags & AHCI_HFLAG_YES_FBS)) {
457 dev_info(dev, "controller can do FBS, turning on CAP_FBS\n");
458 cap |= HOST_CAP_FBS;
459 }
460
461 if ((cap & HOST_CAP_FBS) && (hpriv->flags & AHCI_HFLAG_NO_FBS)) {
462 dev_info(dev, "controller can't do FBS, turning off CAP_FBS\n");
463 cap &= ~HOST_CAP_FBS;
464 }
465
466 if (hpriv->force_port_map && port_map != hpriv->force_port_map) {
467 dev_info(dev, "forcing port_map 0x%x -> 0x%x\n",
468 port_map, hpriv->force_port_map);
469 port_map = hpriv->force_port_map;
470 hpriv->saved_port_map = port_map;
471 }
472
473 if (hpriv->mask_port_map) {
474 dev_warn(dev, "masking port_map 0x%x -> 0x%x\n",
475 port_map,
476 port_map & hpriv->mask_port_map);
477 port_map &= hpriv->mask_port_map;
478 }
479
480 /* cross check port_map and cap.n_ports */
481 if (port_map) {
482 int map_ports = 0;
483
484 for (i = 0; i < AHCI_MAX_PORTS; i++)
485 if (port_map & (1 << i))
486 map_ports++;
487
488 /* If PI has more ports than n_ports, whine, clear
489 * port_map and let it be generated from n_ports.
490 */
491 if (map_ports > ahci_nr_ports(cap)) {
492 dev_warn(dev,
493 "implemented port map (0x%x) contains more ports than nr_ports (%u), using nr_ports\n",
494 port_map, ahci_nr_ports(cap));
495 port_map = 0;
496 }
497 }
498
499 /* fabricate port_map from cap.nr_ports for < AHCI 1.3 */
500 if (!port_map && vers < 0x10300) {
501 port_map = (1 << ahci_nr_ports(cap)) - 1;
502 dev_warn(dev, "forcing PORTS_IMPL to 0x%x\n", port_map);
503
504 /* write the fixed up value to the PI register */
505 hpriv->saved_port_map = port_map;
506 }
507
508 /* record values to use during operation */
509 hpriv->cap = cap;
510 hpriv->cap2 = cap2;
511 hpriv->port_map = port_map;
512
513 if (!hpriv->start_engine)
514 hpriv->start_engine = ahci_start_engine;
515 }
516 EXPORT_SYMBOL_GPL(ahci_save_initial_config);
517
518 /**
519 * ahci_restore_initial_config - Restore initial config
520 * @host: target ATA host
521 *
522 * Restore initial config stored by ahci_save_initial_config().
523 *
524 * LOCKING:
525 * None.
526 */
ahci_restore_initial_config(struct ata_host * host)527 static void ahci_restore_initial_config(struct ata_host *host)
528 {
529 struct ahci_host_priv *hpriv = host->private_data;
530 void __iomem *mmio = hpriv->mmio;
531
532 writel(hpriv->saved_cap, mmio + HOST_CAP);
533 if (hpriv->saved_cap2)
534 writel(hpriv->saved_cap2, mmio + HOST_CAP2);
535 writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL);
536 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
537 }
538
ahci_scr_offset(struct ata_port * ap,unsigned int sc_reg)539 static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg)
540 {
541 static const int offset[] = {
542 [SCR_STATUS] = PORT_SCR_STAT,
543 [SCR_CONTROL] = PORT_SCR_CTL,
544 [SCR_ERROR] = PORT_SCR_ERR,
545 [SCR_ACTIVE] = PORT_SCR_ACT,
546 [SCR_NOTIFICATION] = PORT_SCR_NTF,
547 };
548 struct ahci_host_priv *hpriv = ap->host->private_data;
549
550 if (sc_reg < ARRAY_SIZE(offset) &&
551 (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF)))
552 return offset[sc_reg];
553 return 0;
554 }
555
ahci_scr_read(struct ata_link * link,unsigned int sc_reg,u32 * val)556 static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val)
557 {
558 void __iomem *port_mmio = ahci_port_base(link->ap);
559 int offset = ahci_scr_offset(link->ap, sc_reg);
560
561 if (offset) {
562 *val = readl(port_mmio + offset);
563 return 0;
564 }
565 return -EINVAL;
566 }
567
ahci_scr_write(struct ata_link * link,unsigned int sc_reg,u32 val)568 static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val)
569 {
570 void __iomem *port_mmio = ahci_port_base(link->ap);
571 int offset = ahci_scr_offset(link->ap, sc_reg);
572
573 if (offset) {
574 writel(val, port_mmio + offset);
575 return 0;
576 }
577 return -EINVAL;
578 }
579
ahci_start_engine(struct ata_port * ap)580 void ahci_start_engine(struct ata_port *ap)
581 {
582 void __iomem *port_mmio = ahci_port_base(ap);
583 u32 tmp;
584
585 /* start DMA */
586 tmp = readl(port_mmio + PORT_CMD);
587 tmp |= PORT_CMD_START;
588 writel(tmp, port_mmio + PORT_CMD);
589 readl(port_mmio + PORT_CMD); /* flush */
590 }
591 EXPORT_SYMBOL_GPL(ahci_start_engine);
592
ahci_stop_engine(struct ata_port * ap)593 int ahci_stop_engine(struct ata_port *ap)
594 {
595 void __iomem *port_mmio = ahci_port_base(ap);
596 u32 tmp;
597
598 tmp = readl(port_mmio + PORT_CMD);
599
600 /* check if the HBA is idle */
601 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
602 return 0;
603
604 /* setting HBA to idle */
605 tmp &= ~PORT_CMD_START;
606 writel(tmp, port_mmio + PORT_CMD);
607
608 /* wait for engine to stop. This could be as long as 500 msec */
609 tmp = ata_wait_register(ap, port_mmio + PORT_CMD,
610 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
611 if (tmp & PORT_CMD_LIST_ON)
612 return -EIO;
613
614 return 0;
615 }
616 EXPORT_SYMBOL_GPL(ahci_stop_engine);
617
ahci_start_fis_rx(struct ata_port * ap)618 void ahci_start_fis_rx(struct ata_port *ap)
619 {
620 void __iomem *port_mmio = ahci_port_base(ap);
621 struct ahci_host_priv *hpriv = ap->host->private_data;
622 struct ahci_port_priv *pp = ap->private_data;
623 u32 tmp;
624
625 /* set FIS registers */
626 if (hpriv->cap & HOST_CAP_64)
627 writel((pp->cmd_slot_dma >> 16) >> 16,
628 port_mmio + PORT_LST_ADDR_HI);
629 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
630
631 if (hpriv->cap & HOST_CAP_64)
632 writel((pp->rx_fis_dma >> 16) >> 16,
633 port_mmio + PORT_FIS_ADDR_HI);
634 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
635
636 /* enable FIS reception */
637 tmp = readl(port_mmio + PORT_CMD);
638 tmp |= PORT_CMD_FIS_RX;
639 writel(tmp, port_mmio + PORT_CMD);
640
641 /* flush */
642 readl(port_mmio + PORT_CMD);
643 }
644 EXPORT_SYMBOL_GPL(ahci_start_fis_rx);
645
ahci_stop_fis_rx(struct ata_port * ap)646 static int ahci_stop_fis_rx(struct ata_port *ap)
647 {
648 void __iomem *port_mmio = ahci_port_base(ap);
649 u32 tmp;
650
651 /* disable FIS reception */
652 tmp = readl(port_mmio + PORT_CMD);
653 tmp &= ~PORT_CMD_FIS_RX;
654 writel(tmp, port_mmio + PORT_CMD);
655
656 /* wait for completion, spec says 500ms, give it 1000 */
657 tmp = ata_wait_register(ap, port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
658 PORT_CMD_FIS_ON, 10, 1000);
659 if (tmp & PORT_CMD_FIS_ON)
660 return -EBUSY;
661
662 return 0;
663 }
664
ahci_power_up(struct ata_port * ap)665 static void ahci_power_up(struct ata_port *ap)
666 {
667 struct ahci_host_priv *hpriv = ap->host->private_data;
668 void __iomem *port_mmio = ahci_port_base(ap);
669 u32 cmd;
670
671 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
672
673 /* spin up device */
674 if (hpriv->cap & HOST_CAP_SSS) {
675 cmd |= PORT_CMD_SPIN_UP;
676 writel(cmd, port_mmio + PORT_CMD);
677 }
678
679 /* wake up link */
680 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
681 }
682
ahci_set_lpm(struct ata_link * link,enum ata_lpm_policy policy,unsigned int hints)683 static int ahci_set_lpm(struct ata_link *link, enum ata_lpm_policy policy,
684 unsigned int hints)
685 {
686 struct ata_port *ap = link->ap;
687 struct ahci_host_priv *hpriv = ap->host->private_data;
688 struct ahci_port_priv *pp = ap->private_data;
689 void __iomem *port_mmio = ahci_port_base(ap);
690
691 if (policy != ATA_LPM_MAX_POWER) {
692 /*
693 * Disable interrupts on Phy Ready. This keeps us from
694 * getting woken up due to spurious phy ready
695 * interrupts.
696 */
697 pp->intr_mask &= ~PORT_IRQ_PHYRDY;
698 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
699
700 sata_link_scr_lpm(link, policy, false);
701 }
702
703 if (hpriv->cap & HOST_CAP_ALPM) {
704 u32 cmd = readl(port_mmio + PORT_CMD);
705
706 if (policy == ATA_LPM_MAX_POWER || !(hints & ATA_LPM_HIPM)) {
707 cmd &= ~(PORT_CMD_ASP | PORT_CMD_ALPE);
708 cmd |= PORT_CMD_ICC_ACTIVE;
709
710 writel(cmd, port_mmio + PORT_CMD);
711 readl(port_mmio + PORT_CMD);
712
713 /* wait 10ms to be sure we've come out of LPM state */
714 ata_msleep(ap, 10);
715 } else {
716 cmd |= PORT_CMD_ALPE;
717 if (policy == ATA_LPM_MIN_POWER)
718 cmd |= PORT_CMD_ASP;
719
720 /* write out new cmd value */
721 writel(cmd, port_mmio + PORT_CMD);
722 }
723 }
724
725 /* set aggressive device sleep */
726 if ((hpriv->cap2 & HOST_CAP2_SDS) &&
727 (hpriv->cap2 & HOST_CAP2_SADM) &&
728 (link->device->flags & ATA_DFLAG_DEVSLP)) {
729 if (policy == ATA_LPM_MIN_POWER)
730 ahci_set_aggressive_devslp(ap, true);
731 else
732 ahci_set_aggressive_devslp(ap, false);
733 }
734
735 if (policy == ATA_LPM_MAX_POWER) {
736 sata_link_scr_lpm(link, policy, false);
737
738 /* turn PHYRDY IRQ back on */
739 pp->intr_mask |= PORT_IRQ_PHYRDY;
740 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
741 }
742
743 return 0;
744 }
745
746 #ifdef CONFIG_PM
ahci_power_down(struct ata_port * ap)747 static void ahci_power_down(struct ata_port *ap)
748 {
749 struct ahci_host_priv *hpriv = ap->host->private_data;
750 void __iomem *port_mmio = ahci_port_base(ap);
751 u32 cmd, scontrol;
752
753 if (!(hpriv->cap & HOST_CAP_SSS))
754 return;
755
756 /* put device into listen mode, first set PxSCTL.DET to 0 */
757 scontrol = readl(port_mmio + PORT_SCR_CTL);
758 scontrol &= ~0xf;
759 writel(scontrol, port_mmio + PORT_SCR_CTL);
760
761 /* then set PxCMD.SUD to 0 */
762 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
763 cmd &= ~PORT_CMD_SPIN_UP;
764 writel(cmd, port_mmio + PORT_CMD);
765 }
766 #endif
767
ahci_start_port(struct ata_port * ap)768 static void ahci_start_port(struct ata_port *ap)
769 {
770 struct ahci_host_priv *hpriv = ap->host->private_data;
771 struct ahci_port_priv *pp = ap->private_data;
772 struct ata_link *link;
773 struct ahci_em_priv *emp;
774 ssize_t rc;
775 int i;
776
777 /* enable FIS reception */
778 ahci_start_fis_rx(ap);
779
780 /* enable DMA */
781 if (!(hpriv->flags & AHCI_HFLAG_DELAY_ENGINE))
782 hpriv->start_engine(ap);
783
784 /* turn on LEDs */
785 if (ap->flags & ATA_FLAG_EM) {
786 ata_for_each_link(link, ap, EDGE) {
787 emp = &pp->em_priv[link->pmp];
788
789 /* EM Transmit bit maybe busy during init */
790 for (i = 0; i < EM_MAX_RETRY; i++) {
791 rc = ap->ops->transmit_led_message(ap,
792 emp->led_state,
793 4);
794 /*
795 * If busy, give a breather but do not
796 * release EH ownership by using msleep()
797 * instead of ata_msleep(). EM Transmit
798 * bit is busy for the whole host and
799 * releasing ownership will cause other
800 * ports to fail the same way.
801 */
802 if (rc == -EBUSY)
803 msleep(1);
804 else
805 break;
806 }
807 }
808 }
809
810 if (ap->flags & ATA_FLAG_SW_ACTIVITY)
811 ata_for_each_link(link, ap, EDGE)
812 ahci_init_sw_activity(link);
813
814 }
815
ahci_deinit_port(struct ata_port * ap,const char ** emsg)816 static int ahci_deinit_port(struct ata_port *ap, const char **emsg)
817 {
818 int rc;
819
820 /* disable DMA */
821 rc = ahci_stop_engine(ap);
822 if (rc) {
823 *emsg = "failed to stop engine";
824 return rc;
825 }
826
827 /* disable FIS reception */
828 rc = ahci_stop_fis_rx(ap);
829 if (rc) {
830 *emsg = "failed stop FIS RX";
831 return rc;
832 }
833
834 return 0;
835 }
836
ahci_reset_controller(struct ata_host * host)837 int ahci_reset_controller(struct ata_host *host)
838 {
839 struct ahci_host_priv *hpriv = host->private_data;
840 void __iomem *mmio = hpriv->mmio;
841 u32 tmp;
842
843 /* we must be in AHCI mode, before using anything
844 * AHCI-specific, such as HOST_RESET.
845 */
846 ahci_enable_ahci(mmio);
847
848 /* global controller reset */
849 if (!ahci_skip_host_reset) {
850 tmp = readl(mmio + HOST_CTL);
851 if ((tmp & HOST_RESET) == 0) {
852 writel(tmp | HOST_RESET, mmio + HOST_CTL);
853 readl(mmio + HOST_CTL); /* flush */
854 }
855
856 /*
857 * to perform host reset, OS should set HOST_RESET
858 * and poll until this bit is read to be "0".
859 * reset must complete within 1 second, or
860 * the hardware should be considered fried.
861 */
862 tmp = ata_wait_register(NULL, mmio + HOST_CTL, HOST_RESET,
863 HOST_RESET, 10, 1000);
864
865 if (tmp & HOST_RESET) {
866 dev_err(host->dev, "controller reset failed (0x%x)\n",
867 tmp);
868 return -EIO;
869 }
870
871 /* turn on AHCI mode */
872 ahci_enable_ahci(mmio);
873
874 /* Some registers might be cleared on reset. Restore
875 * initial values.
876 */
877 ahci_restore_initial_config(host);
878 } else
879 dev_info(host->dev, "skipping global host reset\n");
880
881 return 0;
882 }
883 EXPORT_SYMBOL_GPL(ahci_reset_controller);
884
ahci_sw_activity(struct ata_link * link)885 static void ahci_sw_activity(struct ata_link *link)
886 {
887 struct ata_port *ap = link->ap;
888 struct ahci_port_priv *pp = ap->private_data;
889 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
890
891 if (!(link->flags & ATA_LFLAG_SW_ACTIVITY))
892 return;
893
894 emp->activity++;
895 if (!timer_pending(&emp->timer))
896 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(10));
897 }
898
ahci_sw_activity_blink(unsigned long arg)899 static void ahci_sw_activity_blink(unsigned long arg)
900 {
901 struct ata_link *link = (struct ata_link *)arg;
902 struct ata_port *ap = link->ap;
903 struct ahci_port_priv *pp = ap->private_data;
904 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
905 unsigned long led_message = emp->led_state;
906 u32 activity_led_state;
907 unsigned long flags;
908
909 led_message &= EM_MSG_LED_VALUE;
910 led_message |= ap->port_no | (link->pmp << 8);
911
912 /* check to see if we've had activity. If so,
913 * toggle state of LED and reset timer. If not,
914 * turn LED to desired idle state.
915 */
916 spin_lock_irqsave(ap->lock, flags);
917 if (emp->saved_activity != emp->activity) {
918 emp->saved_activity = emp->activity;
919 /* get the current LED state */
920 activity_led_state = led_message & EM_MSG_LED_VALUE_ON;
921
922 if (activity_led_state)
923 activity_led_state = 0;
924 else
925 activity_led_state = 1;
926
927 /* clear old state */
928 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY;
929
930 /* toggle state */
931 led_message |= (activity_led_state << 16);
932 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(100));
933 } else {
934 /* switch to idle */
935 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY;
936 if (emp->blink_policy == BLINK_OFF)
937 led_message |= (1 << 16);
938 }
939 spin_unlock_irqrestore(ap->lock, flags);
940 ap->ops->transmit_led_message(ap, led_message, 4);
941 }
942
ahci_init_sw_activity(struct ata_link * link)943 static void ahci_init_sw_activity(struct ata_link *link)
944 {
945 struct ata_port *ap = link->ap;
946 struct ahci_port_priv *pp = ap->private_data;
947 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
948
949 /* init activity stats, setup timer */
950 emp->saved_activity = emp->activity = 0;
951 setup_timer(&emp->timer, ahci_sw_activity_blink, (unsigned long)link);
952
953 /* check our blink policy and set flag for link if it's enabled */
954 if (emp->blink_policy)
955 link->flags |= ATA_LFLAG_SW_ACTIVITY;
956 }
957
ahci_reset_em(struct ata_host * host)958 int ahci_reset_em(struct ata_host *host)
959 {
960 struct ahci_host_priv *hpriv = host->private_data;
961 void __iomem *mmio = hpriv->mmio;
962 u32 em_ctl;
963
964 em_ctl = readl(mmio + HOST_EM_CTL);
965 if ((em_ctl & EM_CTL_TM) || (em_ctl & EM_CTL_RST))
966 return -EINVAL;
967
968 writel(em_ctl | EM_CTL_RST, mmio + HOST_EM_CTL);
969 return 0;
970 }
971 EXPORT_SYMBOL_GPL(ahci_reset_em);
972
ahci_transmit_led_message(struct ata_port * ap,u32 state,ssize_t size)973 static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
974 ssize_t size)
975 {
976 struct ahci_host_priv *hpriv = ap->host->private_data;
977 struct ahci_port_priv *pp = ap->private_data;
978 void __iomem *mmio = hpriv->mmio;
979 u32 em_ctl;
980 u32 message[] = {0, 0};
981 unsigned long flags;
982 int pmp;
983 struct ahci_em_priv *emp;
984
985 /* get the slot number from the message */
986 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
987 if (pmp < EM_MAX_SLOTS)
988 emp = &pp->em_priv[pmp];
989 else
990 return -EINVAL;
991
992 spin_lock_irqsave(ap->lock, flags);
993
994 /*
995 * if we are still busy transmitting a previous message,
996 * do not allow
997 */
998 em_ctl = readl(mmio + HOST_EM_CTL);
999 if (em_ctl & EM_CTL_TM) {
1000 spin_unlock_irqrestore(ap->lock, flags);
1001 return -EBUSY;
1002 }
1003
1004 if (hpriv->em_msg_type & EM_MSG_TYPE_LED) {
1005 /*
1006 * create message header - this is all zero except for
1007 * the message size, which is 4 bytes.
1008 */
1009 message[0] |= (4 << 8);
1010
1011 /* ignore 0:4 of byte zero, fill in port info yourself */
1012 message[1] = ((state & ~EM_MSG_LED_HBA_PORT) | ap->port_no);
1013
1014 /* write message to EM_LOC */
1015 writel(message[0], mmio + hpriv->em_loc);
1016 writel(message[1], mmio + hpriv->em_loc+4);
1017
1018 /*
1019 * tell hardware to transmit the message
1020 */
1021 writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL);
1022 }
1023
1024 /* save off new led state for port/slot */
1025 emp->led_state = state;
1026
1027 spin_unlock_irqrestore(ap->lock, flags);
1028 return size;
1029 }
1030
ahci_led_show(struct ata_port * ap,char * buf)1031 static ssize_t ahci_led_show(struct ata_port *ap, char *buf)
1032 {
1033 struct ahci_port_priv *pp = ap->private_data;
1034 struct ata_link *link;
1035 struct ahci_em_priv *emp;
1036 int rc = 0;
1037
1038 ata_for_each_link(link, ap, EDGE) {
1039 emp = &pp->em_priv[link->pmp];
1040 rc += sprintf(buf, "%lx\n", emp->led_state);
1041 }
1042 return rc;
1043 }
1044
ahci_led_store(struct ata_port * ap,const char * buf,size_t size)1045 static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
1046 size_t size)
1047 {
1048 unsigned int state;
1049 int pmp;
1050 struct ahci_port_priv *pp = ap->private_data;
1051 struct ahci_em_priv *emp;
1052
1053 if (kstrtouint(buf, 0, &state) < 0)
1054 return -EINVAL;
1055
1056 /* get the slot number from the message */
1057 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
1058 if (pmp < EM_MAX_SLOTS)
1059 emp = &pp->em_priv[pmp];
1060 else
1061 return -EINVAL;
1062
1063 /* mask off the activity bits if we are in sw_activity
1064 * mode, user should turn off sw_activity before setting
1065 * activity led through em_message
1066 */
1067 if (emp->blink_policy)
1068 state &= ~EM_MSG_LED_VALUE_ACTIVITY;
1069
1070 return ap->ops->transmit_led_message(ap, state, size);
1071 }
1072
ahci_activity_store(struct ata_device * dev,enum sw_activity val)1073 static ssize_t ahci_activity_store(struct ata_device *dev, enum sw_activity val)
1074 {
1075 struct ata_link *link = dev->link;
1076 struct ata_port *ap = link->ap;
1077 struct ahci_port_priv *pp = ap->private_data;
1078 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1079 u32 port_led_state = emp->led_state;
1080
1081 /* save the desired Activity LED behavior */
1082 if (val == OFF) {
1083 /* clear LFLAG */
1084 link->flags &= ~(ATA_LFLAG_SW_ACTIVITY);
1085
1086 /* set the LED to OFF */
1087 port_led_state &= EM_MSG_LED_VALUE_OFF;
1088 port_led_state |= (ap->port_no | (link->pmp << 8));
1089 ap->ops->transmit_led_message(ap, port_led_state, 4);
1090 } else {
1091 link->flags |= ATA_LFLAG_SW_ACTIVITY;
1092 if (val == BLINK_OFF) {
1093 /* set LED to ON for idle */
1094 port_led_state &= EM_MSG_LED_VALUE_OFF;
1095 port_led_state |= (ap->port_no | (link->pmp << 8));
1096 port_led_state |= EM_MSG_LED_VALUE_ON; /* check this */
1097 ap->ops->transmit_led_message(ap, port_led_state, 4);
1098 }
1099 }
1100 emp->blink_policy = val;
1101 return 0;
1102 }
1103
ahci_activity_show(struct ata_device * dev,char * buf)1104 static ssize_t ahci_activity_show(struct ata_device *dev, char *buf)
1105 {
1106 struct ata_link *link = dev->link;
1107 struct ata_port *ap = link->ap;
1108 struct ahci_port_priv *pp = ap->private_data;
1109 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1110
1111 /* display the saved value of activity behavior for this
1112 * disk.
1113 */
1114 return sprintf(buf, "%d\n", emp->blink_policy);
1115 }
1116
ahci_port_init(struct device * dev,struct ata_port * ap,int port_no,void __iomem * mmio,void __iomem * port_mmio)1117 static void ahci_port_init(struct device *dev, struct ata_port *ap,
1118 int port_no, void __iomem *mmio,
1119 void __iomem *port_mmio)
1120 {
1121 const char *emsg = NULL;
1122 int rc;
1123 u32 tmp;
1124
1125 /* make sure port is not active */
1126 rc = ahci_deinit_port(ap, &emsg);
1127 if (rc)
1128 dev_warn(dev, "%s (%d)\n", emsg, rc);
1129
1130 /* clear SError */
1131 tmp = readl(port_mmio + PORT_SCR_ERR);
1132 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
1133 writel(tmp, port_mmio + PORT_SCR_ERR);
1134
1135 /* clear port IRQ */
1136 tmp = readl(port_mmio + PORT_IRQ_STAT);
1137 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
1138 if (tmp)
1139 writel(tmp, port_mmio + PORT_IRQ_STAT);
1140
1141 writel(1 << port_no, mmio + HOST_IRQ_STAT);
1142 }
1143
ahci_init_controller(struct ata_host * host)1144 void ahci_init_controller(struct ata_host *host)
1145 {
1146 struct ahci_host_priv *hpriv = host->private_data;
1147 void __iomem *mmio = hpriv->mmio;
1148 int i;
1149 void __iomem *port_mmio;
1150 u32 tmp;
1151
1152 for (i = 0; i < host->n_ports; i++) {
1153 struct ata_port *ap = host->ports[i];
1154
1155 port_mmio = ahci_port_base(ap);
1156 if (ata_port_is_dummy(ap))
1157 continue;
1158
1159 ahci_port_init(host->dev, ap, i, mmio, port_mmio);
1160 }
1161
1162 tmp = readl(mmio + HOST_CTL);
1163 VPRINTK("HOST_CTL 0x%x\n", tmp);
1164 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
1165 tmp = readl(mmio + HOST_CTL);
1166 VPRINTK("HOST_CTL 0x%x\n", tmp);
1167 }
1168 EXPORT_SYMBOL_GPL(ahci_init_controller);
1169
ahci_dev_config(struct ata_device * dev)1170 static void ahci_dev_config(struct ata_device *dev)
1171 {
1172 struct ahci_host_priv *hpriv = dev->link->ap->host->private_data;
1173
1174 if (hpriv->flags & AHCI_HFLAG_SECT255) {
1175 dev->max_sectors = 255;
1176 ata_dev_info(dev,
1177 "SB600 AHCI: limiting to 255 sectors per cmd\n");
1178 }
1179 }
1180
ahci_dev_classify(struct ata_port * ap)1181 unsigned int ahci_dev_classify(struct ata_port *ap)
1182 {
1183 void __iomem *port_mmio = ahci_port_base(ap);
1184 struct ata_taskfile tf;
1185 u32 tmp;
1186
1187 tmp = readl(port_mmio + PORT_SIG);
1188 tf.lbah = (tmp >> 24) & 0xff;
1189 tf.lbam = (tmp >> 16) & 0xff;
1190 tf.lbal = (tmp >> 8) & 0xff;
1191 tf.nsect = (tmp) & 0xff;
1192
1193 return ata_dev_classify(&tf);
1194 }
1195 EXPORT_SYMBOL_GPL(ahci_dev_classify);
1196
ahci_fill_cmd_slot(struct ahci_port_priv * pp,unsigned int tag,u32 opts)1197 void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
1198 u32 opts)
1199 {
1200 dma_addr_t cmd_tbl_dma;
1201
1202 cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ;
1203
1204 pp->cmd_slot[tag].opts = cpu_to_le32(opts);
1205 pp->cmd_slot[tag].status = 0;
1206 pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);
1207 pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);
1208 }
1209 EXPORT_SYMBOL_GPL(ahci_fill_cmd_slot);
1210
ahci_kick_engine(struct ata_port * ap)1211 int ahci_kick_engine(struct ata_port *ap)
1212 {
1213 void __iomem *port_mmio = ahci_port_base(ap);
1214 struct ahci_host_priv *hpriv = ap->host->private_data;
1215 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1216 u32 tmp;
1217 int busy, rc;
1218
1219 /* stop engine */
1220 rc = ahci_stop_engine(ap);
1221 if (rc)
1222 goto out_restart;
1223
1224 /* need to do CLO?
1225 * always do CLO if PMP is attached (AHCI-1.3 9.2)
1226 */
1227 busy = status & (ATA_BUSY | ATA_DRQ);
1228 if (!busy && !sata_pmp_attached(ap)) {
1229 rc = 0;
1230 goto out_restart;
1231 }
1232
1233 if (!(hpriv->cap & HOST_CAP_CLO)) {
1234 rc = -EOPNOTSUPP;
1235 goto out_restart;
1236 }
1237
1238 /* perform CLO */
1239 tmp = readl(port_mmio + PORT_CMD);
1240 tmp |= PORT_CMD_CLO;
1241 writel(tmp, port_mmio + PORT_CMD);
1242
1243 rc = 0;
1244 tmp = ata_wait_register(ap, port_mmio + PORT_CMD,
1245 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
1246 if (tmp & PORT_CMD_CLO)
1247 rc = -EIO;
1248
1249 /* restart engine */
1250 out_restart:
1251 hpriv->start_engine(ap);
1252 return rc;
1253 }
1254 EXPORT_SYMBOL_GPL(ahci_kick_engine);
1255
ahci_exec_polled_cmd(struct ata_port * ap,int pmp,struct ata_taskfile * tf,int is_cmd,u16 flags,unsigned long timeout_msec)1256 static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp,
1257 struct ata_taskfile *tf, int is_cmd, u16 flags,
1258 unsigned long timeout_msec)
1259 {
1260 const u32 cmd_fis_len = 5; /* five dwords */
1261 struct ahci_port_priv *pp = ap->private_data;
1262 void __iomem *port_mmio = ahci_port_base(ap);
1263 u8 *fis = pp->cmd_tbl;
1264 u32 tmp;
1265
1266 /* prep the command */
1267 ata_tf_to_fis(tf, pmp, is_cmd, fis);
1268 ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12));
1269
1270 /* issue & wait */
1271 writel(1, port_mmio + PORT_CMD_ISSUE);
1272
1273 if (timeout_msec) {
1274 tmp = ata_wait_register(ap, port_mmio + PORT_CMD_ISSUE,
1275 0x1, 0x1, 1, timeout_msec);
1276 if (tmp & 0x1) {
1277 ahci_kick_engine(ap);
1278 return -EBUSY;
1279 }
1280 } else
1281 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1282
1283 return 0;
1284 }
1285
ahci_do_softreset(struct ata_link * link,unsigned int * class,int pmp,unsigned long deadline,int (* check_ready)(struct ata_link * link))1286 int ahci_do_softreset(struct ata_link *link, unsigned int *class,
1287 int pmp, unsigned long deadline,
1288 int (*check_ready)(struct ata_link *link))
1289 {
1290 struct ata_port *ap = link->ap;
1291 struct ahci_host_priv *hpriv = ap->host->private_data;
1292 struct ahci_port_priv *pp = ap->private_data;
1293 const char *reason = NULL;
1294 unsigned long now, msecs;
1295 struct ata_taskfile tf;
1296 bool fbs_disabled = false;
1297 int rc;
1298
1299 DPRINTK("ENTER\n");
1300
1301 /* prepare for SRST (AHCI-1.1 10.4.1) */
1302 rc = ahci_kick_engine(ap);
1303 if (rc && rc != -EOPNOTSUPP)
1304 ata_link_warn(link, "failed to reset engine (errno=%d)\n", rc);
1305
1306 /*
1307 * According to AHCI-1.2 9.3.9: if FBS is enable, software shall
1308 * clear PxFBS.EN to '0' prior to issuing software reset to devices
1309 * that is attached to port multiplier.
1310 */
1311 if (!ata_is_host_link(link) && pp->fbs_enabled) {
1312 ahci_disable_fbs(ap);
1313 fbs_disabled = true;
1314 }
1315
1316 ata_tf_init(link->device, &tf);
1317
1318 /* issue the first D2H Register FIS */
1319 msecs = 0;
1320 now = jiffies;
1321 if (time_after(deadline, now))
1322 msecs = jiffies_to_msecs(deadline - now);
1323
1324 tf.ctl |= ATA_SRST;
1325 if (ahci_exec_polled_cmd(ap, pmp, &tf, 0,
1326 AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) {
1327 rc = -EIO;
1328 reason = "1st FIS failed";
1329 goto fail;
1330 }
1331
1332 /* spec says at least 5us, but be generous and sleep for 1ms */
1333 ata_msleep(ap, 1);
1334
1335 /* issue the second D2H Register FIS */
1336 tf.ctl &= ~ATA_SRST;
1337 ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0);
1338
1339 /* wait for link to become ready */
1340 rc = ata_wait_after_reset(link, deadline, check_ready);
1341 if (rc == -EBUSY && hpriv->flags & AHCI_HFLAG_SRST_TOUT_IS_OFFLINE) {
1342 /*
1343 * Workaround for cases where link online status can't
1344 * be trusted. Treat device readiness timeout as link
1345 * offline.
1346 */
1347 ata_link_info(link, "device not ready, treating as offline\n");
1348 *class = ATA_DEV_NONE;
1349 } else if (rc) {
1350 /* link occupied, -ENODEV too is an error */
1351 reason = "device not ready";
1352 goto fail;
1353 } else
1354 *class = ahci_dev_classify(ap);
1355
1356 /* re-enable FBS if disabled before */
1357 if (fbs_disabled)
1358 ahci_enable_fbs(ap);
1359
1360 DPRINTK("EXIT, class=%u\n", *class);
1361 return 0;
1362
1363 fail:
1364 ata_link_err(link, "softreset failed (%s)\n", reason);
1365 return rc;
1366 }
1367
ahci_check_ready(struct ata_link * link)1368 int ahci_check_ready(struct ata_link *link)
1369 {
1370 void __iomem *port_mmio = ahci_port_base(link->ap);
1371 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1372
1373 return ata_check_ready(status);
1374 }
1375 EXPORT_SYMBOL_GPL(ahci_check_ready);
1376
ahci_softreset(struct ata_link * link,unsigned int * class,unsigned long deadline)1377 static int ahci_softreset(struct ata_link *link, unsigned int *class,
1378 unsigned long deadline)
1379 {
1380 int pmp = sata_srst_pmp(link);
1381
1382 DPRINTK("ENTER\n");
1383
1384 return ahci_do_softreset(link, class, pmp, deadline, ahci_check_ready);
1385 }
1386 EXPORT_SYMBOL_GPL(ahci_do_softreset);
1387
ahci_bad_pmp_check_ready(struct ata_link * link)1388 static int ahci_bad_pmp_check_ready(struct ata_link *link)
1389 {
1390 void __iomem *port_mmio = ahci_port_base(link->ap);
1391 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1392 u32 irq_status = readl(port_mmio + PORT_IRQ_STAT);
1393
1394 /*
1395 * There is no need to check TFDATA if BAD PMP is found due to HW bug,
1396 * which can save timeout delay.
1397 */
1398 if (irq_status & PORT_IRQ_BAD_PMP)
1399 return -EIO;
1400
1401 return ata_check_ready(status);
1402 }
1403
ahci_pmp_retry_softreset(struct ata_link * link,unsigned int * class,unsigned long deadline)1404 static int ahci_pmp_retry_softreset(struct ata_link *link, unsigned int *class,
1405 unsigned long deadline)
1406 {
1407 struct ata_port *ap = link->ap;
1408 void __iomem *port_mmio = ahci_port_base(ap);
1409 int pmp = sata_srst_pmp(link);
1410 int rc;
1411 u32 irq_sts;
1412
1413 DPRINTK("ENTER\n");
1414
1415 rc = ahci_do_softreset(link, class, pmp, deadline,
1416 ahci_bad_pmp_check_ready);
1417
1418 /*
1419 * Soft reset fails with IPMS set when PMP is enabled but
1420 * SATA HDD/ODD is connected to SATA port, do soft reset
1421 * again to port 0.
1422 */
1423 if (rc == -EIO) {
1424 irq_sts = readl(port_mmio + PORT_IRQ_STAT);
1425 if (irq_sts & PORT_IRQ_BAD_PMP) {
1426 ata_link_warn(link,
1427 "applying PMP SRST workaround "
1428 "and retrying\n");
1429 rc = ahci_do_softreset(link, class, 0, deadline,
1430 ahci_check_ready);
1431 }
1432 }
1433
1434 return rc;
1435 }
1436
ahci_hardreset(struct ata_link * link,unsigned int * class,unsigned long deadline)1437 static int ahci_hardreset(struct ata_link *link, unsigned int *class,
1438 unsigned long deadline)
1439 {
1440 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
1441 struct ata_port *ap = link->ap;
1442 struct ahci_port_priv *pp = ap->private_data;
1443 struct ahci_host_priv *hpriv = ap->host->private_data;
1444 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1445 struct ata_taskfile tf;
1446 bool online;
1447 int rc;
1448
1449 DPRINTK("ENTER\n");
1450
1451 ahci_stop_engine(ap);
1452
1453 /* clear D2H reception area to properly wait for D2H FIS */
1454 ata_tf_init(link->device, &tf);
1455 tf.command = ATA_BUSY;
1456 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
1457
1458 rc = sata_link_hardreset(link, timing, deadline, &online,
1459 ahci_check_ready);
1460
1461 hpriv->start_engine(ap);
1462
1463 if (online)
1464 *class = ahci_dev_classify(ap);
1465
1466 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1467 return rc;
1468 }
1469
ahci_postreset(struct ata_link * link,unsigned int * class)1470 static void ahci_postreset(struct ata_link *link, unsigned int *class)
1471 {
1472 struct ata_port *ap = link->ap;
1473 void __iomem *port_mmio = ahci_port_base(ap);
1474 u32 new_tmp, tmp;
1475
1476 ata_std_postreset(link, class);
1477
1478 /* Make sure port's ATAPI bit is set appropriately */
1479 new_tmp = tmp = readl(port_mmio + PORT_CMD);
1480 if (*class == ATA_DEV_ATAPI)
1481 new_tmp |= PORT_CMD_ATAPI;
1482 else
1483 new_tmp &= ~PORT_CMD_ATAPI;
1484 if (new_tmp != tmp) {
1485 writel(new_tmp, port_mmio + PORT_CMD);
1486 readl(port_mmio + PORT_CMD); /* flush */
1487 }
1488 }
1489
ahci_fill_sg(struct ata_queued_cmd * qc,void * cmd_tbl)1490 static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
1491 {
1492 struct scatterlist *sg;
1493 struct ahci_sg *ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
1494 unsigned int si;
1495
1496 VPRINTK("ENTER\n");
1497
1498 /*
1499 * Next, the S/G list.
1500 */
1501 for_each_sg(qc->sg, sg, qc->n_elem, si) {
1502 dma_addr_t addr = sg_dma_address(sg);
1503 u32 sg_len = sg_dma_len(sg);
1504
1505 ahci_sg[si].addr = cpu_to_le32(addr & 0xffffffff);
1506 ahci_sg[si].addr_hi = cpu_to_le32((addr >> 16) >> 16);
1507 ahci_sg[si].flags_size = cpu_to_le32(sg_len - 1);
1508 }
1509
1510 return si;
1511 }
1512
ahci_pmp_qc_defer(struct ata_queued_cmd * qc)1513 static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc)
1514 {
1515 struct ata_port *ap = qc->ap;
1516 struct ahci_port_priv *pp = ap->private_data;
1517
1518 if (!sata_pmp_attached(ap) || pp->fbs_enabled)
1519 return ata_std_qc_defer(qc);
1520 else
1521 return sata_pmp_qc_defer_cmd_switch(qc);
1522 }
1523
ahci_qc_prep(struct ata_queued_cmd * qc)1524 static void ahci_qc_prep(struct ata_queued_cmd *qc)
1525 {
1526 struct ata_port *ap = qc->ap;
1527 struct ahci_port_priv *pp = ap->private_data;
1528 int is_atapi = ata_is_atapi(qc->tf.protocol);
1529 void *cmd_tbl;
1530 u32 opts;
1531 const u32 cmd_fis_len = 5; /* five dwords */
1532 unsigned int n_elem;
1533
1534 /*
1535 * Fill in command table information. First, the header,
1536 * a SATA Register - Host to Device command FIS.
1537 */
1538 cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ;
1539
1540 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl);
1541 if (is_atapi) {
1542 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
1543 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
1544 }
1545
1546 n_elem = 0;
1547 if (qc->flags & ATA_QCFLAG_DMAMAP)
1548 n_elem = ahci_fill_sg(qc, cmd_tbl);
1549
1550 /*
1551 * Fill in command slot information.
1552 */
1553 opts = cmd_fis_len | n_elem << 16 | (qc->dev->link->pmp << 12);
1554 if (qc->tf.flags & ATA_TFLAG_WRITE)
1555 opts |= AHCI_CMD_WRITE;
1556 if (is_atapi)
1557 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
1558
1559 ahci_fill_cmd_slot(pp, qc->tag, opts);
1560 }
1561
ahci_fbs_dec_intr(struct ata_port * ap)1562 static void ahci_fbs_dec_intr(struct ata_port *ap)
1563 {
1564 struct ahci_port_priv *pp = ap->private_data;
1565 void __iomem *port_mmio = ahci_port_base(ap);
1566 u32 fbs = readl(port_mmio + PORT_FBS);
1567 int retries = 3;
1568
1569 DPRINTK("ENTER\n");
1570 BUG_ON(!pp->fbs_enabled);
1571
1572 /* time to wait for DEC is not specified by AHCI spec,
1573 * add a retry loop for safety.
1574 */
1575 writel(fbs | PORT_FBS_DEC, port_mmio + PORT_FBS);
1576 fbs = readl(port_mmio + PORT_FBS);
1577 while ((fbs & PORT_FBS_DEC) && retries--) {
1578 udelay(1);
1579 fbs = readl(port_mmio + PORT_FBS);
1580 }
1581
1582 if (fbs & PORT_FBS_DEC)
1583 dev_err(ap->host->dev, "failed to clear device error\n");
1584 }
1585
ahci_error_intr(struct ata_port * ap,u32 irq_stat)1586 static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
1587 {
1588 struct ahci_host_priv *hpriv = ap->host->private_data;
1589 struct ahci_port_priv *pp = ap->private_data;
1590 struct ata_eh_info *host_ehi = &ap->link.eh_info;
1591 struct ata_link *link = NULL;
1592 struct ata_queued_cmd *active_qc;
1593 struct ata_eh_info *active_ehi;
1594 bool fbs_need_dec = false;
1595 u32 serror;
1596
1597 /* determine active link with error */
1598 if (pp->fbs_enabled) {
1599 void __iomem *port_mmio = ahci_port_base(ap);
1600 u32 fbs = readl(port_mmio + PORT_FBS);
1601 int pmp = fbs >> PORT_FBS_DWE_OFFSET;
1602
1603 if ((fbs & PORT_FBS_SDE) && (pmp < ap->nr_pmp_links)) {
1604 link = &ap->pmp_link[pmp];
1605 fbs_need_dec = true;
1606 }
1607
1608 } else
1609 ata_for_each_link(link, ap, EDGE)
1610 if (ata_link_active(link))
1611 break;
1612
1613 if (!link)
1614 link = &ap->link;
1615
1616 active_qc = ata_qc_from_tag(ap, link->active_tag);
1617 active_ehi = &link->eh_info;
1618
1619 /* record irq stat */
1620 ata_ehi_clear_desc(host_ehi);
1621 ata_ehi_push_desc(host_ehi, "irq_stat 0x%08x", irq_stat);
1622
1623 /* AHCI needs SError cleared; otherwise, it might lock up */
1624 ahci_scr_read(&ap->link, SCR_ERROR, &serror);
1625 ahci_scr_write(&ap->link, SCR_ERROR, serror);
1626 host_ehi->serror |= serror;
1627
1628 /* some controllers set IRQ_IF_ERR on device errors, ignore it */
1629 if (hpriv->flags & AHCI_HFLAG_IGN_IRQ_IF_ERR)
1630 irq_stat &= ~PORT_IRQ_IF_ERR;
1631
1632 if (irq_stat & PORT_IRQ_TF_ERR) {
1633 /* If qc is active, charge it; otherwise, the active
1634 * link. There's no active qc on NCQ errors. It will
1635 * be determined by EH by reading log page 10h.
1636 */
1637 if (active_qc)
1638 active_qc->err_mask |= AC_ERR_DEV;
1639 else
1640 active_ehi->err_mask |= AC_ERR_DEV;
1641
1642 if (hpriv->flags & AHCI_HFLAG_IGN_SERR_INTERNAL)
1643 host_ehi->serror &= ~SERR_INTERNAL;
1644 }
1645
1646 if (irq_stat & PORT_IRQ_UNK_FIS) {
1647 u32 *unk = pp->rx_fis + RX_FIS_UNK;
1648
1649 active_ehi->err_mask |= AC_ERR_HSM;
1650 active_ehi->action |= ATA_EH_RESET;
1651 ata_ehi_push_desc(active_ehi,
1652 "unknown FIS %08x %08x %08x %08x" ,
1653 unk[0], unk[1], unk[2], unk[3]);
1654 }
1655
1656 if (sata_pmp_attached(ap) && (irq_stat & PORT_IRQ_BAD_PMP)) {
1657 active_ehi->err_mask |= AC_ERR_HSM;
1658 active_ehi->action |= ATA_EH_RESET;
1659 ata_ehi_push_desc(active_ehi, "incorrect PMP");
1660 }
1661
1662 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
1663 host_ehi->err_mask |= AC_ERR_HOST_BUS;
1664 host_ehi->action |= ATA_EH_RESET;
1665 ata_ehi_push_desc(host_ehi, "host bus error");
1666 }
1667
1668 if (irq_stat & PORT_IRQ_IF_ERR) {
1669 if (fbs_need_dec)
1670 active_ehi->err_mask |= AC_ERR_DEV;
1671 else {
1672 host_ehi->err_mask |= AC_ERR_ATA_BUS;
1673 host_ehi->action |= ATA_EH_RESET;
1674 }
1675
1676 ata_ehi_push_desc(host_ehi, "interface fatal error");
1677 }
1678
1679 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
1680 ata_ehi_hotplugged(host_ehi);
1681 ata_ehi_push_desc(host_ehi, "%s",
1682 irq_stat & PORT_IRQ_CONNECT ?
1683 "connection status changed" : "PHY RDY changed");
1684 }
1685
1686 /* okay, let's hand over to EH */
1687
1688 if (irq_stat & PORT_IRQ_FREEZE)
1689 ata_port_freeze(ap);
1690 else if (fbs_need_dec) {
1691 ata_link_abort(link);
1692 ahci_fbs_dec_intr(ap);
1693 } else
1694 ata_port_abort(ap);
1695 }
1696
ahci_handle_port_interrupt(struct ata_port * ap,void __iomem * port_mmio,u32 status)1697 static void ahci_handle_port_interrupt(struct ata_port *ap,
1698 void __iomem *port_mmio, u32 status)
1699 {
1700 struct ata_eh_info *ehi = &ap->link.eh_info;
1701 struct ahci_port_priv *pp = ap->private_data;
1702 struct ahci_host_priv *hpriv = ap->host->private_data;
1703 int resetting = !!(ap->pflags & ATA_PFLAG_RESETTING);
1704 u32 qc_active = 0;
1705 int rc;
1706
1707 /* ignore BAD_PMP while resetting */
1708 if (unlikely(resetting))
1709 status &= ~PORT_IRQ_BAD_PMP;
1710
1711 if (sata_lpm_ignore_phy_events(&ap->link)) {
1712 status &= ~PORT_IRQ_PHYRDY;
1713 ahci_scr_write(&ap->link, SCR_ERROR, SERR_PHYRDY_CHG);
1714 }
1715
1716 if (unlikely(status & PORT_IRQ_ERROR)) {
1717 ahci_error_intr(ap, status);
1718 return;
1719 }
1720
1721 if (status & PORT_IRQ_SDB_FIS) {
1722 /* If SNotification is available, leave notification
1723 * handling to sata_async_notification(). If not,
1724 * emulate it by snooping SDB FIS RX area.
1725 *
1726 * Snooping FIS RX area is probably cheaper than
1727 * poking SNotification but some constrollers which
1728 * implement SNotification, ICH9 for example, don't
1729 * store AN SDB FIS into receive area.
1730 */
1731 if (hpriv->cap & HOST_CAP_SNTF)
1732 sata_async_notification(ap);
1733 else {
1734 /* If the 'N' bit in word 0 of the FIS is set,
1735 * we just received asynchronous notification.
1736 * Tell libata about it.
1737 *
1738 * Lack of SNotification should not appear in
1739 * ahci 1.2, so the workaround is unnecessary
1740 * when FBS is enabled.
1741 */
1742 if (pp->fbs_enabled)
1743 WARN_ON_ONCE(1);
1744 else {
1745 const __le32 *f = pp->rx_fis + RX_FIS_SDB;
1746 u32 f0 = le32_to_cpu(f[0]);
1747 if (f0 & (1 << 15))
1748 sata_async_notification(ap);
1749 }
1750 }
1751 }
1752
1753 /* pp->active_link is not reliable once FBS is enabled, both
1754 * PORT_SCR_ACT and PORT_CMD_ISSUE should be checked because
1755 * NCQ and non-NCQ commands may be in flight at the same time.
1756 */
1757 if (pp->fbs_enabled) {
1758 if (ap->qc_active) {
1759 qc_active = readl(port_mmio + PORT_SCR_ACT);
1760 qc_active |= readl(port_mmio + PORT_CMD_ISSUE);
1761 }
1762 } else {
1763 /* pp->active_link is valid iff any command is in flight */
1764 if (ap->qc_active && pp->active_link->sactive)
1765 qc_active = readl(port_mmio + PORT_SCR_ACT);
1766 else
1767 qc_active = readl(port_mmio + PORT_CMD_ISSUE);
1768 }
1769
1770
1771 rc = ata_qc_complete_multiple(ap, qc_active);
1772
1773 /* while resetting, invalid completions are expected */
1774 if (unlikely(rc < 0 && !resetting)) {
1775 ehi->err_mask |= AC_ERR_HSM;
1776 ehi->action |= ATA_EH_RESET;
1777 ata_port_freeze(ap);
1778 }
1779 }
1780
ahci_port_intr(struct ata_port * ap)1781 static void ahci_port_intr(struct ata_port *ap)
1782 {
1783 void __iomem *port_mmio = ahci_port_base(ap);
1784 u32 status;
1785
1786 status = readl(port_mmio + PORT_IRQ_STAT);
1787 writel(status, port_mmio + PORT_IRQ_STAT);
1788
1789 ahci_handle_port_interrupt(ap, port_mmio, status);
1790 }
1791
ahci_port_thread_fn(int irq,void * dev_instance)1792 static irqreturn_t ahci_port_thread_fn(int irq, void *dev_instance)
1793 {
1794 struct ata_port *ap = dev_instance;
1795 struct ahci_port_priv *pp = ap->private_data;
1796 void __iomem *port_mmio = ahci_port_base(ap);
1797 u32 status;
1798
1799 status = atomic_xchg(&pp->intr_status, 0);
1800 if (!status)
1801 return IRQ_NONE;
1802
1803 spin_lock_bh(ap->lock);
1804 ahci_handle_port_interrupt(ap, port_mmio, status);
1805 spin_unlock_bh(ap->lock);
1806
1807 return IRQ_HANDLED;
1808 }
1809
ahci_multi_irqs_intr(int irq,void * dev_instance)1810 static irqreturn_t ahci_multi_irqs_intr(int irq, void *dev_instance)
1811 {
1812 struct ata_port *ap = dev_instance;
1813 void __iomem *port_mmio = ahci_port_base(ap);
1814 struct ahci_port_priv *pp = ap->private_data;
1815 u32 status;
1816
1817 VPRINTK("ENTER\n");
1818
1819 status = readl(port_mmio + PORT_IRQ_STAT);
1820 writel(status, port_mmio + PORT_IRQ_STAT);
1821
1822 atomic_or(status, &pp->intr_status);
1823
1824 VPRINTK("EXIT\n");
1825
1826 return IRQ_WAKE_THREAD;
1827 }
1828
ahci_single_irq_intr(int irq,void * dev_instance)1829 static irqreturn_t ahci_single_irq_intr(int irq, void *dev_instance)
1830 {
1831 struct ata_host *host = dev_instance;
1832 struct ahci_host_priv *hpriv;
1833 unsigned int i, handled = 0;
1834 void __iomem *mmio;
1835 u32 irq_stat, irq_masked;
1836
1837 VPRINTK("ENTER\n");
1838
1839 hpriv = host->private_data;
1840 mmio = hpriv->mmio;
1841
1842 /* sigh. 0xffffffff is a valid return from h/w */
1843 irq_stat = readl(mmio + HOST_IRQ_STAT);
1844 if (!irq_stat)
1845 return IRQ_NONE;
1846
1847 irq_masked = irq_stat & hpriv->port_map;
1848
1849 spin_lock(&host->lock);
1850
1851 for (i = 0; i < host->n_ports; i++) {
1852 struct ata_port *ap;
1853
1854 if (!(irq_masked & (1 << i)))
1855 continue;
1856
1857 ap = host->ports[i];
1858 if (ap) {
1859 ahci_port_intr(ap);
1860 VPRINTK("port %u\n", i);
1861 } else {
1862 VPRINTK("port %u (no irq)\n", i);
1863 if (ata_ratelimit())
1864 dev_warn(host->dev,
1865 "interrupt on disabled port %u\n", i);
1866 }
1867
1868 handled = 1;
1869 }
1870
1871 /* HOST_IRQ_STAT behaves as level triggered latch meaning that
1872 * it should be cleared after all the port events are cleared;
1873 * otherwise, it will raise a spurious interrupt after each
1874 * valid one. Please read section 10.6.2 of ahci 1.1 for more
1875 * information.
1876 *
1877 * Also, use the unmasked value to clear interrupt as spurious
1878 * pending event on a dummy port might cause screaming IRQ.
1879 */
1880 writel(irq_stat, mmio + HOST_IRQ_STAT);
1881
1882 spin_unlock(&host->lock);
1883
1884 VPRINTK("EXIT\n");
1885
1886 return IRQ_RETVAL(handled);
1887 }
1888
ahci_qc_issue(struct ata_queued_cmd * qc)1889 unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
1890 {
1891 struct ata_port *ap = qc->ap;
1892 void __iomem *port_mmio = ahci_port_base(ap);
1893 struct ahci_port_priv *pp = ap->private_data;
1894
1895 /* Keep track of the currently active link. It will be used
1896 * in completion path to determine whether NCQ phase is in
1897 * progress.
1898 */
1899 pp->active_link = qc->dev->link;
1900
1901 if (qc->tf.protocol == ATA_PROT_NCQ)
1902 writel(1 << qc->tag, port_mmio + PORT_SCR_ACT);
1903
1904 if (pp->fbs_enabled && pp->fbs_last_dev != qc->dev->link->pmp) {
1905 u32 fbs = readl(port_mmio + PORT_FBS);
1906 fbs &= ~(PORT_FBS_DEV_MASK | PORT_FBS_DEC);
1907 fbs |= qc->dev->link->pmp << PORT_FBS_DEV_OFFSET;
1908 writel(fbs, port_mmio + PORT_FBS);
1909 pp->fbs_last_dev = qc->dev->link->pmp;
1910 }
1911
1912 writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE);
1913
1914 ahci_sw_activity(qc->dev->link);
1915
1916 return 0;
1917 }
1918 EXPORT_SYMBOL_GPL(ahci_qc_issue);
1919
ahci_qc_fill_rtf(struct ata_queued_cmd * qc)1920 static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc)
1921 {
1922 struct ahci_port_priv *pp = qc->ap->private_data;
1923 u8 *rx_fis = pp->rx_fis;
1924
1925 if (pp->fbs_enabled)
1926 rx_fis += qc->dev->link->pmp * AHCI_RX_FIS_SZ;
1927
1928 /*
1929 * After a successful execution of an ATA PIO data-in command,
1930 * the device doesn't send D2H Reg FIS to update the TF and
1931 * the host should take TF and E_Status from the preceding PIO
1932 * Setup FIS.
1933 */
1934 if (qc->tf.protocol == ATA_PROT_PIO && qc->dma_dir == DMA_FROM_DEVICE &&
1935 !(qc->flags & ATA_QCFLAG_FAILED)) {
1936 ata_tf_from_fis(rx_fis + RX_FIS_PIO_SETUP, &qc->result_tf);
1937 qc->result_tf.command = (rx_fis + RX_FIS_PIO_SETUP)[15];
1938 } else
1939 ata_tf_from_fis(rx_fis + RX_FIS_D2H_REG, &qc->result_tf);
1940
1941 return true;
1942 }
1943
ahci_freeze(struct ata_port * ap)1944 static void ahci_freeze(struct ata_port *ap)
1945 {
1946 void __iomem *port_mmio = ahci_port_base(ap);
1947
1948 /* turn IRQ off */
1949 writel(0, port_mmio + PORT_IRQ_MASK);
1950 }
1951
ahci_thaw(struct ata_port * ap)1952 static void ahci_thaw(struct ata_port *ap)
1953 {
1954 struct ahci_host_priv *hpriv = ap->host->private_data;
1955 void __iomem *mmio = hpriv->mmio;
1956 void __iomem *port_mmio = ahci_port_base(ap);
1957 u32 tmp;
1958 struct ahci_port_priv *pp = ap->private_data;
1959
1960 /* clear IRQ */
1961 tmp = readl(port_mmio + PORT_IRQ_STAT);
1962 writel(tmp, port_mmio + PORT_IRQ_STAT);
1963 writel(1 << ap->port_no, mmio + HOST_IRQ_STAT);
1964
1965 /* turn IRQ back on */
1966 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
1967 }
1968
ahci_error_handler(struct ata_port * ap)1969 void ahci_error_handler(struct ata_port *ap)
1970 {
1971 struct ahci_host_priv *hpriv = ap->host->private_data;
1972
1973 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
1974 /* restart engine */
1975 ahci_stop_engine(ap);
1976 hpriv->start_engine(ap);
1977 }
1978
1979 sata_pmp_error_handler(ap);
1980
1981 if (!ata_dev_enabled(ap->link.device))
1982 ahci_stop_engine(ap);
1983 }
1984 EXPORT_SYMBOL_GPL(ahci_error_handler);
1985
ahci_post_internal_cmd(struct ata_queued_cmd * qc)1986 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
1987 {
1988 struct ata_port *ap = qc->ap;
1989
1990 /* make DMA engine forget about the failed command */
1991 if (qc->flags & ATA_QCFLAG_FAILED)
1992 ahci_kick_engine(ap);
1993 }
1994
ahci_set_aggressive_devslp(struct ata_port * ap,bool sleep)1995 static void ahci_set_aggressive_devslp(struct ata_port *ap, bool sleep)
1996 {
1997 struct ahci_host_priv *hpriv = ap->host->private_data;
1998 void __iomem *port_mmio = ahci_port_base(ap);
1999 struct ata_device *dev = ap->link.device;
2000 u32 devslp, dm, dito, mdat, deto;
2001 int rc;
2002 unsigned int err_mask;
2003
2004 devslp = readl(port_mmio + PORT_DEVSLP);
2005 if (!(devslp & PORT_DEVSLP_DSP)) {
2006 dev_err(ap->host->dev, "port does not support device sleep\n");
2007 return;
2008 }
2009
2010 /* disable device sleep */
2011 if (!sleep) {
2012 if (devslp & PORT_DEVSLP_ADSE) {
2013 writel(devslp & ~PORT_DEVSLP_ADSE,
2014 port_mmio + PORT_DEVSLP);
2015 err_mask = ata_dev_set_feature(dev,
2016 SETFEATURES_SATA_DISABLE,
2017 SATA_DEVSLP);
2018 if (err_mask && err_mask != AC_ERR_DEV)
2019 ata_dev_warn(dev, "failed to disable DEVSLP\n");
2020 }
2021 return;
2022 }
2023
2024 /* device sleep was already enabled */
2025 if (devslp & PORT_DEVSLP_ADSE)
2026 return;
2027
2028 /* set DITO, MDAT, DETO and enable DevSlp, need to stop engine first */
2029 rc = ahci_stop_engine(ap);
2030 if (rc)
2031 return;
2032
2033 dm = (devslp & PORT_DEVSLP_DM_MASK) >> PORT_DEVSLP_DM_OFFSET;
2034 dito = devslp_idle_timeout / (dm + 1);
2035 if (dito > 0x3ff)
2036 dito = 0x3ff;
2037
2038 /* Use the nominal value 10 ms if the read MDAT is zero,
2039 * the nominal value of DETO is 20 ms.
2040 */
2041 if (dev->devslp_timing[ATA_LOG_DEVSLP_VALID] &
2042 ATA_LOG_DEVSLP_VALID_MASK) {
2043 mdat = dev->devslp_timing[ATA_LOG_DEVSLP_MDAT] &
2044 ATA_LOG_DEVSLP_MDAT_MASK;
2045 if (!mdat)
2046 mdat = 10;
2047 deto = dev->devslp_timing[ATA_LOG_DEVSLP_DETO];
2048 if (!deto)
2049 deto = 20;
2050 } else {
2051 mdat = 10;
2052 deto = 20;
2053 }
2054
2055 devslp |= ((dito << PORT_DEVSLP_DITO_OFFSET) |
2056 (mdat << PORT_DEVSLP_MDAT_OFFSET) |
2057 (deto << PORT_DEVSLP_DETO_OFFSET) |
2058 PORT_DEVSLP_ADSE);
2059 writel(devslp, port_mmio + PORT_DEVSLP);
2060
2061 hpriv->start_engine(ap);
2062
2063 /* enable device sleep feature for the drive */
2064 err_mask = ata_dev_set_feature(dev,
2065 SETFEATURES_SATA_ENABLE,
2066 SATA_DEVSLP);
2067 if (err_mask && err_mask != AC_ERR_DEV)
2068 ata_dev_warn(dev, "failed to enable DEVSLP\n");
2069 }
2070
ahci_enable_fbs(struct ata_port * ap)2071 static void ahci_enable_fbs(struct ata_port *ap)
2072 {
2073 struct ahci_host_priv *hpriv = ap->host->private_data;
2074 struct ahci_port_priv *pp = ap->private_data;
2075 void __iomem *port_mmio = ahci_port_base(ap);
2076 u32 fbs;
2077 int rc;
2078
2079 if (!pp->fbs_supported)
2080 return;
2081
2082 fbs = readl(port_mmio + PORT_FBS);
2083 if (fbs & PORT_FBS_EN) {
2084 pp->fbs_enabled = true;
2085 pp->fbs_last_dev = -1; /* initialization */
2086 return;
2087 }
2088
2089 rc = ahci_stop_engine(ap);
2090 if (rc)
2091 return;
2092
2093 writel(fbs | PORT_FBS_EN, port_mmio + PORT_FBS);
2094 fbs = readl(port_mmio + PORT_FBS);
2095 if (fbs & PORT_FBS_EN) {
2096 dev_info(ap->host->dev, "FBS is enabled\n");
2097 pp->fbs_enabled = true;
2098 pp->fbs_last_dev = -1; /* initialization */
2099 } else
2100 dev_err(ap->host->dev, "Failed to enable FBS\n");
2101
2102 hpriv->start_engine(ap);
2103 }
2104
ahci_disable_fbs(struct ata_port * ap)2105 static void ahci_disable_fbs(struct ata_port *ap)
2106 {
2107 struct ahci_host_priv *hpriv = ap->host->private_data;
2108 struct ahci_port_priv *pp = ap->private_data;
2109 void __iomem *port_mmio = ahci_port_base(ap);
2110 u32 fbs;
2111 int rc;
2112
2113 if (!pp->fbs_supported)
2114 return;
2115
2116 fbs = readl(port_mmio + PORT_FBS);
2117 if ((fbs & PORT_FBS_EN) == 0) {
2118 pp->fbs_enabled = false;
2119 return;
2120 }
2121
2122 rc = ahci_stop_engine(ap);
2123 if (rc)
2124 return;
2125
2126 writel(fbs & ~PORT_FBS_EN, port_mmio + PORT_FBS);
2127 fbs = readl(port_mmio + PORT_FBS);
2128 if (fbs & PORT_FBS_EN)
2129 dev_err(ap->host->dev, "Failed to disable FBS\n");
2130 else {
2131 dev_info(ap->host->dev, "FBS is disabled\n");
2132 pp->fbs_enabled = false;
2133 }
2134
2135 hpriv->start_engine(ap);
2136 }
2137
ahci_pmp_attach(struct ata_port * ap)2138 static void ahci_pmp_attach(struct ata_port *ap)
2139 {
2140 void __iomem *port_mmio = ahci_port_base(ap);
2141 struct ahci_port_priv *pp = ap->private_data;
2142 u32 cmd;
2143
2144 cmd = readl(port_mmio + PORT_CMD);
2145 cmd |= PORT_CMD_PMP;
2146 writel(cmd, port_mmio + PORT_CMD);
2147
2148 ahci_enable_fbs(ap);
2149
2150 pp->intr_mask |= PORT_IRQ_BAD_PMP;
2151
2152 /*
2153 * We must not change the port interrupt mask register if the
2154 * port is marked frozen, the value in pp->intr_mask will be
2155 * restored later when the port is thawed.
2156 *
2157 * Note that during initialization, the port is marked as
2158 * frozen since the irq handler is not yet registered.
2159 */
2160 if (!(ap->pflags & ATA_PFLAG_FROZEN))
2161 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
2162 }
2163
ahci_pmp_detach(struct ata_port * ap)2164 static void ahci_pmp_detach(struct ata_port *ap)
2165 {
2166 void __iomem *port_mmio = ahci_port_base(ap);
2167 struct ahci_port_priv *pp = ap->private_data;
2168 u32 cmd;
2169
2170 ahci_disable_fbs(ap);
2171
2172 cmd = readl(port_mmio + PORT_CMD);
2173 cmd &= ~PORT_CMD_PMP;
2174 writel(cmd, port_mmio + PORT_CMD);
2175
2176 pp->intr_mask &= ~PORT_IRQ_BAD_PMP;
2177
2178 /* see comment above in ahci_pmp_attach() */
2179 if (!(ap->pflags & ATA_PFLAG_FROZEN))
2180 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
2181 }
2182
ahci_port_resume(struct ata_port * ap)2183 int ahci_port_resume(struct ata_port *ap)
2184 {
2185 ahci_power_up(ap);
2186 ahci_start_port(ap);
2187
2188 if (sata_pmp_attached(ap))
2189 ahci_pmp_attach(ap);
2190 else
2191 ahci_pmp_detach(ap);
2192
2193 return 0;
2194 }
2195 EXPORT_SYMBOL_GPL(ahci_port_resume);
2196
2197 #ifdef CONFIG_PM
ahci_port_suspend(struct ata_port * ap,pm_message_t mesg)2198 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
2199 {
2200 const char *emsg = NULL;
2201 int rc;
2202
2203 rc = ahci_deinit_port(ap, &emsg);
2204 if (rc == 0)
2205 ahci_power_down(ap);
2206 else {
2207 ata_port_err(ap, "%s (%d)\n", emsg, rc);
2208 ata_port_freeze(ap);
2209 }
2210
2211 return rc;
2212 }
2213 #endif
2214
ahci_port_start(struct ata_port * ap)2215 static int ahci_port_start(struct ata_port *ap)
2216 {
2217 struct ahci_host_priv *hpriv = ap->host->private_data;
2218 struct device *dev = ap->host->dev;
2219 struct ahci_port_priv *pp;
2220 void *mem;
2221 dma_addr_t mem_dma;
2222 size_t dma_sz, rx_fis_sz;
2223
2224 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
2225 if (!pp)
2226 return -ENOMEM;
2227
2228 if (ap->host->n_ports > 1) {
2229 pp->irq_desc = devm_kzalloc(dev, 8, GFP_KERNEL);
2230 if (!pp->irq_desc) {
2231 devm_kfree(dev, pp);
2232 return -ENOMEM;
2233 }
2234 snprintf(pp->irq_desc, 8,
2235 "%s%d", dev_driver_string(dev), ap->port_no);
2236 }
2237
2238 /* check FBS capability */
2239 if ((hpriv->cap & HOST_CAP_FBS) && sata_pmp_supported(ap)) {
2240 void __iomem *port_mmio = ahci_port_base(ap);
2241 u32 cmd = readl(port_mmio + PORT_CMD);
2242 if (cmd & PORT_CMD_FBSCP)
2243 pp->fbs_supported = true;
2244 else if (hpriv->flags & AHCI_HFLAG_YES_FBS) {
2245 dev_info(dev, "port %d can do FBS, forcing FBSCP\n",
2246 ap->port_no);
2247 pp->fbs_supported = true;
2248 } else
2249 dev_warn(dev, "port %d is not capable of FBS\n",
2250 ap->port_no);
2251 }
2252
2253 if (pp->fbs_supported) {
2254 dma_sz = AHCI_PORT_PRIV_FBS_DMA_SZ;
2255 rx_fis_sz = AHCI_RX_FIS_SZ * 16;
2256 } else {
2257 dma_sz = AHCI_PORT_PRIV_DMA_SZ;
2258 rx_fis_sz = AHCI_RX_FIS_SZ;
2259 }
2260
2261 mem = dmam_alloc_coherent(dev, dma_sz, &mem_dma, GFP_KERNEL);
2262 if (!mem)
2263 return -ENOMEM;
2264 memset(mem, 0, dma_sz);
2265
2266 /*
2267 * First item in chunk of DMA memory: 32-slot command table,
2268 * 32 bytes each in size
2269 */
2270 pp->cmd_slot = mem;
2271 pp->cmd_slot_dma = mem_dma;
2272
2273 mem += AHCI_CMD_SLOT_SZ;
2274 mem_dma += AHCI_CMD_SLOT_SZ;
2275
2276 /*
2277 * Second item: Received-FIS area
2278 */
2279 pp->rx_fis = mem;
2280 pp->rx_fis_dma = mem_dma;
2281
2282 mem += rx_fis_sz;
2283 mem_dma += rx_fis_sz;
2284
2285 /*
2286 * Third item: data area for storing a single command
2287 * and its scatter-gather table
2288 */
2289 pp->cmd_tbl = mem;
2290 pp->cmd_tbl_dma = mem_dma;
2291
2292 /*
2293 * Save off initial list of interrupts to be enabled.
2294 * This could be changed later
2295 */
2296 pp->intr_mask = DEF_PORT_IRQ;
2297
2298 /*
2299 * Switch to per-port locking in case each port has its own MSI vector.
2300 */
2301 if ((hpriv->flags & AHCI_HFLAG_MULTI_MSI)) {
2302 spin_lock_init(&pp->lock);
2303 ap->lock = &pp->lock;
2304 }
2305
2306 ap->private_data = pp;
2307
2308 /* engage engines, captain */
2309 return ahci_port_resume(ap);
2310 }
2311
ahci_port_stop(struct ata_port * ap)2312 static void ahci_port_stop(struct ata_port *ap)
2313 {
2314 const char *emsg = NULL;
2315 int rc;
2316
2317 /* de-initialize port */
2318 rc = ahci_deinit_port(ap, &emsg);
2319 if (rc)
2320 ata_port_warn(ap, "%s (%d)\n", emsg, rc);
2321 }
2322
ahci_print_info(struct ata_host * host,const char * scc_s)2323 void ahci_print_info(struct ata_host *host, const char *scc_s)
2324 {
2325 struct ahci_host_priv *hpriv = host->private_data;
2326 void __iomem *mmio = hpriv->mmio;
2327 u32 vers, cap, cap2, impl, speed;
2328 const char *speed_s;
2329
2330 vers = readl(mmio + HOST_VERSION);
2331 cap = hpriv->cap;
2332 cap2 = hpriv->cap2;
2333 impl = hpriv->port_map;
2334
2335 speed = (cap >> 20) & 0xf;
2336 if (speed == 1)
2337 speed_s = "1.5";
2338 else if (speed == 2)
2339 speed_s = "3";
2340 else if (speed == 3)
2341 speed_s = "6";
2342 else
2343 speed_s = "?";
2344
2345 dev_info(host->dev,
2346 "AHCI %02x%02x.%02x%02x "
2347 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
2348 ,
2349
2350 (vers >> 24) & 0xff,
2351 (vers >> 16) & 0xff,
2352 (vers >> 8) & 0xff,
2353 vers & 0xff,
2354
2355 ((cap >> 8) & 0x1f) + 1,
2356 (cap & 0x1f) + 1,
2357 speed_s,
2358 impl,
2359 scc_s);
2360
2361 dev_info(host->dev,
2362 "flags: "
2363 "%s%s%s%s%s%s%s"
2364 "%s%s%s%s%s%s%s"
2365 "%s%s%s%s%s%s%s"
2366 "%s%s\n"
2367 ,
2368
2369 cap & HOST_CAP_64 ? "64bit " : "",
2370 cap & HOST_CAP_NCQ ? "ncq " : "",
2371 cap & HOST_CAP_SNTF ? "sntf " : "",
2372 cap & HOST_CAP_MPS ? "ilck " : "",
2373 cap & HOST_CAP_SSS ? "stag " : "",
2374 cap & HOST_CAP_ALPM ? "pm " : "",
2375 cap & HOST_CAP_LED ? "led " : "",
2376 cap & HOST_CAP_CLO ? "clo " : "",
2377 cap & HOST_CAP_ONLY ? "only " : "",
2378 cap & HOST_CAP_PMP ? "pmp " : "",
2379 cap & HOST_CAP_FBS ? "fbs " : "",
2380 cap & HOST_CAP_PIO_MULTI ? "pio " : "",
2381 cap & HOST_CAP_SSC ? "slum " : "",
2382 cap & HOST_CAP_PART ? "part " : "",
2383 cap & HOST_CAP_CCC ? "ccc " : "",
2384 cap & HOST_CAP_EMS ? "ems " : "",
2385 cap & HOST_CAP_SXS ? "sxs " : "",
2386 cap2 & HOST_CAP2_DESO ? "deso " : "",
2387 cap2 & HOST_CAP2_SADM ? "sadm " : "",
2388 cap2 & HOST_CAP2_SDS ? "sds " : "",
2389 cap2 & HOST_CAP2_APST ? "apst " : "",
2390 cap2 & HOST_CAP2_NVMHCI ? "nvmp " : "",
2391 cap2 & HOST_CAP2_BOH ? "boh " : ""
2392 );
2393 }
2394 EXPORT_SYMBOL_GPL(ahci_print_info);
2395
ahci_set_em_messages(struct ahci_host_priv * hpriv,struct ata_port_info * pi)2396 void ahci_set_em_messages(struct ahci_host_priv *hpriv,
2397 struct ata_port_info *pi)
2398 {
2399 u8 messages;
2400 void __iomem *mmio = hpriv->mmio;
2401 u32 em_loc = readl(mmio + HOST_EM_LOC);
2402 u32 em_ctl = readl(mmio + HOST_EM_CTL);
2403
2404 if (!ahci_em_messages || !(hpriv->cap & HOST_CAP_EMS))
2405 return;
2406
2407 messages = (em_ctl & EM_CTRL_MSG_TYPE) >> 16;
2408
2409 if (messages) {
2410 /* store em_loc */
2411 hpriv->em_loc = ((em_loc >> 16) * 4);
2412 hpriv->em_buf_sz = ((em_loc & 0xff) * 4);
2413 hpriv->em_msg_type = messages;
2414 pi->flags |= ATA_FLAG_EM;
2415 if (!(em_ctl & EM_CTL_ALHD))
2416 pi->flags |= ATA_FLAG_SW_ACTIVITY;
2417 }
2418 }
2419 EXPORT_SYMBOL_GPL(ahci_set_em_messages);
2420
ahci_host_activate_multi_irqs(struct ata_host * host,int irq,struct scsi_host_template * sht)2421 static int ahci_host_activate_multi_irqs(struct ata_host *host, int irq,
2422 struct scsi_host_template *sht)
2423 {
2424 int i, rc;
2425
2426 rc = ata_host_start(host);
2427 if (rc)
2428 return rc;
2429
2430 for (i = 0; i < host->n_ports; i++) {
2431 struct ahci_port_priv *pp = host->ports[i]->private_data;
2432
2433 /* Do not receive interrupts sent by dummy ports */
2434 if (!pp) {
2435 disable_irq(irq + i);
2436 continue;
2437 }
2438
2439 rc = devm_request_threaded_irq(host->dev, irq + i,
2440 ahci_multi_irqs_intr,
2441 ahci_port_thread_fn, IRQF_SHARED,
2442 pp->irq_desc, host->ports[i]);
2443 if (rc)
2444 goto out_free_irqs;
2445 }
2446
2447 for (i = 0; i < host->n_ports; i++)
2448 ata_port_desc(host->ports[i], "irq %d", irq + i);
2449
2450 rc = ata_host_register(host, sht);
2451 if (rc)
2452 goto out_free_all_irqs;
2453
2454 return 0;
2455
2456 out_free_all_irqs:
2457 i = host->n_ports;
2458 out_free_irqs:
2459 for (i--; i >= 0; i--)
2460 devm_free_irq(host->dev, irq + i, host->ports[i]);
2461
2462 return rc;
2463 }
2464
2465 /**
2466 * ahci_host_activate - start AHCI host, request IRQs and register it
2467 * @host: target ATA host
2468 * @irq: base IRQ number to request
2469 * @sht: scsi_host_template to use when registering the host
2470 *
2471 * Similar to ata_host_activate, but requests IRQs according to AHCI-1.1
2472 * when multiple MSIs were allocated. That is one MSI per port, starting
2473 * from @irq.
2474 *
2475 * LOCKING:
2476 * Inherited from calling layer (may sleep).
2477 *
2478 * RETURNS:
2479 * 0 on success, -errno otherwise.
2480 */
ahci_host_activate(struct ata_host * host,int irq,struct scsi_host_template * sht)2481 int ahci_host_activate(struct ata_host *host, int irq,
2482 struct scsi_host_template *sht)
2483 {
2484 struct ahci_host_priv *hpriv = host->private_data;
2485 int rc;
2486
2487 if (hpriv->flags & AHCI_HFLAG_MULTI_MSI)
2488 rc = ahci_host_activate_multi_irqs(host, irq, sht);
2489 else
2490 rc = ata_host_activate(host, irq, ahci_single_irq_intr,
2491 IRQF_SHARED, sht);
2492 return rc;
2493 }
2494 EXPORT_SYMBOL_GPL(ahci_host_activate);
2495
2496 MODULE_AUTHOR("Jeff Garzik");
2497 MODULE_DESCRIPTION("Common AHCI SATA low-level routines");
2498 MODULE_LICENSE("GPL");
2499