1 /*
2 * Address map functions for Marvell EBU SoCs (Kirkwood, Armada
3 * 370/XP, Dove, Orion5x and MV78xx0)
4 *
5 * This file is licensed under the terms of the GNU General Public
6 * License version 2. This program is licensed "as is" without any
7 * warranty of any kind, whether express or implied.
8 *
9 * The Marvell EBU SoCs have a configurable physical address space:
10 * the physical address at which certain devices (PCIe, NOR, NAND,
11 * etc.) sit can be configured. The configuration takes place through
12 * two sets of registers:
13 *
14 * - One to configure the access of the CPU to the devices. Depending
15 * on the families, there are between 8 and 20 configurable windows,
16 * each can be use to create a physical memory window that maps to a
17 * specific device. Devices are identified by a tuple (target,
18 * attribute).
19 *
20 * - One to configure the access to the CPU to the SDRAM. There are
21 * either 2 (for Dove) or 4 (for other families) windows to map the
22 * SDRAM into the physical address space.
23 *
24 * This driver:
25 *
26 * - Reads out the SDRAM address decoding windows at initialization
27 * time, and fills the mvebu_mbus_dram_info structure with these
28 * informations. The exported function mv_mbus_dram_info() allow
29 * device drivers to get those informations related to the SDRAM
30 * address decoding windows. This is because devices also have their
31 * own windows (configured through registers that are part of each
32 * device register space), and therefore the drivers for Marvell
33 * devices have to configure those device -> SDRAM windows to ensure
34 * that DMA works properly.
35 *
36 * - Provides an API for platform code or device drivers to
37 * dynamically add or remove address decoding windows for the CPU ->
38 * device accesses. This API is mvebu_mbus_add_window_by_id(),
39 * mvebu_mbus_add_window_remap_by_id() and
40 * mvebu_mbus_del_window().
41 *
42 * - Provides a debugfs interface in /sys/kernel/debug/mvebu-mbus/ to
43 * see the list of CPU -> SDRAM windows and their configuration
44 * (file 'sdram') and the list of CPU -> devices windows and their
45 * configuration (file 'devices').
46 */
47
48 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
49
50 #include <linux/kernel.h>
51 #include <linux/module.h>
52 #include <linux/init.h>
53 #include <linux/mbus.h>
54 #include <linux/io.h>
55 #include <linux/ioport.h>
56 #include <linux/of.h>
57 #include <linux/of_address.h>
58 #include <linux/debugfs.h>
59 #include <linux/log2.h>
60
61 /*
62 * DDR target is the same on all platforms.
63 */
64 #define TARGET_DDR 0
65
66 /*
67 * CPU Address Decode Windows registers
68 */
69 #define WIN_CTRL_OFF 0x0000
70 #define WIN_CTRL_ENABLE BIT(0)
71 #define WIN_CTRL_TGT_MASK 0xf0
72 #define WIN_CTRL_TGT_SHIFT 4
73 #define WIN_CTRL_ATTR_MASK 0xff00
74 #define WIN_CTRL_ATTR_SHIFT 8
75 #define WIN_CTRL_SIZE_MASK 0xffff0000
76 #define WIN_CTRL_SIZE_SHIFT 16
77 #define WIN_BASE_OFF 0x0004
78 #define WIN_BASE_LOW 0xffff0000
79 #define WIN_BASE_HIGH 0xf
80 #define WIN_REMAP_LO_OFF 0x0008
81 #define WIN_REMAP_LOW 0xffff0000
82 #define WIN_REMAP_HI_OFF 0x000c
83
84 #define ATTR_HW_COHERENCY (0x1 << 4)
85
86 #define DDR_BASE_CS_OFF(n) (0x0000 + ((n) << 3))
87 #define DDR_BASE_CS_HIGH_MASK 0xf
88 #define DDR_BASE_CS_LOW_MASK 0xff000000
89 #define DDR_SIZE_CS_OFF(n) (0x0004 + ((n) << 3))
90 #define DDR_SIZE_ENABLED BIT(0)
91 #define DDR_SIZE_CS_MASK 0x1c
92 #define DDR_SIZE_CS_SHIFT 2
93 #define DDR_SIZE_MASK 0xff000000
94
95 #define DOVE_DDR_BASE_CS_OFF(n) ((n) << 4)
96
97 struct mvebu_mbus_state;
98
99 struct mvebu_mbus_soc_data {
100 unsigned int num_wins;
101 unsigned int num_remappable_wins;
102 unsigned int (*win_cfg_offset)(const int win);
103 void (*setup_cpu_target)(struct mvebu_mbus_state *s);
104 int (*show_cpu_target)(struct mvebu_mbus_state *s,
105 struct seq_file *seq, void *v);
106 };
107
108 struct mvebu_mbus_state {
109 void __iomem *mbuswins_base;
110 void __iomem *sdramwins_base;
111 struct dentry *debugfs_root;
112 struct dentry *debugfs_sdram;
113 struct dentry *debugfs_devs;
114 struct resource pcie_mem_aperture;
115 struct resource pcie_io_aperture;
116 const struct mvebu_mbus_soc_data *soc;
117 int hw_io_coherency;
118 };
119
120 static struct mvebu_mbus_state mbus_state;
121
122 static struct mbus_dram_target_info mvebu_mbus_dram_info;
mv_mbus_dram_info(void)123 const struct mbus_dram_target_info *mv_mbus_dram_info(void)
124 {
125 return &mvebu_mbus_dram_info;
126 }
127 EXPORT_SYMBOL_GPL(mv_mbus_dram_info);
128
129 /*
130 * Functions to manipulate the address decoding windows
131 */
132
mvebu_mbus_read_window(struct mvebu_mbus_state * mbus,int win,int * enabled,u64 * base,u32 * size,u8 * target,u8 * attr,u64 * remap)133 static void mvebu_mbus_read_window(struct mvebu_mbus_state *mbus,
134 int win, int *enabled, u64 *base,
135 u32 *size, u8 *target, u8 *attr,
136 u64 *remap)
137 {
138 void __iomem *addr = mbus->mbuswins_base +
139 mbus->soc->win_cfg_offset(win);
140 u32 basereg = readl(addr + WIN_BASE_OFF);
141 u32 ctrlreg = readl(addr + WIN_CTRL_OFF);
142
143 if (!(ctrlreg & WIN_CTRL_ENABLE)) {
144 *enabled = 0;
145 return;
146 }
147
148 *enabled = 1;
149 *base = ((u64)basereg & WIN_BASE_HIGH) << 32;
150 *base |= (basereg & WIN_BASE_LOW);
151 *size = (ctrlreg | ~WIN_CTRL_SIZE_MASK) + 1;
152
153 if (target)
154 *target = (ctrlreg & WIN_CTRL_TGT_MASK) >> WIN_CTRL_TGT_SHIFT;
155
156 if (attr)
157 *attr = (ctrlreg & WIN_CTRL_ATTR_MASK) >> WIN_CTRL_ATTR_SHIFT;
158
159 if (remap) {
160 if (win < mbus->soc->num_remappable_wins) {
161 u32 remap_low = readl(addr + WIN_REMAP_LO_OFF);
162 u32 remap_hi = readl(addr + WIN_REMAP_HI_OFF);
163 *remap = ((u64)remap_hi << 32) | remap_low;
164 } else
165 *remap = 0;
166 }
167 }
168
mvebu_mbus_disable_window(struct mvebu_mbus_state * mbus,int win)169 static void mvebu_mbus_disable_window(struct mvebu_mbus_state *mbus,
170 int win)
171 {
172 void __iomem *addr;
173
174 addr = mbus->mbuswins_base + mbus->soc->win_cfg_offset(win);
175
176 writel(0, addr + WIN_BASE_OFF);
177 writel(0, addr + WIN_CTRL_OFF);
178 if (win < mbus->soc->num_remappable_wins) {
179 writel(0, addr + WIN_REMAP_LO_OFF);
180 writel(0, addr + WIN_REMAP_HI_OFF);
181 }
182 }
183
184 /* Checks whether the given window number is available */
185
186 /* On Armada XP, 375 and 38x the MBus window 13 has the remap
187 * capability, like windows 0 to 7. However, the mvebu-mbus driver
188 * isn't currently taking into account this special case, which means
189 * that when window 13 is actually used, the remap registers are left
190 * to 0, making the device using this MBus window unavailable. The
191 * quick fix for stable is to not use window 13. A follow up patch
192 * will correctly handle this window.
193 */
mvebu_mbus_window_is_free(struct mvebu_mbus_state * mbus,const int win)194 static int mvebu_mbus_window_is_free(struct mvebu_mbus_state *mbus,
195 const int win)
196 {
197 void __iomem *addr = mbus->mbuswins_base +
198 mbus->soc->win_cfg_offset(win);
199 u32 ctrl = readl(addr + WIN_CTRL_OFF);
200
201 if (win == 13)
202 return false;
203
204 return !(ctrl & WIN_CTRL_ENABLE);
205 }
206
207 /*
208 * Checks whether the given (base, base+size) area doesn't overlap an
209 * existing region
210 */
mvebu_mbus_window_conflicts(struct mvebu_mbus_state * mbus,phys_addr_t base,size_t size,u8 target,u8 attr)211 static int mvebu_mbus_window_conflicts(struct mvebu_mbus_state *mbus,
212 phys_addr_t base, size_t size,
213 u8 target, u8 attr)
214 {
215 u64 end = (u64)base + size;
216 int win;
217
218 for (win = 0; win < mbus->soc->num_wins; win++) {
219 u64 wbase, wend;
220 u32 wsize;
221 u8 wtarget, wattr;
222 int enabled;
223
224 mvebu_mbus_read_window(mbus, win,
225 &enabled, &wbase, &wsize,
226 &wtarget, &wattr, NULL);
227
228 if (!enabled)
229 continue;
230
231 wend = wbase + wsize;
232
233 /*
234 * Check if the current window overlaps with the
235 * proposed physical range
236 */
237 if ((u64)base < wend && end > wbase)
238 return 0;
239 }
240
241 return 1;
242 }
243
mvebu_mbus_find_window(struct mvebu_mbus_state * mbus,phys_addr_t base,size_t size)244 static int mvebu_mbus_find_window(struct mvebu_mbus_state *mbus,
245 phys_addr_t base, size_t size)
246 {
247 int win;
248
249 for (win = 0; win < mbus->soc->num_wins; win++) {
250 u64 wbase;
251 u32 wsize;
252 int enabled;
253
254 mvebu_mbus_read_window(mbus, win,
255 &enabled, &wbase, &wsize,
256 NULL, NULL, NULL);
257
258 if (!enabled)
259 continue;
260
261 if (base == wbase && size == wsize)
262 return win;
263 }
264
265 return -ENODEV;
266 }
267
mvebu_mbus_setup_window(struct mvebu_mbus_state * mbus,int win,phys_addr_t base,size_t size,phys_addr_t remap,u8 target,u8 attr)268 static int mvebu_mbus_setup_window(struct mvebu_mbus_state *mbus,
269 int win, phys_addr_t base, size_t size,
270 phys_addr_t remap, u8 target,
271 u8 attr)
272 {
273 void __iomem *addr = mbus->mbuswins_base +
274 mbus->soc->win_cfg_offset(win);
275 u32 ctrl, remap_addr;
276
277 if (!is_power_of_2(size)) {
278 WARN(true, "Invalid MBus window size: 0x%zx\n", size);
279 return -EINVAL;
280 }
281
282 if ((base & (phys_addr_t)(size - 1)) != 0) {
283 WARN(true, "Invalid MBus base/size: %pa len 0x%zx\n", &base,
284 size);
285 return -EINVAL;
286 }
287
288 ctrl = ((size - 1) & WIN_CTRL_SIZE_MASK) |
289 (attr << WIN_CTRL_ATTR_SHIFT) |
290 (target << WIN_CTRL_TGT_SHIFT) |
291 WIN_CTRL_ENABLE;
292
293 writel(base & WIN_BASE_LOW, addr + WIN_BASE_OFF);
294 writel(ctrl, addr + WIN_CTRL_OFF);
295 if (win < mbus->soc->num_remappable_wins) {
296 if (remap == MVEBU_MBUS_NO_REMAP)
297 remap_addr = base;
298 else
299 remap_addr = remap;
300 writel(remap_addr & WIN_REMAP_LOW, addr + WIN_REMAP_LO_OFF);
301 writel(0, addr + WIN_REMAP_HI_OFF);
302 }
303
304 return 0;
305 }
306
mvebu_mbus_alloc_window(struct mvebu_mbus_state * mbus,phys_addr_t base,size_t size,phys_addr_t remap,u8 target,u8 attr)307 static int mvebu_mbus_alloc_window(struct mvebu_mbus_state *mbus,
308 phys_addr_t base, size_t size,
309 phys_addr_t remap, u8 target,
310 u8 attr)
311 {
312 int win;
313
314 if (remap == MVEBU_MBUS_NO_REMAP) {
315 for (win = mbus->soc->num_remappable_wins;
316 win < mbus->soc->num_wins; win++)
317 if (mvebu_mbus_window_is_free(mbus, win))
318 return mvebu_mbus_setup_window(mbus, win, base,
319 size, remap,
320 target, attr);
321 }
322
323
324 for (win = 0; win < mbus->soc->num_wins; win++)
325 if (mvebu_mbus_window_is_free(mbus, win))
326 return mvebu_mbus_setup_window(mbus, win, base, size,
327 remap, target, attr);
328
329 return -ENOMEM;
330 }
331
332 /*
333 * Debugfs debugging
334 */
335
336 /* Common function used for Dove, Kirkwood, Armada 370/XP and Orion 5x */
mvebu_sdram_debug_show_orion(struct mvebu_mbus_state * mbus,struct seq_file * seq,void * v)337 static int mvebu_sdram_debug_show_orion(struct mvebu_mbus_state *mbus,
338 struct seq_file *seq, void *v)
339 {
340 int i;
341
342 for (i = 0; i < 4; i++) {
343 u32 basereg = readl(mbus->sdramwins_base + DDR_BASE_CS_OFF(i));
344 u32 sizereg = readl(mbus->sdramwins_base + DDR_SIZE_CS_OFF(i));
345 u64 base;
346 u32 size;
347
348 if (!(sizereg & DDR_SIZE_ENABLED)) {
349 seq_printf(seq, "[%d] disabled\n", i);
350 continue;
351 }
352
353 base = ((u64)basereg & DDR_BASE_CS_HIGH_MASK) << 32;
354 base |= basereg & DDR_BASE_CS_LOW_MASK;
355 size = (sizereg | ~DDR_SIZE_MASK);
356
357 seq_printf(seq, "[%d] %016llx - %016llx : cs%d\n",
358 i, (unsigned long long)base,
359 (unsigned long long)base + size + 1,
360 (sizereg & DDR_SIZE_CS_MASK) >> DDR_SIZE_CS_SHIFT);
361 }
362
363 return 0;
364 }
365
366 /* Special function for Dove */
mvebu_sdram_debug_show_dove(struct mvebu_mbus_state * mbus,struct seq_file * seq,void * v)367 static int mvebu_sdram_debug_show_dove(struct mvebu_mbus_state *mbus,
368 struct seq_file *seq, void *v)
369 {
370 int i;
371
372 for (i = 0; i < 2; i++) {
373 u32 map = readl(mbus->sdramwins_base + DOVE_DDR_BASE_CS_OFF(i));
374 u64 base;
375 u32 size;
376
377 if (!(map & 1)) {
378 seq_printf(seq, "[%d] disabled\n", i);
379 continue;
380 }
381
382 base = map & 0xff800000;
383 size = 0x100000 << (((map & 0x000f0000) >> 16) - 4);
384
385 seq_printf(seq, "[%d] %016llx - %016llx : cs%d\n",
386 i, (unsigned long long)base,
387 (unsigned long long)base + size, i);
388 }
389
390 return 0;
391 }
392
mvebu_sdram_debug_show(struct seq_file * seq,void * v)393 static int mvebu_sdram_debug_show(struct seq_file *seq, void *v)
394 {
395 struct mvebu_mbus_state *mbus = &mbus_state;
396 return mbus->soc->show_cpu_target(mbus, seq, v);
397 }
398
mvebu_sdram_debug_open(struct inode * inode,struct file * file)399 static int mvebu_sdram_debug_open(struct inode *inode, struct file *file)
400 {
401 return single_open(file, mvebu_sdram_debug_show, inode->i_private);
402 }
403
404 static const struct file_operations mvebu_sdram_debug_fops = {
405 .open = mvebu_sdram_debug_open,
406 .read = seq_read,
407 .llseek = seq_lseek,
408 .release = single_release,
409 };
410
mvebu_devs_debug_show(struct seq_file * seq,void * v)411 static int mvebu_devs_debug_show(struct seq_file *seq, void *v)
412 {
413 struct mvebu_mbus_state *mbus = &mbus_state;
414 int win;
415
416 for (win = 0; win < mbus->soc->num_wins; win++) {
417 u64 wbase, wremap;
418 u32 wsize;
419 u8 wtarget, wattr;
420 int enabled;
421
422 mvebu_mbus_read_window(mbus, win,
423 &enabled, &wbase, &wsize,
424 &wtarget, &wattr, &wremap);
425
426 if (!enabled) {
427 seq_printf(seq, "[%02d] disabled\n", win);
428 continue;
429 }
430
431 seq_printf(seq, "[%02d] %016llx - %016llx : %04x:%04x",
432 win, (unsigned long long)wbase,
433 (unsigned long long)(wbase + wsize), wtarget, wattr);
434
435 if (!is_power_of_2(wsize) ||
436 ((wbase & (u64)(wsize - 1)) != 0))
437 seq_puts(seq, " (Invalid base/size!!)");
438
439 if (win < mbus->soc->num_remappable_wins) {
440 seq_printf(seq, " (remap %016llx)\n",
441 (unsigned long long)wremap);
442 } else
443 seq_printf(seq, "\n");
444 }
445
446 return 0;
447 }
448
mvebu_devs_debug_open(struct inode * inode,struct file * file)449 static int mvebu_devs_debug_open(struct inode *inode, struct file *file)
450 {
451 return single_open(file, mvebu_devs_debug_show, inode->i_private);
452 }
453
454 static const struct file_operations mvebu_devs_debug_fops = {
455 .open = mvebu_devs_debug_open,
456 .read = seq_read,
457 .llseek = seq_lseek,
458 .release = single_release,
459 };
460
461 /*
462 * SoC-specific functions and definitions
463 */
464
orion_mbus_win_offset(int win)465 static unsigned int orion_mbus_win_offset(int win)
466 {
467 return win << 4;
468 }
469
armada_370_xp_mbus_win_offset(int win)470 static unsigned int armada_370_xp_mbus_win_offset(int win)
471 {
472 /* The register layout is a bit annoying and the below code
473 * tries to cope with it.
474 * - At offset 0x0, there are the registers for the first 8
475 * windows, with 4 registers of 32 bits per window (ctrl,
476 * base, remap low, remap high)
477 * - Then at offset 0x80, there is a hole of 0x10 bytes for
478 * the internal registers base address and internal units
479 * sync barrier register.
480 * - Then at offset 0x90, there the registers for 12
481 * windows, with only 2 registers of 32 bits per window
482 * (ctrl, base).
483 */
484 if (win < 8)
485 return win << 4;
486 else
487 return 0x90 + ((win - 8) << 3);
488 }
489
mv78xx0_mbus_win_offset(int win)490 static unsigned int mv78xx0_mbus_win_offset(int win)
491 {
492 if (win < 8)
493 return win << 4;
494 else
495 return 0x900 + ((win - 8) << 4);
496 }
497
498 static void __init
mvebu_mbus_default_setup_cpu_target(struct mvebu_mbus_state * mbus)499 mvebu_mbus_default_setup_cpu_target(struct mvebu_mbus_state *mbus)
500 {
501 int i;
502 int cs;
503
504 mvebu_mbus_dram_info.mbus_dram_target_id = TARGET_DDR;
505
506 for (i = 0, cs = 0; i < 4; i++) {
507 u32 base = readl(mbus->sdramwins_base + DDR_BASE_CS_OFF(i));
508 u32 size = readl(mbus->sdramwins_base + DDR_SIZE_CS_OFF(i));
509
510 /*
511 * We only take care of entries for which the chip
512 * select is enabled, and that don't have high base
513 * address bits set (devices can only access the first
514 * 32 bits of the memory).
515 */
516 if ((size & DDR_SIZE_ENABLED) &&
517 !(base & DDR_BASE_CS_HIGH_MASK)) {
518 struct mbus_dram_window *w;
519
520 w = &mvebu_mbus_dram_info.cs[cs++];
521 w->cs_index = i;
522 w->mbus_attr = 0xf & ~(1 << i);
523 if (mbus->hw_io_coherency)
524 w->mbus_attr |= ATTR_HW_COHERENCY;
525 w->base = base & DDR_BASE_CS_LOW_MASK;
526 w->size = (u64)(size | ~DDR_SIZE_MASK) + 1;
527 }
528 }
529 mvebu_mbus_dram_info.num_cs = cs;
530 }
531
532 static void __init
mvebu_mbus_dove_setup_cpu_target(struct mvebu_mbus_state * mbus)533 mvebu_mbus_dove_setup_cpu_target(struct mvebu_mbus_state *mbus)
534 {
535 int i;
536 int cs;
537
538 mvebu_mbus_dram_info.mbus_dram_target_id = TARGET_DDR;
539
540 for (i = 0, cs = 0; i < 2; i++) {
541 u32 map = readl(mbus->sdramwins_base + DOVE_DDR_BASE_CS_OFF(i));
542
543 /*
544 * Chip select enabled?
545 */
546 if (map & 1) {
547 struct mbus_dram_window *w;
548
549 w = &mvebu_mbus_dram_info.cs[cs++];
550 w->cs_index = i;
551 w->mbus_attr = 0; /* CS address decoding done inside */
552 /* the DDR controller, no need to */
553 /* provide attributes */
554 w->base = map & 0xff800000;
555 w->size = 0x100000 << (((map & 0x000f0000) >> 16) - 4);
556 }
557 }
558
559 mvebu_mbus_dram_info.num_cs = cs;
560 }
561
562 static const struct mvebu_mbus_soc_data armada_370_xp_mbus_data = {
563 .num_wins = 20,
564 .num_remappable_wins = 8,
565 .win_cfg_offset = armada_370_xp_mbus_win_offset,
566 .setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
567 .show_cpu_target = mvebu_sdram_debug_show_orion,
568 };
569
570 static const struct mvebu_mbus_soc_data kirkwood_mbus_data = {
571 .num_wins = 8,
572 .num_remappable_wins = 4,
573 .win_cfg_offset = orion_mbus_win_offset,
574 .setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
575 .show_cpu_target = mvebu_sdram_debug_show_orion,
576 };
577
578 static const struct mvebu_mbus_soc_data dove_mbus_data = {
579 .num_wins = 8,
580 .num_remappable_wins = 4,
581 .win_cfg_offset = orion_mbus_win_offset,
582 .setup_cpu_target = mvebu_mbus_dove_setup_cpu_target,
583 .show_cpu_target = mvebu_sdram_debug_show_dove,
584 };
585
586 /*
587 * Some variants of Orion5x have 4 remappable windows, some other have
588 * only two of them.
589 */
590 static const struct mvebu_mbus_soc_data orion5x_4win_mbus_data = {
591 .num_wins = 8,
592 .num_remappable_wins = 4,
593 .win_cfg_offset = orion_mbus_win_offset,
594 .setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
595 .show_cpu_target = mvebu_sdram_debug_show_orion,
596 };
597
598 static const struct mvebu_mbus_soc_data orion5x_2win_mbus_data = {
599 .num_wins = 8,
600 .num_remappable_wins = 2,
601 .win_cfg_offset = orion_mbus_win_offset,
602 .setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
603 .show_cpu_target = mvebu_sdram_debug_show_orion,
604 };
605
606 static const struct mvebu_mbus_soc_data mv78xx0_mbus_data = {
607 .num_wins = 14,
608 .num_remappable_wins = 8,
609 .win_cfg_offset = mv78xx0_mbus_win_offset,
610 .setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
611 .show_cpu_target = mvebu_sdram_debug_show_orion,
612 };
613
614 static const struct of_device_id of_mvebu_mbus_ids[] = {
615 { .compatible = "marvell,armada370-mbus",
616 .data = &armada_370_xp_mbus_data, },
617 { .compatible = "marvell,armadaxp-mbus",
618 .data = &armada_370_xp_mbus_data, },
619 { .compatible = "marvell,kirkwood-mbus",
620 .data = &kirkwood_mbus_data, },
621 { .compatible = "marvell,dove-mbus",
622 .data = &dove_mbus_data, },
623 { .compatible = "marvell,orion5x-88f5281-mbus",
624 .data = &orion5x_4win_mbus_data, },
625 { .compatible = "marvell,orion5x-88f5182-mbus",
626 .data = &orion5x_2win_mbus_data, },
627 { .compatible = "marvell,orion5x-88f5181-mbus",
628 .data = &orion5x_2win_mbus_data, },
629 { .compatible = "marvell,orion5x-88f6183-mbus",
630 .data = &orion5x_4win_mbus_data, },
631 { .compatible = "marvell,mv78xx0-mbus",
632 .data = &mv78xx0_mbus_data, },
633 { },
634 };
635
636 /*
637 * Public API of the driver
638 */
mvebu_mbus_add_window_remap_by_id(unsigned int target,unsigned int attribute,phys_addr_t base,size_t size,phys_addr_t remap)639 int mvebu_mbus_add_window_remap_by_id(unsigned int target,
640 unsigned int attribute,
641 phys_addr_t base, size_t size,
642 phys_addr_t remap)
643 {
644 struct mvebu_mbus_state *s = &mbus_state;
645
646 if (!mvebu_mbus_window_conflicts(s, base, size, target, attribute)) {
647 pr_err("cannot add window '%x:%x', conflicts with another window\n",
648 target, attribute);
649 return -EINVAL;
650 }
651
652 return mvebu_mbus_alloc_window(s, base, size, remap, target, attribute);
653 }
654
mvebu_mbus_add_window_by_id(unsigned int target,unsigned int attribute,phys_addr_t base,size_t size)655 int mvebu_mbus_add_window_by_id(unsigned int target, unsigned int attribute,
656 phys_addr_t base, size_t size)
657 {
658 return mvebu_mbus_add_window_remap_by_id(target, attribute, base,
659 size, MVEBU_MBUS_NO_REMAP);
660 }
661
mvebu_mbus_del_window(phys_addr_t base,size_t size)662 int mvebu_mbus_del_window(phys_addr_t base, size_t size)
663 {
664 int win;
665
666 win = mvebu_mbus_find_window(&mbus_state, base, size);
667 if (win < 0)
668 return win;
669
670 mvebu_mbus_disable_window(&mbus_state, win);
671 return 0;
672 }
673
mvebu_mbus_get_pcie_mem_aperture(struct resource * res)674 void mvebu_mbus_get_pcie_mem_aperture(struct resource *res)
675 {
676 if (!res)
677 return;
678 *res = mbus_state.pcie_mem_aperture;
679 }
680
mvebu_mbus_get_pcie_io_aperture(struct resource * res)681 void mvebu_mbus_get_pcie_io_aperture(struct resource *res)
682 {
683 if (!res)
684 return;
685 *res = mbus_state.pcie_io_aperture;
686 }
687
mvebu_mbus_debugfs_init(void)688 static __init int mvebu_mbus_debugfs_init(void)
689 {
690 struct mvebu_mbus_state *s = &mbus_state;
691
692 /*
693 * If no base has been initialized, doesn't make sense to
694 * register the debugfs entries. We may be on a multiplatform
695 * kernel that isn't running a Marvell EBU SoC.
696 */
697 if (!s->mbuswins_base)
698 return 0;
699
700 s->debugfs_root = debugfs_create_dir("mvebu-mbus", NULL);
701 if (s->debugfs_root) {
702 s->debugfs_sdram = debugfs_create_file("sdram", S_IRUGO,
703 s->debugfs_root, NULL,
704 &mvebu_sdram_debug_fops);
705 s->debugfs_devs = debugfs_create_file("devices", S_IRUGO,
706 s->debugfs_root, NULL,
707 &mvebu_devs_debug_fops);
708 }
709
710 return 0;
711 }
712 fs_initcall(mvebu_mbus_debugfs_init);
713
mvebu_mbus_common_init(struct mvebu_mbus_state * mbus,phys_addr_t mbuswins_phys_base,size_t mbuswins_size,phys_addr_t sdramwins_phys_base,size_t sdramwins_size)714 static int __init mvebu_mbus_common_init(struct mvebu_mbus_state *mbus,
715 phys_addr_t mbuswins_phys_base,
716 size_t mbuswins_size,
717 phys_addr_t sdramwins_phys_base,
718 size_t sdramwins_size)
719 {
720 int win;
721
722 mbus->mbuswins_base = ioremap(mbuswins_phys_base, mbuswins_size);
723 if (!mbus->mbuswins_base)
724 return -ENOMEM;
725
726 mbus->sdramwins_base = ioremap(sdramwins_phys_base, sdramwins_size);
727 if (!mbus->sdramwins_base) {
728 iounmap(mbus_state.mbuswins_base);
729 return -ENOMEM;
730 }
731
732 for (win = 0; win < mbus->soc->num_wins; win++)
733 mvebu_mbus_disable_window(mbus, win);
734
735 mbus->soc->setup_cpu_target(mbus);
736
737 return 0;
738 }
739
mvebu_mbus_init(const char * soc,phys_addr_t mbuswins_phys_base,size_t mbuswins_size,phys_addr_t sdramwins_phys_base,size_t sdramwins_size)740 int __init mvebu_mbus_init(const char *soc, phys_addr_t mbuswins_phys_base,
741 size_t mbuswins_size,
742 phys_addr_t sdramwins_phys_base,
743 size_t sdramwins_size)
744 {
745 const struct of_device_id *of_id;
746
747 for (of_id = of_mvebu_mbus_ids; of_id->compatible[0]; of_id++)
748 if (!strcmp(of_id->compatible, soc))
749 break;
750
751 if (!of_id->compatible[0]) {
752 pr_err("could not find a matching SoC family\n");
753 return -ENODEV;
754 }
755
756 mbus_state.soc = of_id->data;
757
758 return mvebu_mbus_common_init(&mbus_state,
759 mbuswins_phys_base,
760 mbuswins_size,
761 sdramwins_phys_base,
762 sdramwins_size);
763 }
764
765 #ifdef CONFIG_OF
766 /*
767 * The window IDs in the ranges DT property have the following format:
768 * - bits 28 to 31: MBus custom field
769 * - bits 24 to 27: window target ID
770 * - bits 16 to 23: window attribute ID
771 * - bits 0 to 15: unused
772 */
773 #define CUSTOM(id) (((id) & 0xF0000000) >> 24)
774 #define TARGET(id) (((id) & 0x0F000000) >> 24)
775 #define ATTR(id) (((id) & 0x00FF0000) >> 16)
776
mbus_dt_setup_win(struct mvebu_mbus_state * mbus,u32 base,u32 size,u8 target,u8 attr)777 static int __init mbus_dt_setup_win(struct mvebu_mbus_state *mbus,
778 u32 base, u32 size,
779 u8 target, u8 attr)
780 {
781 if (!mvebu_mbus_window_conflicts(mbus, base, size, target, attr)) {
782 pr_err("cannot add window '%04x:%04x', conflicts with another window\n",
783 target, attr);
784 return -EBUSY;
785 }
786
787 if (mvebu_mbus_alloc_window(mbus, base, size, MVEBU_MBUS_NO_REMAP,
788 target, attr)) {
789 pr_err("cannot add window '%04x:%04x', too many windows\n",
790 target, attr);
791 return -ENOMEM;
792 }
793 return 0;
794 }
795
796 static int __init
mbus_parse_ranges(struct device_node * node,int * addr_cells,int * c_addr_cells,int * c_size_cells,int * cell_count,const __be32 ** ranges_start,const __be32 ** ranges_end)797 mbus_parse_ranges(struct device_node *node,
798 int *addr_cells, int *c_addr_cells, int *c_size_cells,
799 int *cell_count, const __be32 **ranges_start,
800 const __be32 **ranges_end)
801 {
802 const __be32 *prop;
803 int ranges_len, tuple_len;
804
805 /* Allow a node with no 'ranges' property */
806 *ranges_start = of_get_property(node, "ranges", &ranges_len);
807 if (*ranges_start == NULL) {
808 *addr_cells = *c_addr_cells = *c_size_cells = *cell_count = 0;
809 *ranges_start = *ranges_end = NULL;
810 return 0;
811 }
812 *ranges_end = *ranges_start + ranges_len / sizeof(__be32);
813
814 *addr_cells = of_n_addr_cells(node);
815
816 prop = of_get_property(node, "#address-cells", NULL);
817 *c_addr_cells = be32_to_cpup(prop);
818
819 prop = of_get_property(node, "#size-cells", NULL);
820 *c_size_cells = be32_to_cpup(prop);
821
822 *cell_count = *addr_cells + *c_addr_cells + *c_size_cells;
823 tuple_len = (*cell_count) * sizeof(__be32);
824
825 if (ranges_len % tuple_len) {
826 pr_warn("malformed ranges entry '%s'\n", node->name);
827 return -EINVAL;
828 }
829 return 0;
830 }
831
mbus_dt_setup(struct mvebu_mbus_state * mbus,struct device_node * np)832 static int __init mbus_dt_setup(struct mvebu_mbus_state *mbus,
833 struct device_node *np)
834 {
835 int addr_cells, c_addr_cells, c_size_cells;
836 int i, ret, cell_count;
837 const __be32 *r, *ranges_start, *ranges_end;
838
839 ret = mbus_parse_ranges(np, &addr_cells, &c_addr_cells,
840 &c_size_cells, &cell_count,
841 &ranges_start, &ranges_end);
842 if (ret < 0)
843 return ret;
844
845 for (i = 0, r = ranges_start; r < ranges_end; r += cell_count, i++) {
846 u32 windowid, base, size;
847 u8 target, attr;
848
849 /*
850 * An entry with a non-zero custom field do not
851 * correspond to a static window, so skip it.
852 */
853 windowid = of_read_number(r, 1);
854 if (CUSTOM(windowid))
855 continue;
856
857 target = TARGET(windowid);
858 attr = ATTR(windowid);
859
860 base = of_read_number(r + c_addr_cells, addr_cells);
861 size = of_read_number(r + c_addr_cells + addr_cells,
862 c_size_cells);
863 ret = mbus_dt_setup_win(mbus, base, size, target, attr);
864 if (ret < 0)
865 return ret;
866 }
867 return 0;
868 }
869
mvebu_mbus_get_pcie_resources(struct device_node * np,struct resource * mem,struct resource * io)870 static void __init mvebu_mbus_get_pcie_resources(struct device_node *np,
871 struct resource *mem,
872 struct resource *io)
873 {
874 u32 reg[2];
875 int ret;
876
877 /*
878 * These are optional, so we make sure that resource_size(x) will
879 * return 0.
880 */
881 memset(mem, 0, sizeof(struct resource));
882 mem->end = -1;
883 memset(io, 0, sizeof(struct resource));
884 io->end = -1;
885
886 ret = of_property_read_u32_array(np, "pcie-mem-aperture", reg, ARRAY_SIZE(reg));
887 if (!ret) {
888 mem->start = reg[0];
889 mem->end = mem->start + reg[1] - 1;
890 mem->flags = IORESOURCE_MEM;
891 }
892
893 ret = of_property_read_u32_array(np, "pcie-io-aperture", reg, ARRAY_SIZE(reg));
894 if (!ret) {
895 io->start = reg[0];
896 io->end = io->start + reg[1] - 1;
897 io->flags = IORESOURCE_IO;
898 }
899 }
900
mvebu_mbus_dt_init(bool is_coherent)901 int __init mvebu_mbus_dt_init(bool is_coherent)
902 {
903 struct resource mbuswins_res, sdramwins_res;
904 struct device_node *np, *controller;
905 const struct of_device_id *of_id;
906 const __be32 *prop;
907 int ret;
908
909 np = of_find_matching_node_and_match(NULL, of_mvebu_mbus_ids, &of_id);
910 if (!np) {
911 pr_err("could not find a matching SoC family\n");
912 return -ENODEV;
913 }
914
915 mbus_state.soc = of_id->data;
916
917 prop = of_get_property(np, "controller", NULL);
918 if (!prop) {
919 pr_err("required 'controller' property missing\n");
920 return -EINVAL;
921 }
922
923 controller = of_find_node_by_phandle(be32_to_cpup(prop));
924 if (!controller) {
925 pr_err("could not find an 'mbus-controller' node\n");
926 return -ENODEV;
927 }
928
929 if (of_address_to_resource(controller, 0, &mbuswins_res)) {
930 pr_err("cannot get MBUS register address\n");
931 return -EINVAL;
932 }
933
934 if (of_address_to_resource(controller, 1, &sdramwins_res)) {
935 pr_err("cannot get SDRAM register address\n");
936 return -EINVAL;
937 }
938
939 mbus_state.hw_io_coherency = is_coherent;
940
941 /* Get optional pcie-{mem,io}-aperture properties */
942 mvebu_mbus_get_pcie_resources(np, &mbus_state.pcie_mem_aperture,
943 &mbus_state.pcie_io_aperture);
944
945 ret = mvebu_mbus_common_init(&mbus_state,
946 mbuswins_res.start,
947 resource_size(&mbuswins_res),
948 sdramwins_res.start,
949 resource_size(&sdramwins_res));
950 if (ret)
951 return ret;
952
953 /* Setup statically declared windows in the DT */
954 return mbus_dt_setup(&mbus_state, np);
955 }
956 #endif
957