1 /*
2 * WM831x clock control
3 *
4 * Copyright 2011-2 Wolfson Microelectronics PLC.
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 */
14
15 #include <linux/clk.h>
16 #include <linux/clk-provider.h>
17 #include <linux/delay.h>
18 #include <linux/module.h>
19 #include <linux/slab.h>
20 #include <linux/platform_device.h>
21 #include <linux/mfd/wm831x/core.h>
22
23 struct wm831x_clk {
24 struct wm831x *wm831x;
25 struct clk_hw xtal_hw;
26 struct clk_hw fll_hw;
27 struct clk_hw clkout_hw;
28 struct clk *xtal;
29 struct clk *fll;
30 struct clk *clkout;
31 bool xtal_ena;
32 };
33
wm831x_xtal_is_prepared(struct clk_hw * hw)34 static int wm831x_xtal_is_prepared(struct clk_hw *hw)
35 {
36 struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
37 xtal_hw);
38
39 return clkdata->xtal_ena;
40 }
41
wm831x_xtal_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)42 static unsigned long wm831x_xtal_recalc_rate(struct clk_hw *hw,
43 unsigned long parent_rate)
44 {
45 struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
46 xtal_hw);
47
48 if (clkdata->xtal_ena)
49 return 32768;
50 else
51 return 0;
52 }
53
54 static const struct clk_ops wm831x_xtal_ops = {
55 .is_prepared = wm831x_xtal_is_prepared,
56 .recalc_rate = wm831x_xtal_recalc_rate,
57 };
58
59 static struct clk_init_data wm831x_xtal_init = {
60 .name = "xtal",
61 .ops = &wm831x_xtal_ops,
62 .flags = CLK_IS_ROOT,
63 };
64
65 static const unsigned long wm831x_fll_auto_rates[] = {
66 2048000,
67 11289600,
68 12000000,
69 12288000,
70 19200000,
71 22579600,
72 24000000,
73 24576000,
74 };
75
wm831x_fll_is_prepared(struct clk_hw * hw)76 static int wm831x_fll_is_prepared(struct clk_hw *hw)
77 {
78 struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
79 fll_hw);
80 struct wm831x *wm831x = clkdata->wm831x;
81 int ret;
82
83 ret = wm831x_reg_read(wm831x, WM831X_FLL_CONTROL_1);
84 if (ret < 0) {
85 dev_err(wm831x->dev, "Unable to read FLL_CONTROL_1: %d\n",
86 ret);
87 return true;
88 }
89
90 return (ret & WM831X_FLL_ENA) != 0;
91 }
92
wm831x_fll_prepare(struct clk_hw * hw)93 static int wm831x_fll_prepare(struct clk_hw *hw)
94 {
95 struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
96 fll_hw);
97 struct wm831x *wm831x = clkdata->wm831x;
98 int ret;
99
100 ret = wm831x_set_bits(wm831x, WM831X_FLL_CONTROL_1,
101 WM831X_FLL_ENA, WM831X_FLL_ENA);
102 if (ret != 0)
103 dev_crit(wm831x->dev, "Failed to enable FLL: %d\n", ret);
104
105 usleep_range(2000, 2000);
106
107 return ret;
108 }
109
wm831x_fll_unprepare(struct clk_hw * hw)110 static void wm831x_fll_unprepare(struct clk_hw *hw)
111 {
112 struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
113 fll_hw);
114 struct wm831x *wm831x = clkdata->wm831x;
115 int ret;
116
117 ret = wm831x_set_bits(wm831x, WM831X_FLL_CONTROL_1, WM831X_FLL_ENA, 0);
118 if (ret != 0)
119 dev_crit(wm831x->dev, "Failed to disable FLL: %d\n", ret);
120 }
121
wm831x_fll_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)122 static unsigned long wm831x_fll_recalc_rate(struct clk_hw *hw,
123 unsigned long parent_rate)
124 {
125 struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
126 fll_hw);
127 struct wm831x *wm831x = clkdata->wm831x;
128 int ret;
129
130 ret = wm831x_reg_read(wm831x, WM831X_CLOCK_CONTROL_2);
131 if (ret < 0) {
132 dev_err(wm831x->dev, "Unable to read CLOCK_CONTROL_2: %d\n",
133 ret);
134 return 0;
135 }
136
137 if (ret & WM831X_FLL_AUTO)
138 return wm831x_fll_auto_rates[ret & WM831X_FLL_AUTO_FREQ_MASK];
139
140 dev_err(wm831x->dev, "FLL only supported in AUTO mode\n");
141
142 return 0;
143 }
144
wm831x_fll_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * unused)145 static long wm831x_fll_round_rate(struct clk_hw *hw, unsigned long rate,
146 unsigned long *unused)
147 {
148 int best = 0;
149 int i;
150
151 for (i = 0; i < ARRAY_SIZE(wm831x_fll_auto_rates); i++)
152 if (abs(wm831x_fll_auto_rates[i] - rate) <
153 abs(wm831x_fll_auto_rates[best] - rate))
154 best = i;
155
156 return wm831x_fll_auto_rates[best];
157 }
158
wm831x_fll_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)159 static int wm831x_fll_set_rate(struct clk_hw *hw, unsigned long rate,
160 unsigned long parent_rate)
161 {
162 struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
163 fll_hw);
164 struct wm831x *wm831x = clkdata->wm831x;
165 int i;
166
167 for (i = 0; i < ARRAY_SIZE(wm831x_fll_auto_rates); i++)
168 if (wm831x_fll_auto_rates[i] == rate)
169 break;
170 if (i == ARRAY_SIZE(wm831x_fll_auto_rates))
171 return -EINVAL;
172
173 if (wm831x_fll_is_prepared(hw))
174 return -EPERM;
175
176 return wm831x_set_bits(wm831x, WM831X_CLOCK_CONTROL_2,
177 WM831X_FLL_AUTO_FREQ_MASK, i);
178 }
179
180 static const char *wm831x_fll_parents[] = {
181 "xtal",
182 "clkin",
183 };
184
wm831x_fll_get_parent(struct clk_hw * hw)185 static u8 wm831x_fll_get_parent(struct clk_hw *hw)
186 {
187 struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
188 fll_hw);
189 struct wm831x *wm831x = clkdata->wm831x;
190 int ret;
191
192 /* AUTO mode is always clocked from the crystal */
193 ret = wm831x_reg_read(wm831x, WM831X_CLOCK_CONTROL_2);
194 if (ret < 0) {
195 dev_err(wm831x->dev, "Unable to read CLOCK_CONTROL_2: %d\n",
196 ret);
197 return 0;
198 }
199
200 if (ret & WM831X_FLL_AUTO)
201 return 0;
202
203 ret = wm831x_reg_read(wm831x, WM831X_FLL_CONTROL_5);
204 if (ret < 0) {
205 dev_err(wm831x->dev, "Unable to read FLL_CONTROL_5: %d\n",
206 ret);
207 return 0;
208 }
209
210 switch (ret & WM831X_FLL_CLK_SRC_MASK) {
211 case 0:
212 return 0;
213 case 1:
214 return 1;
215 default:
216 dev_err(wm831x->dev, "Unsupported FLL clock source %d\n",
217 ret & WM831X_FLL_CLK_SRC_MASK);
218 return 0;
219 }
220 }
221
222 static const struct clk_ops wm831x_fll_ops = {
223 .is_prepared = wm831x_fll_is_prepared,
224 .prepare = wm831x_fll_prepare,
225 .unprepare = wm831x_fll_unprepare,
226 .round_rate = wm831x_fll_round_rate,
227 .recalc_rate = wm831x_fll_recalc_rate,
228 .set_rate = wm831x_fll_set_rate,
229 .get_parent = wm831x_fll_get_parent,
230 };
231
232 static struct clk_init_data wm831x_fll_init = {
233 .name = "fll",
234 .ops = &wm831x_fll_ops,
235 .parent_names = wm831x_fll_parents,
236 .num_parents = ARRAY_SIZE(wm831x_fll_parents),
237 .flags = CLK_SET_RATE_GATE,
238 };
239
wm831x_clkout_is_prepared(struct clk_hw * hw)240 static int wm831x_clkout_is_prepared(struct clk_hw *hw)
241 {
242 struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
243 clkout_hw);
244 struct wm831x *wm831x = clkdata->wm831x;
245 int ret;
246
247 ret = wm831x_reg_read(wm831x, WM831X_CLOCK_CONTROL_1);
248 if (ret < 0) {
249 dev_err(wm831x->dev, "Unable to read CLOCK_CONTROL_1: %d\n",
250 ret);
251 return true;
252 }
253
254 return (ret & WM831X_CLKOUT_ENA) != 0;
255 }
256
wm831x_clkout_prepare(struct clk_hw * hw)257 static int wm831x_clkout_prepare(struct clk_hw *hw)
258 {
259 struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
260 clkout_hw);
261 struct wm831x *wm831x = clkdata->wm831x;
262 int ret;
263
264 ret = wm831x_reg_unlock(wm831x);
265 if (ret != 0) {
266 dev_crit(wm831x->dev, "Failed to lock registers: %d\n", ret);
267 return ret;
268 }
269
270 ret = wm831x_set_bits(wm831x, WM831X_CLOCK_CONTROL_1,
271 WM831X_CLKOUT_ENA, WM831X_CLKOUT_ENA);
272 if (ret != 0)
273 dev_crit(wm831x->dev, "Failed to enable CLKOUT: %d\n", ret);
274
275 wm831x_reg_lock(wm831x);
276
277 return ret;
278 }
279
wm831x_clkout_unprepare(struct clk_hw * hw)280 static void wm831x_clkout_unprepare(struct clk_hw *hw)
281 {
282 struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
283 clkout_hw);
284 struct wm831x *wm831x = clkdata->wm831x;
285 int ret;
286
287 ret = wm831x_reg_unlock(wm831x);
288 if (ret != 0) {
289 dev_crit(wm831x->dev, "Failed to lock registers: %d\n", ret);
290 return;
291 }
292
293 ret = wm831x_set_bits(wm831x, WM831X_CLOCK_CONTROL_1,
294 WM831X_CLKOUT_ENA, 0);
295 if (ret != 0)
296 dev_crit(wm831x->dev, "Failed to disable CLKOUT: %d\n", ret);
297
298 wm831x_reg_lock(wm831x);
299 }
300
301 static const char *wm831x_clkout_parents[] = {
302 "fll",
303 "xtal",
304 };
305
wm831x_clkout_get_parent(struct clk_hw * hw)306 static u8 wm831x_clkout_get_parent(struct clk_hw *hw)
307 {
308 struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
309 clkout_hw);
310 struct wm831x *wm831x = clkdata->wm831x;
311 int ret;
312
313 ret = wm831x_reg_read(wm831x, WM831X_CLOCK_CONTROL_1);
314 if (ret < 0) {
315 dev_err(wm831x->dev, "Unable to read CLOCK_CONTROL_1: %d\n",
316 ret);
317 return 0;
318 }
319
320 if (ret & WM831X_CLKOUT_SRC)
321 return 1;
322 else
323 return 0;
324 }
325
wm831x_clkout_set_parent(struct clk_hw * hw,u8 parent)326 static int wm831x_clkout_set_parent(struct clk_hw *hw, u8 parent)
327 {
328 struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk,
329 clkout_hw);
330 struct wm831x *wm831x = clkdata->wm831x;
331
332 return wm831x_set_bits(wm831x, WM831X_CLOCK_CONTROL_1,
333 WM831X_CLKOUT_SRC,
334 parent << WM831X_CLKOUT_SRC_SHIFT);
335 }
336
337 static const struct clk_ops wm831x_clkout_ops = {
338 .is_prepared = wm831x_clkout_is_prepared,
339 .prepare = wm831x_clkout_prepare,
340 .unprepare = wm831x_clkout_unprepare,
341 .get_parent = wm831x_clkout_get_parent,
342 .set_parent = wm831x_clkout_set_parent,
343 };
344
345 static struct clk_init_data wm831x_clkout_init = {
346 .name = "clkout",
347 .ops = &wm831x_clkout_ops,
348 .parent_names = wm831x_clkout_parents,
349 .num_parents = ARRAY_SIZE(wm831x_clkout_parents),
350 .flags = CLK_SET_RATE_PARENT,
351 };
352
wm831x_clk_probe(struct platform_device * pdev)353 static int wm831x_clk_probe(struct platform_device *pdev)
354 {
355 struct wm831x *wm831x = dev_get_drvdata(pdev->dev.parent);
356 struct wm831x_clk *clkdata;
357 int ret;
358
359 clkdata = devm_kzalloc(&pdev->dev, sizeof(*clkdata), GFP_KERNEL);
360 if (!clkdata)
361 return -ENOMEM;
362
363 clkdata->wm831x = wm831x;
364
365 /* XTAL_ENA can only be set via OTP/InstantConfig so just read once */
366 ret = wm831x_reg_read(wm831x, WM831X_CLOCK_CONTROL_2);
367 if (ret < 0) {
368 dev_err(wm831x->dev, "Unable to read CLOCK_CONTROL_2: %d\n",
369 ret);
370 return ret;
371 }
372 clkdata->xtal_ena = ret & WM831X_XTAL_ENA;
373
374 clkdata->xtal_hw.init = &wm831x_xtal_init;
375 clkdata->xtal = devm_clk_register(&pdev->dev, &clkdata->xtal_hw);
376 if (IS_ERR(clkdata->xtal))
377 return PTR_ERR(clkdata->xtal);
378
379 clkdata->fll_hw.init = &wm831x_fll_init;
380 clkdata->fll = devm_clk_register(&pdev->dev, &clkdata->fll_hw);
381 if (IS_ERR(clkdata->fll))
382 return PTR_ERR(clkdata->fll);
383
384 clkdata->clkout_hw.init = &wm831x_clkout_init;
385 clkdata->clkout = devm_clk_register(&pdev->dev, &clkdata->clkout_hw);
386 if (IS_ERR(clkdata->clkout))
387 return PTR_ERR(clkdata->clkout);
388
389 platform_set_drvdata(pdev, clkdata);
390
391 return 0;
392 }
393
394 static struct platform_driver wm831x_clk_driver = {
395 .probe = wm831x_clk_probe,
396 .driver = {
397 .name = "wm831x-clk",
398 },
399 };
400
401 module_platform_driver(wm831x_clk_driver);
402
403 /* Module information */
404 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
405 MODULE_DESCRIPTION("WM831x clock driver");
406 MODULE_LICENSE("GPL");
407 MODULE_ALIAS("platform:wm831x-clk");
408