1 /*
2 * Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de>
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * Common Clock Framework support for s3c24xx external clock output.
9 */
10
11 #include <linux/platform_device.h>
12 #include <linux/module.h>
13 #include "clk.h"
14
15 /* legacy access to misccr, until dt conversion is finished */
16 #include <mach/hardware.h>
17 #include <mach/regs-gpio.h>
18
19 #define MUX_DCLK0 0
20 #define MUX_DCLK1 1
21 #define DIV_DCLK0 2
22 #define DIV_DCLK1 3
23 #define GATE_DCLK0 4
24 #define GATE_DCLK1 5
25 #define MUX_CLKOUT0 6
26 #define MUX_CLKOUT1 7
27 #define DCLK_MAX_CLKS (MUX_CLKOUT1 + 1)
28
29 enum supported_socs {
30 S3C2410,
31 S3C2412,
32 S3C2440,
33 S3C2443,
34 };
35
36 struct s3c24xx_dclk_drv_data {
37 const char **clkout0_parent_names;
38 int clkout0_num_parents;
39 const char **clkout1_parent_names;
40 int clkout1_num_parents;
41 const char **mux_parent_names;
42 int mux_num_parents;
43 };
44
45 /*
46 * Clock for output-parent selection in misccr
47 */
48
49 struct s3c24xx_clkout {
50 struct clk_hw hw;
51 u32 mask;
52 u8 shift;
53 };
54
55 #define to_s3c24xx_clkout(_hw) container_of(_hw, struct s3c24xx_clkout, hw)
56
s3c24xx_clkout_get_parent(struct clk_hw * hw)57 static u8 s3c24xx_clkout_get_parent(struct clk_hw *hw)
58 {
59 struct s3c24xx_clkout *clkout = to_s3c24xx_clkout(hw);
60 int num_parents = __clk_get_num_parents(hw->clk);
61 u32 val;
62
63 val = readl_relaxed(S3C24XX_MISCCR) >> clkout->shift;
64 val >>= clkout->shift;
65 val &= clkout->mask;
66
67 if (val >= num_parents)
68 return -EINVAL;
69
70 return val;
71 }
72
s3c24xx_clkout_set_parent(struct clk_hw * hw,u8 index)73 static int s3c24xx_clkout_set_parent(struct clk_hw *hw, u8 index)
74 {
75 struct s3c24xx_clkout *clkout = to_s3c24xx_clkout(hw);
76 int ret = 0;
77
78 s3c2410_modify_misccr((clkout->mask << clkout->shift),
79 (index << clkout->shift));
80
81 return ret;
82 }
83
84 const struct clk_ops s3c24xx_clkout_ops = {
85 .get_parent = s3c24xx_clkout_get_parent,
86 .set_parent = s3c24xx_clkout_set_parent,
87 .determine_rate = __clk_mux_determine_rate,
88 };
89
s3c24xx_register_clkout(struct device * dev,const char * name,const char ** parent_names,u8 num_parents,u8 shift,u32 mask)90 struct clk *s3c24xx_register_clkout(struct device *dev, const char *name,
91 const char **parent_names, u8 num_parents,
92 u8 shift, u32 mask)
93 {
94 struct s3c24xx_clkout *clkout;
95 struct clk *clk;
96 struct clk_init_data init;
97
98 /* allocate the clkout */
99 clkout = kzalloc(sizeof(*clkout), GFP_KERNEL);
100 if (!clkout)
101 return ERR_PTR(-ENOMEM);
102
103 init.name = name;
104 init.ops = &s3c24xx_clkout_ops;
105 init.flags = CLK_IS_BASIC;
106 init.parent_names = parent_names;
107 init.num_parents = num_parents;
108
109 clkout->shift = shift;
110 clkout->mask = mask;
111 clkout->hw.init = &init;
112
113 clk = clk_register(dev, &clkout->hw);
114
115 return clk;
116 }
117
118 /*
119 * dclk and clkout init
120 */
121
122 struct s3c24xx_dclk {
123 struct device *dev;
124 void __iomem *base;
125 struct clk_onecell_data clk_data;
126 struct notifier_block dclk0_div_change_nb;
127 struct notifier_block dclk1_div_change_nb;
128 spinlock_t dclk_lock;
129 unsigned long reg_save;
130 };
131
132 #define to_s3c24xx_dclk0(x) \
133 container_of(x, struct s3c24xx_dclk, dclk0_div_change_nb)
134
135 #define to_s3c24xx_dclk1(x) \
136 container_of(x, struct s3c24xx_dclk, dclk1_div_change_nb)
137
138 static const char *dclk_s3c2410_p[] = { "pclk", "uclk" };
139 static const char *clkout0_s3c2410_p[] = { "mpll", "upll", "fclk", "hclk", "pclk",
140 "gate_dclk0" };
141 static const char *clkout1_s3c2410_p[] = { "mpll", "upll", "fclk", "hclk", "pclk",
142 "gate_dclk1" };
143
144 static const char *clkout0_s3c2412_p[] = { "mpll", "upll", "rtc_clkout",
145 "hclk", "pclk", "gate_dclk0" };
146 static const char *clkout1_s3c2412_p[] = { "xti", "upll", "fclk", "hclk", "pclk",
147 "gate_dclk1" };
148
149 static const char *clkout0_s3c2440_p[] = { "xti", "upll", "fclk", "hclk", "pclk",
150 "gate_dclk0" };
151 static const char *clkout1_s3c2440_p[] = { "mpll", "upll", "rtc_clkout",
152 "hclk", "pclk", "gate_dclk1" };
153
154 static const char *dclk_s3c2443_p[] = { "pclk", "epll" };
155 static const char *clkout0_s3c2443_p[] = { "xti", "epll", "armclk", "hclk", "pclk",
156 "gate_dclk0" };
157 static const char *clkout1_s3c2443_p[] = { "dummy", "epll", "rtc_clkout",
158 "hclk", "pclk", "gate_dclk1" };
159
160 #define DCLKCON_DCLK_DIV_MASK 0xf
161 #define DCLKCON_DCLK0_DIV_SHIFT 4
162 #define DCLKCON_DCLK0_CMP_SHIFT 8
163 #define DCLKCON_DCLK1_DIV_SHIFT 20
164 #define DCLKCON_DCLK1_CMP_SHIFT 24
165
s3c24xx_dclk_update_cmp(struct s3c24xx_dclk * s3c24xx_dclk,int div_shift,int cmp_shift)166 static void s3c24xx_dclk_update_cmp(struct s3c24xx_dclk *s3c24xx_dclk,
167 int div_shift, int cmp_shift)
168 {
169 unsigned long flags = 0;
170 u32 dclk_con, div, cmp;
171
172 spin_lock_irqsave(&s3c24xx_dclk->dclk_lock, flags);
173
174 dclk_con = readl_relaxed(s3c24xx_dclk->base);
175
176 div = ((dclk_con >> div_shift) & DCLKCON_DCLK_DIV_MASK) + 1;
177 cmp = ((div + 1) / 2) - 1;
178
179 dclk_con &= ~(DCLKCON_DCLK_DIV_MASK << cmp_shift);
180 dclk_con |= (cmp << cmp_shift);
181
182 writel_relaxed(dclk_con, s3c24xx_dclk->base);
183
184 spin_unlock_irqrestore(&s3c24xx_dclk->dclk_lock, flags);
185 }
186
s3c24xx_dclk0_div_notify(struct notifier_block * nb,unsigned long event,void * data)187 static int s3c24xx_dclk0_div_notify(struct notifier_block *nb,
188 unsigned long event, void *data)
189 {
190 struct s3c24xx_dclk *s3c24xx_dclk = to_s3c24xx_dclk0(nb);
191
192 if (event == POST_RATE_CHANGE) {
193 s3c24xx_dclk_update_cmp(s3c24xx_dclk,
194 DCLKCON_DCLK0_DIV_SHIFT, DCLKCON_DCLK0_CMP_SHIFT);
195 }
196
197 return NOTIFY_DONE;
198 }
199
s3c24xx_dclk1_div_notify(struct notifier_block * nb,unsigned long event,void * data)200 static int s3c24xx_dclk1_div_notify(struct notifier_block *nb,
201 unsigned long event, void *data)
202 {
203 struct s3c24xx_dclk *s3c24xx_dclk = to_s3c24xx_dclk1(nb);
204
205 if (event == POST_RATE_CHANGE) {
206 s3c24xx_dclk_update_cmp(s3c24xx_dclk,
207 DCLKCON_DCLK1_DIV_SHIFT, DCLKCON_DCLK1_CMP_SHIFT);
208 }
209
210 return NOTIFY_DONE;
211 }
212
213 #ifdef CONFIG_PM_SLEEP
s3c24xx_dclk_suspend(struct device * dev)214 static int s3c24xx_dclk_suspend(struct device *dev)
215 {
216 struct platform_device *pdev = to_platform_device(dev);
217 struct s3c24xx_dclk *s3c24xx_dclk = platform_get_drvdata(pdev);
218
219 s3c24xx_dclk->reg_save = readl_relaxed(s3c24xx_dclk->base);
220 return 0;
221 }
222
s3c24xx_dclk_resume(struct device * dev)223 static int s3c24xx_dclk_resume(struct device *dev)
224 {
225 struct platform_device *pdev = to_platform_device(dev);
226 struct s3c24xx_dclk *s3c24xx_dclk = platform_get_drvdata(pdev);
227
228 writel_relaxed(s3c24xx_dclk->reg_save, s3c24xx_dclk->base);
229 return 0;
230 }
231 #endif
232
233 static SIMPLE_DEV_PM_OPS(s3c24xx_dclk_pm_ops,
234 s3c24xx_dclk_suspend, s3c24xx_dclk_resume);
235
s3c24xx_dclk_probe(struct platform_device * pdev)236 static int s3c24xx_dclk_probe(struct platform_device *pdev)
237 {
238 struct s3c24xx_dclk *s3c24xx_dclk;
239 struct resource *mem;
240 struct clk **clk_table;
241 struct s3c24xx_dclk_drv_data *dclk_variant;
242 int ret, i;
243
244 s3c24xx_dclk = devm_kzalloc(&pdev->dev, sizeof(*s3c24xx_dclk),
245 GFP_KERNEL);
246 if (!s3c24xx_dclk)
247 return -ENOMEM;
248
249 s3c24xx_dclk->dev = &pdev->dev;
250 platform_set_drvdata(pdev, s3c24xx_dclk);
251 spin_lock_init(&s3c24xx_dclk->dclk_lock);
252
253 clk_table = devm_kzalloc(&pdev->dev,
254 sizeof(struct clk *) * DCLK_MAX_CLKS,
255 GFP_KERNEL);
256 if (!clk_table)
257 return -ENOMEM;
258
259 s3c24xx_dclk->clk_data.clks = clk_table;
260 s3c24xx_dclk->clk_data.clk_num = DCLK_MAX_CLKS;
261
262 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
263 s3c24xx_dclk->base = devm_ioremap_resource(&pdev->dev, mem);
264 if (IS_ERR(s3c24xx_dclk->base))
265 return PTR_ERR(s3c24xx_dclk->base);
266
267 dclk_variant = (struct s3c24xx_dclk_drv_data *)
268 platform_get_device_id(pdev)->driver_data;
269
270
271 clk_table[MUX_DCLK0] = clk_register_mux(&pdev->dev, "mux_dclk0",
272 dclk_variant->mux_parent_names,
273 dclk_variant->mux_num_parents, 0,
274 s3c24xx_dclk->base, 1, 1, 0,
275 &s3c24xx_dclk->dclk_lock);
276 clk_table[MUX_DCLK1] = clk_register_mux(&pdev->dev, "mux_dclk1",
277 dclk_variant->mux_parent_names,
278 dclk_variant->mux_num_parents, 0,
279 s3c24xx_dclk->base, 17, 1, 0,
280 &s3c24xx_dclk->dclk_lock);
281
282 clk_table[DIV_DCLK0] = clk_register_divider(&pdev->dev, "div_dclk0",
283 "mux_dclk0", 0, s3c24xx_dclk->base,
284 4, 4, 0, &s3c24xx_dclk->dclk_lock);
285 clk_table[DIV_DCLK1] = clk_register_divider(&pdev->dev, "div_dclk1",
286 "mux_dclk1", 0, s3c24xx_dclk->base,
287 20, 4, 0, &s3c24xx_dclk->dclk_lock);
288
289 clk_table[GATE_DCLK0] = clk_register_gate(&pdev->dev, "gate_dclk0",
290 "div_dclk0", CLK_SET_RATE_PARENT,
291 s3c24xx_dclk->base, 0, 0,
292 &s3c24xx_dclk->dclk_lock);
293 clk_table[GATE_DCLK1] = clk_register_gate(&pdev->dev, "gate_dclk1",
294 "div_dclk1", CLK_SET_RATE_PARENT,
295 s3c24xx_dclk->base, 16, 0,
296 &s3c24xx_dclk->dclk_lock);
297
298 clk_table[MUX_CLKOUT0] = s3c24xx_register_clkout(&pdev->dev,
299 "clkout0", dclk_variant->clkout0_parent_names,
300 dclk_variant->clkout0_num_parents, 4, 7);
301 clk_table[MUX_CLKOUT1] = s3c24xx_register_clkout(&pdev->dev,
302 "clkout1", dclk_variant->clkout1_parent_names,
303 dclk_variant->clkout1_num_parents, 8, 7);
304
305 for (i = 0; i < DCLK_MAX_CLKS; i++)
306 if (IS_ERR(clk_table[i])) {
307 dev_err(&pdev->dev, "clock %d failed to register\n", i);
308 ret = PTR_ERR(clk_table[i]);
309 goto err_clk_register;
310 }
311
312 ret = clk_register_clkdev(clk_table[MUX_DCLK0], "dclk0", NULL);
313 if (!ret)
314 ret = clk_register_clkdev(clk_table[MUX_DCLK1], "dclk1", NULL);
315 if (!ret)
316 ret = clk_register_clkdev(clk_table[MUX_CLKOUT0],
317 "clkout0", NULL);
318 if (!ret)
319 ret = clk_register_clkdev(clk_table[MUX_CLKOUT1],
320 "clkout1", NULL);
321 if (ret) {
322 dev_err(&pdev->dev, "failed to register aliases, %d\n", ret);
323 goto err_clk_register;
324 }
325
326 s3c24xx_dclk->dclk0_div_change_nb.notifier_call =
327 s3c24xx_dclk0_div_notify;
328
329 s3c24xx_dclk->dclk1_div_change_nb.notifier_call =
330 s3c24xx_dclk1_div_notify;
331
332 ret = clk_notifier_register(clk_table[DIV_DCLK0],
333 &s3c24xx_dclk->dclk0_div_change_nb);
334 if (ret)
335 goto err_clk_register;
336
337 ret = clk_notifier_register(clk_table[DIV_DCLK1],
338 &s3c24xx_dclk->dclk1_div_change_nb);
339 if (ret)
340 goto err_dclk_notify;
341
342 return 0;
343
344 err_dclk_notify:
345 clk_notifier_unregister(clk_table[DIV_DCLK0],
346 &s3c24xx_dclk->dclk0_div_change_nb);
347 err_clk_register:
348 for (i = 0; i < DCLK_MAX_CLKS; i++)
349 if (clk_table[i] && !IS_ERR(clk_table[i]))
350 clk_unregister(clk_table[i]);
351
352 return ret;
353 }
354
s3c24xx_dclk_remove(struct platform_device * pdev)355 static int s3c24xx_dclk_remove(struct platform_device *pdev)
356 {
357 struct s3c24xx_dclk *s3c24xx_dclk = platform_get_drvdata(pdev);
358 struct clk **clk_table = s3c24xx_dclk->clk_data.clks;
359 int i;
360
361 clk_notifier_unregister(clk_table[DIV_DCLK1],
362 &s3c24xx_dclk->dclk1_div_change_nb);
363 clk_notifier_unregister(clk_table[DIV_DCLK0],
364 &s3c24xx_dclk->dclk0_div_change_nb);
365
366 for (i = 0; i < DCLK_MAX_CLKS; i++)
367 clk_unregister(clk_table[i]);
368
369 return 0;
370 }
371
372 static struct s3c24xx_dclk_drv_data dclk_variants[] = {
373 [S3C2410] = {
374 .clkout0_parent_names = clkout0_s3c2410_p,
375 .clkout0_num_parents = ARRAY_SIZE(clkout0_s3c2410_p),
376 .clkout1_parent_names = clkout1_s3c2410_p,
377 .clkout1_num_parents = ARRAY_SIZE(clkout1_s3c2410_p),
378 .mux_parent_names = dclk_s3c2410_p,
379 .mux_num_parents = ARRAY_SIZE(dclk_s3c2410_p),
380 },
381 [S3C2412] = {
382 .clkout0_parent_names = clkout0_s3c2412_p,
383 .clkout0_num_parents = ARRAY_SIZE(clkout0_s3c2412_p),
384 .clkout1_parent_names = clkout1_s3c2412_p,
385 .clkout1_num_parents = ARRAY_SIZE(clkout1_s3c2412_p),
386 .mux_parent_names = dclk_s3c2410_p,
387 .mux_num_parents = ARRAY_SIZE(dclk_s3c2410_p),
388 },
389 [S3C2440] = {
390 .clkout0_parent_names = clkout0_s3c2440_p,
391 .clkout0_num_parents = ARRAY_SIZE(clkout0_s3c2440_p),
392 .clkout1_parent_names = clkout1_s3c2440_p,
393 .clkout1_num_parents = ARRAY_SIZE(clkout1_s3c2440_p),
394 .mux_parent_names = dclk_s3c2410_p,
395 .mux_num_parents = ARRAY_SIZE(dclk_s3c2410_p),
396 },
397 [S3C2443] = {
398 .clkout0_parent_names = clkout0_s3c2443_p,
399 .clkout0_num_parents = ARRAY_SIZE(clkout0_s3c2443_p),
400 .clkout1_parent_names = clkout1_s3c2443_p,
401 .clkout1_num_parents = ARRAY_SIZE(clkout1_s3c2443_p),
402 .mux_parent_names = dclk_s3c2443_p,
403 .mux_num_parents = ARRAY_SIZE(dclk_s3c2443_p),
404 },
405 };
406
407 static struct platform_device_id s3c24xx_dclk_driver_ids[] = {
408 {
409 .name = "s3c2410-dclk",
410 .driver_data = (kernel_ulong_t)&dclk_variants[S3C2410],
411 }, {
412 .name = "s3c2412-dclk",
413 .driver_data = (kernel_ulong_t)&dclk_variants[S3C2412],
414 }, {
415 .name = "s3c2440-dclk",
416 .driver_data = (kernel_ulong_t)&dclk_variants[S3C2440],
417 }, {
418 .name = "s3c2443-dclk",
419 .driver_data = (kernel_ulong_t)&dclk_variants[S3C2443],
420 },
421 { }
422 };
423
424 MODULE_DEVICE_TABLE(platform, s3c24xx_dclk_driver_ids);
425
426 static struct platform_driver s3c24xx_dclk_driver = {
427 .driver = {
428 .name = "s3c24xx-dclk",
429 .pm = &s3c24xx_dclk_pm_ops,
430 },
431 .probe = s3c24xx_dclk_probe,
432 .remove = s3c24xx_dclk_remove,
433 .id_table = s3c24xx_dclk_driver_ids,
434 };
435 module_platform_driver(s3c24xx_dclk_driver);
436
437 MODULE_LICENSE("GPL v2");
438 MODULE_AUTHOR("Heiko Stuebner <heiko@sntech.de>");
439 MODULE_DESCRIPTION("Driver for the S3C24XX external clock outputs");
440