1 /*
2 * OMAP gate clock support
3 *
4 * Copyright (C) 2013 Texas Instruments, Inc.
5 *
6 * Tero Kristo <t-kristo@ti.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
13 * kind, whether express or implied; without even the implied warranty
14 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 */
17
18 #include <linux/clk-provider.h>
19 #include <linux/slab.h>
20 #include <linux/io.h>
21 #include <linux/of.h>
22 #include <linux/of_address.h>
23 #include <linux/clk/ti.h>
24
25 #define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw)
26
27 #undef pr_fmt
28 #define pr_fmt(fmt) "%s: " fmt, __func__
29
30 static int omap36xx_gate_clk_enable_with_hsdiv_restore(struct clk_hw *clk);
31
32 static const struct clk_ops omap_gate_clkdm_clk_ops = {
33 .init = &omap2_init_clk_clkdm,
34 .enable = &omap2_clkops_enable_clkdm,
35 .disable = &omap2_clkops_disable_clkdm,
36 };
37
38 static const struct clk_ops omap_gate_clk_ops = {
39 .init = &omap2_init_clk_clkdm,
40 .enable = &omap2_dflt_clk_enable,
41 .disable = &omap2_dflt_clk_disable,
42 .is_enabled = &omap2_dflt_clk_is_enabled,
43 };
44
45 static const struct clk_ops omap_gate_clk_hsdiv_restore_ops = {
46 .init = &omap2_init_clk_clkdm,
47 .enable = &omap36xx_gate_clk_enable_with_hsdiv_restore,
48 .disable = &omap2_dflt_clk_disable,
49 .is_enabled = &omap2_dflt_clk_is_enabled,
50 };
51
52 /**
53 * omap36xx_gate_clk_enable_with_hsdiv_restore - enable clocks suffering
54 * from HSDivider PWRDN problem Implements Errata ID: i556.
55 * @clk: DPLL output struct clk
56 *
57 * 3630 only: dpll3_m3_ck, dpll4_m2_ck, dpll4_m3_ck, dpll4_m4_ck,
58 * dpll4_m5_ck & dpll4_m6_ck dividers gets loaded with reset
59 * valueafter their respective PWRDN bits are set. Any dummy write
60 * (Any other value different from the Read value) to the
61 * corresponding CM_CLKSEL register will refresh the dividers.
62 */
omap36xx_gate_clk_enable_with_hsdiv_restore(struct clk_hw * clk)63 static int omap36xx_gate_clk_enable_with_hsdiv_restore(struct clk_hw *clk)
64 {
65 struct clk_divider *parent;
66 struct clk_hw *parent_hw;
67 u32 dummy_v, orig_v;
68 int ret;
69
70 /* Clear PWRDN bit of HSDIVIDER */
71 ret = omap2_dflt_clk_enable(clk);
72
73 /* Parent is the x2 node, get parent of parent for the m2 div */
74 parent_hw = __clk_get_hw(__clk_get_parent(__clk_get_parent(clk->clk)));
75 parent = to_clk_divider(parent_hw);
76
77 /* Restore the dividers */
78 if (!ret) {
79 orig_v = ti_clk_ll_ops->clk_readl(parent->reg);
80 dummy_v = orig_v;
81
82 /* Write any other value different from the Read value */
83 dummy_v ^= (1 << parent->shift);
84 ti_clk_ll_ops->clk_writel(dummy_v, parent->reg);
85
86 /* Write the original divider */
87 ti_clk_ll_ops->clk_writel(orig_v, parent->reg);
88 }
89
90 return ret;
91 }
92
_of_ti_gate_clk_setup(struct device_node * node,const struct clk_ops * ops,const struct clk_hw_omap_ops * hw_ops)93 static void __init _of_ti_gate_clk_setup(struct device_node *node,
94 const struct clk_ops *ops,
95 const struct clk_hw_omap_ops *hw_ops)
96 {
97 struct clk *clk;
98 struct clk_init_data init = { NULL };
99 struct clk_hw_omap *clk_hw;
100 const char *clk_name = node->name;
101 const char *parent_name;
102 u32 val;
103
104 clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
105 if (!clk_hw)
106 return;
107
108 clk_hw->hw.init = &init;
109
110 init.name = clk_name;
111 init.ops = ops;
112
113 if (ops != &omap_gate_clkdm_clk_ops) {
114 clk_hw->enable_reg = ti_clk_get_reg_addr(node, 0);
115 if (!clk_hw->enable_reg)
116 goto cleanup;
117
118 if (!of_property_read_u32(node, "ti,bit-shift", &val))
119 clk_hw->enable_bit = val;
120 }
121
122 clk_hw->ops = hw_ops;
123
124 clk_hw->flags = MEMMAP_ADDRESSING;
125
126 if (of_clk_get_parent_count(node) != 1) {
127 pr_err("%s must have 1 parent\n", clk_name);
128 goto cleanup;
129 }
130
131 parent_name = of_clk_get_parent_name(node, 0);
132 init.parent_names = &parent_name;
133 init.num_parents = 1;
134
135 if (of_property_read_bool(node, "ti,set-rate-parent"))
136 init.flags |= CLK_SET_RATE_PARENT;
137
138 if (of_property_read_bool(node, "ti,set-bit-to-disable"))
139 clk_hw->flags |= INVERT_ENABLE;
140
141 clk = clk_register(NULL, &clk_hw->hw);
142
143 if (!IS_ERR(clk)) {
144 of_clk_add_provider(node, of_clk_src_simple_get, clk);
145 return;
146 }
147
148 cleanup:
149 kfree(clk_hw);
150 }
151
152 static void __init
_of_ti_composite_gate_clk_setup(struct device_node * node,const struct clk_hw_omap_ops * hw_ops)153 _of_ti_composite_gate_clk_setup(struct device_node *node,
154 const struct clk_hw_omap_ops *hw_ops)
155 {
156 struct clk_hw_omap *gate;
157 u32 val = 0;
158
159 gate = kzalloc(sizeof(*gate), GFP_KERNEL);
160 if (!gate)
161 return;
162
163 gate->enable_reg = ti_clk_get_reg_addr(node, 0);
164 if (!gate->enable_reg)
165 goto cleanup;
166
167 of_property_read_u32(node, "ti,bit-shift", &val);
168
169 gate->enable_bit = val;
170 gate->ops = hw_ops;
171 gate->flags = MEMMAP_ADDRESSING;
172
173 if (!ti_clk_add_component(node, &gate->hw, CLK_COMPONENT_TYPE_GATE))
174 return;
175
176 cleanup:
177 kfree(gate);
178 }
179
180 static void __init
of_ti_composite_no_wait_gate_clk_setup(struct device_node * node)181 of_ti_composite_no_wait_gate_clk_setup(struct device_node *node)
182 {
183 _of_ti_composite_gate_clk_setup(node, NULL);
184 }
185 CLK_OF_DECLARE(ti_composite_no_wait_gate_clk, "ti,composite-no-wait-gate-clock",
186 of_ti_composite_no_wait_gate_clk_setup);
187
188 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
of_ti_composite_interface_clk_setup(struct device_node * node)189 static void __init of_ti_composite_interface_clk_setup(struct device_node *node)
190 {
191 _of_ti_composite_gate_clk_setup(node, &clkhwops_iclk_wait);
192 }
193 CLK_OF_DECLARE(ti_composite_interface_clk, "ti,composite-interface-clock",
194 of_ti_composite_interface_clk_setup);
195 #endif
196
of_ti_composite_gate_clk_setup(struct device_node * node)197 static void __init of_ti_composite_gate_clk_setup(struct device_node *node)
198 {
199 _of_ti_composite_gate_clk_setup(node, &clkhwops_wait);
200 }
201 CLK_OF_DECLARE(ti_composite_gate_clk, "ti,composite-gate-clock",
202 of_ti_composite_gate_clk_setup);
203
204
of_ti_clkdm_gate_clk_setup(struct device_node * node)205 static void __init of_ti_clkdm_gate_clk_setup(struct device_node *node)
206 {
207 _of_ti_gate_clk_setup(node, &omap_gate_clkdm_clk_ops, NULL);
208 }
209 CLK_OF_DECLARE(ti_clkdm_gate_clk, "ti,clkdm-gate-clock",
210 of_ti_clkdm_gate_clk_setup);
211
of_ti_hsdiv_gate_clk_setup(struct device_node * node)212 static void __init of_ti_hsdiv_gate_clk_setup(struct device_node *node)
213 {
214 _of_ti_gate_clk_setup(node, &omap_gate_clk_hsdiv_restore_ops,
215 &clkhwops_wait);
216 }
217 CLK_OF_DECLARE(ti_hsdiv_gate_clk, "ti,hsdiv-gate-clock",
218 of_ti_hsdiv_gate_clk_setup);
219
of_ti_gate_clk_setup(struct device_node * node)220 static void __init of_ti_gate_clk_setup(struct device_node *node)
221 {
222 _of_ti_gate_clk_setup(node, &omap_gate_clk_ops, NULL);
223 }
224 CLK_OF_DECLARE(ti_gate_clk, "ti,gate-clock", of_ti_gate_clk_setup);
225
of_ti_wait_gate_clk_setup(struct device_node * node)226 static void __init of_ti_wait_gate_clk_setup(struct device_node *node)
227 {
228 _of_ti_gate_clk_setup(node, &omap_gate_clk_ops, &clkhwops_wait);
229 }
230 CLK_OF_DECLARE(ti_wait_gate_clk, "ti,wait-gate-clock",
231 of_ti_wait_gate_clk_setup);
232
233 #ifdef CONFIG_ARCH_OMAP3
of_ti_am35xx_gate_clk_setup(struct device_node * node)234 static void __init of_ti_am35xx_gate_clk_setup(struct device_node *node)
235 {
236 _of_ti_gate_clk_setup(node, &omap_gate_clk_ops,
237 &clkhwops_am35xx_ipss_module_wait);
238 }
239 CLK_OF_DECLARE(ti_am35xx_gate_clk, "ti,am35xx-gate-clock",
240 of_ti_am35xx_gate_clk_setup);
241
of_ti_dss_gate_clk_setup(struct device_node * node)242 static void __init of_ti_dss_gate_clk_setup(struct device_node *node)
243 {
244 _of_ti_gate_clk_setup(node, &omap_gate_clk_ops,
245 &clkhwops_omap3430es2_dss_usbhost_wait);
246 }
247 CLK_OF_DECLARE(ti_dss_gate_clk, "ti,dss-gate-clock",
248 of_ti_dss_gate_clk_setup);
249 #endif
250