1 /*
2 * drivers/dma/imx-sdma.c
3 *
4 * This file contains a driver for the Freescale Smart DMA engine
5 *
6 * Copyright 2010 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
7 *
8 * Based on code from Freescale:
9 *
10 * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
11 *
12 * The code contained herein is licensed under the GNU General Public
13 * License. You may obtain a copy of the GNU General Public License
14 * Version 2 or later at the following locations:
15 *
16 * http://www.opensource.org/licenses/gpl-license.html
17 * http://www.gnu.org/copyleft/gpl.html
18 */
19
20 #include <linux/init.h>
21 #include <linux/module.h>
22 #include <linux/types.h>
23 #include <linux/bitops.h>
24 #include <linux/mm.h>
25 #include <linux/interrupt.h>
26 #include <linux/clk.h>
27 #include <linux/delay.h>
28 #include <linux/sched.h>
29 #include <linux/semaphore.h>
30 #include <linux/spinlock.h>
31 #include <linux/device.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/firmware.h>
34 #include <linux/slab.h>
35 #include <linux/platform_device.h>
36 #include <linux/dmaengine.h>
37 #include <linux/of.h>
38 #include <linux/of_device.h>
39 #include <linux/of_dma.h>
40
41 #include <asm/irq.h>
42 #include <linux/platform_data/dma-imx-sdma.h>
43 #include <linux/platform_data/dma-imx.h>
44
45 #include "dmaengine.h"
46
47 /* SDMA registers */
48 #define SDMA_H_C0PTR 0x000
49 #define SDMA_H_INTR 0x004
50 #define SDMA_H_STATSTOP 0x008
51 #define SDMA_H_START 0x00c
52 #define SDMA_H_EVTOVR 0x010
53 #define SDMA_H_DSPOVR 0x014
54 #define SDMA_H_HOSTOVR 0x018
55 #define SDMA_H_EVTPEND 0x01c
56 #define SDMA_H_DSPENBL 0x020
57 #define SDMA_H_RESET 0x024
58 #define SDMA_H_EVTERR 0x028
59 #define SDMA_H_INTRMSK 0x02c
60 #define SDMA_H_PSW 0x030
61 #define SDMA_H_EVTERRDBG 0x034
62 #define SDMA_H_CONFIG 0x038
63 #define SDMA_ONCE_ENB 0x040
64 #define SDMA_ONCE_DATA 0x044
65 #define SDMA_ONCE_INSTR 0x048
66 #define SDMA_ONCE_STAT 0x04c
67 #define SDMA_ONCE_CMD 0x050
68 #define SDMA_EVT_MIRROR 0x054
69 #define SDMA_ILLINSTADDR 0x058
70 #define SDMA_CHN0ADDR 0x05c
71 #define SDMA_ONCE_RTB 0x060
72 #define SDMA_XTRIG_CONF1 0x070
73 #define SDMA_XTRIG_CONF2 0x074
74 #define SDMA_CHNENBL0_IMX35 0x200
75 #define SDMA_CHNENBL0_IMX31 0x080
76 #define SDMA_CHNPRI_0 0x100
77
78 /*
79 * Buffer descriptor status values.
80 */
81 #define BD_DONE 0x01
82 #define BD_WRAP 0x02
83 #define BD_CONT 0x04
84 #define BD_INTR 0x08
85 #define BD_RROR 0x10
86 #define BD_LAST 0x20
87 #define BD_EXTD 0x80
88
89 /*
90 * Data Node descriptor status values.
91 */
92 #define DND_END_OF_FRAME 0x80
93 #define DND_END_OF_XFER 0x40
94 #define DND_DONE 0x20
95 #define DND_UNUSED 0x01
96
97 /*
98 * IPCV2 descriptor status values.
99 */
100 #define BD_IPCV2_END_OF_FRAME 0x40
101
102 #define IPCV2_MAX_NODES 50
103 /*
104 * Error bit set in the CCB status field by the SDMA,
105 * in setbd routine, in case of a transfer error
106 */
107 #define DATA_ERROR 0x10000000
108
109 /*
110 * Buffer descriptor commands.
111 */
112 #define C0_ADDR 0x01
113 #define C0_LOAD 0x02
114 #define C0_DUMP 0x03
115 #define C0_SETCTX 0x07
116 #define C0_GETCTX 0x03
117 #define C0_SETDM 0x01
118 #define C0_SETPM 0x04
119 #define C0_GETDM 0x02
120 #define C0_GETPM 0x08
121 /*
122 * Change endianness indicator in the BD command field
123 */
124 #define CHANGE_ENDIANNESS 0x80
125
126 /*
127 * Mode/Count of data node descriptors - IPCv2
128 */
129 struct sdma_mode_count {
130 u32 count : 16; /* size of the buffer pointed by this BD */
131 u32 status : 8; /* E,R,I,C,W,D status bits stored here */
132 u32 command : 8; /* command mostlky used for channel 0 */
133 };
134
135 /*
136 * Buffer descriptor
137 */
138 struct sdma_buffer_descriptor {
139 struct sdma_mode_count mode;
140 u32 buffer_addr; /* address of the buffer described */
141 u32 ext_buffer_addr; /* extended buffer address */
142 } __attribute__ ((packed));
143
144 /**
145 * struct sdma_channel_control - Channel control Block
146 *
147 * @current_bd_ptr current buffer descriptor processed
148 * @base_bd_ptr first element of buffer descriptor array
149 * @unused padding. The SDMA engine expects an array of 128 byte
150 * control blocks
151 */
152 struct sdma_channel_control {
153 u32 current_bd_ptr;
154 u32 base_bd_ptr;
155 u32 unused[2];
156 } __attribute__ ((packed));
157
158 /**
159 * struct sdma_state_registers - SDMA context for a channel
160 *
161 * @pc: program counter
162 * @t: test bit: status of arithmetic & test instruction
163 * @rpc: return program counter
164 * @sf: source fault while loading data
165 * @spc: loop start program counter
166 * @df: destination fault while storing data
167 * @epc: loop end program counter
168 * @lm: loop mode
169 */
170 struct sdma_state_registers {
171 u32 pc :14;
172 u32 unused1: 1;
173 u32 t : 1;
174 u32 rpc :14;
175 u32 unused0: 1;
176 u32 sf : 1;
177 u32 spc :14;
178 u32 unused2: 1;
179 u32 df : 1;
180 u32 epc :14;
181 u32 lm : 2;
182 } __attribute__ ((packed));
183
184 /**
185 * struct sdma_context_data - sdma context specific to a channel
186 *
187 * @channel_state: channel state bits
188 * @gReg: general registers
189 * @mda: burst dma destination address register
190 * @msa: burst dma source address register
191 * @ms: burst dma status register
192 * @md: burst dma data register
193 * @pda: peripheral dma destination address register
194 * @psa: peripheral dma source address register
195 * @ps: peripheral dma status register
196 * @pd: peripheral dma data register
197 * @ca: CRC polynomial register
198 * @cs: CRC accumulator register
199 * @dda: dedicated core destination address register
200 * @dsa: dedicated core source address register
201 * @ds: dedicated core status register
202 * @dd: dedicated core data register
203 */
204 struct sdma_context_data {
205 struct sdma_state_registers channel_state;
206 u32 gReg[8];
207 u32 mda;
208 u32 msa;
209 u32 ms;
210 u32 md;
211 u32 pda;
212 u32 psa;
213 u32 ps;
214 u32 pd;
215 u32 ca;
216 u32 cs;
217 u32 dda;
218 u32 dsa;
219 u32 ds;
220 u32 dd;
221 u32 scratch0;
222 u32 scratch1;
223 u32 scratch2;
224 u32 scratch3;
225 u32 scratch4;
226 u32 scratch5;
227 u32 scratch6;
228 u32 scratch7;
229 } __attribute__ ((packed));
230
231 #define NUM_BD (int)(PAGE_SIZE / sizeof(struct sdma_buffer_descriptor))
232
233 struct sdma_engine;
234
235 /**
236 * struct sdma_channel - housekeeping for a SDMA channel
237 *
238 * @sdma pointer to the SDMA engine for this channel
239 * @channel the channel number, matches dmaengine chan_id + 1
240 * @direction transfer type. Needed for setting SDMA script
241 * @peripheral_type Peripheral type. Needed for setting SDMA script
242 * @event_id0 aka dma request line
243 * @event_id1 for channels that use 2 events
244 * @word_size peripheral access size
245 * @buf_tail ID of the buffer that was processed
246 * @num_bd max NUM_BD. number of descriptors currently handling
247 */
248 struct sdma_channel {
249 struct sdma_engine *sdma;
250 unsigned int channel;
251 enum dma_transfer_direction direction;
252 enum sdma_peripheral_type peripheral_type;
253 unsigned int event_id0;
254 unsigned int event_id1;
255 enum dma_slave_buswidth word_size;
256 unsigned int buf_tail;
257 unsigned int num_bd;
258 unsigned int period_len;
259 struct sdma_buffer_descriptor *bd;
260 dma_addr_t bd_phys;
261 unsigned int pc_from_device, pc_to_device;
262 unsigned long flags;
263 dma_addr_t per_address;
264 unsigned long event_mask[2];
265 unsigned long watermark_level;
266 u32 shp_addr, per_addr;
267 struct dma_chan chan;
268 spinlock_t lock;
269 struct dma_async_tx_descriptor desc;
270 enum dma_status status;
271 unsigned int chn_count;
272 unsigned int chn_real_count;
273 struct tasklet_struct tasklet;
274 struct imx_dma_data data;
275 };
276
277 #define IMX_DMA_SG_LOOP BIT(0)
278
279 #define MAX_DMA_CHANNELS 32
280 #define MXC_SDMA_DEFAULT_PRIORITY 1
281 #define MXC_SDMA_MIN_PRIORITY 1
282 #define MXC_SDMA_MAX_PRIORITY 7
283
284 #define SDMA_FIRMWARE_MAGIC 0x414d4453
285
286 /**
287 * struct sdma_firmware_header - Layout of the firmware image
288 *
289 * @magic "SDMA"
290 * @version_major increased whenever layout of struct sdma_script_start_addrs
291 * changes.
292 * @version_minor firmware minor version (for binary compatible changes)
293 * @script_addrs_start offset of struct sdma_script_start_addrs in this image
294 * @num_script_addrs Number of script addresses in this image
295 * @ram_code_start offset of SDMA ram image in this firmware image
296 * @ram_code_size size of SDMA ram image
297 * @script_addrs Stores the start address of the SDMA scripts
298 * (in SDMA memory space)
299 */
300 struct sdma_firmware_header {
301 u32 magic;
302 u32 version_major;
303 u32 version_minor;
304 u32 script_addrs_start;
305 u32 num_script_addrs;
306 u32 ram_code_start;
307 u32 ram_code_size;
308 };
309
310 struct sdma_driver_data {
311 int chnenbl0;
312 int num_events;
313 struct sdma_script_start_addrs *script_addrs;
314 };
315
316 struct sdma_engine {
317 struct device *dev;
318 struct device_dma_parameters dma_parms;
319 struct sdma_channel channel[MAX_DMA_CHANNELS];
320 struct sdma_channel_control *channel_control;
321 void __iomem *regs;
322 struct sdma_context_data *context;
323 dma_addr_t context_phys;
324 struct dma_device dma_device;
325 struct clk *clk_ipg;
326 struct clk *clk_ahb;
327 spinlock_t channel_0_lock;
328 u32 script_number;
329 struct sdma_script_start_addrs *script_addrs;
330 const struct sdma_driver_data *drvdata;
331 };
332
333 static struct sdma_driver_data sdma_imx31 = {
334 .chnenbl0 = SDMA_CHNENBL0_IMX31,
335 .num_events = 32,
336 };
337
338 static struct sdma_script_start_addrs sdma_script_imx25 = {
339 .ap_2_ap_addr = 729,
340 .uart_2_mcu_addr = 904,
341 .per_2_app_addr = 1255,
342 .mcu_2_app_addr = 834,
343 .uartsh_2_mcu_addr = 1120,
344 .per_2_shp_addr = 1329,
345 .mcu_2_shp_addr = 1048,
346 .ata_2_mcu_addr = 1560,
347 .mcu_2_ata_addr = 1479,
348 .app_2_per_addr = 1189,
349 .app_2_mcu_addr = 770,
350 .shp_2_per_addr = 1407,
351 .shp_2_mcu_addr = 979,
352 };
353
354 static struct sdma_driver_data sdma_imx25 = {
355 .chnenbl0 = SDMA_CHNENBL0_IMX35,
356 .num_events = 48,
357 .script_addrs = &sdma_script_imx25,
358 };
359
360 static struct sdma_driver_data sdma_imx35 = {
361 .chnenbl0 = SDMA_CHNENBL0_IMX35,
362 .num_events = 48,
363 };
364
365 static struct sdma_script_start_addrs sdma_script_imx51 = {
366 .ap_2_ap_addr = 642,
367 .uart_2_mcu_addr = 817,
368 .mcu_2_app_addr = 747,
369 .mcu_2_shp_addr = 961,
370 .ata_2_mcu_addr = 1473,
371 .mcu_2_ata_addr = 1392,
372 .app_2_per_addr = 1033,
373 .app_2_mcu_addr = 683,
374 .shp_2_per_addr = 1251,
375 .shp_2_mcu_addr = 892,
376 };
377
378 static struct sdma_driver_data sdma_imx51 = {
379 .chnenbl0 = SDMA_CHNENBL0_IMX35,
380 .num_events = 48,
381 .script_addrs = &sdma_script_imx51,
382 };
383
384 static struct sdma_script_start_addrs sdma_script_imx53 = {
385 .ap_2_ap_addr = 642,
386 .app_2_mcu_addr = 683,
387 .mcu_2_app_addr = 747,
388 .uart_2_mcu_addr = 817,
389 .shp_2_mcu_addr = 891,
390 .mcu_2_shp_addr = 960,
391 .uartsh_2_mcu_addr = 1032,
392 .spdif_2_mcu_addr = 1100,
393 .mcu_2_spdif_addr = 1134,
394 .firi_2_mcu_addr = 1193,
395 .mcu_2_firi_addr = 1290,
396 };
397
398 static struct sdma_driver_data sdma_imx53 = {
399 .chnenbl0 = SDMA_CHNENBL0_IMX35,
400 .num_events = 48,
401 .script_addrs = &sdma_script_imx53,
402 };
403
404 static struct sdma_script_start_addrs sdma_script_imx6q = {
405 .ap_2_ap_addr = 642,
406 .uart_2_mcu_addr = 817,
407 .mcu_2_app_addr = 747,
408 .per_2_per_addr = 6331,
409 .uartsh_2_mcu_addr = 1032,
410 .mcu_2_shp_addr = 960,
411 .app_2_mcu_addr = 683,
412 .shp_2_mcu_addr = 891,
413 .spdif_2_mcu_addr = 1100,
414 .mcu_2_spdif_addr = 1134,
415 };
416
417 static struct sdma_driver_data sdma_imx6q = {
418 .chnenbl0 = SDMA_CHNENBL0_IMX35,
419 .num_events = 48,
420 .script_addrs = &sdma_script_imx6q,
421 };
422
423 static struct platform_device_id sdma_devtypes[] = {
424 {
425 .name = "imx25-sdma",
426 .driver_data = (unsigned long)&sdma_imx25,
427 }, {
428 .name = "imx31-sdma",
429 .driver_data = (unsigned long)&sdma_imx31,
430 }, {
431 .name = "imx35-sdma",
432 .driver_data = (unsigned long)&sdma_imx35,
433 }, {
434 .name = "imx51-sdma",
435 .driver_data = (unsigned long)&sdma_imx51,
436 }, {
437 .name = "imx53-sdma",
438 .driver_data = (unsigned long)&sdma_imx53,
439 }, {
440 .name = "imx6q-sdma",
441 .driver_data = (unsigned long)&sdma_imx6q,
442 }, {
443 /* sentinel */
444 }
445 };
446 MODULE_DEVICE_TABLE(platform, sdma_devtypes);
447
448 static const struct of_device_id sdma_dt_ids[] = {
449 { .compatible = "fsl,imx6q-sdma", .data = &sdma_imx6q, },
450 { .compatible = "fsl,imx53-sdma", .data = &sdma_imx53, },
451 { .compatible = "fsl,imx51-sdma", .data = &sdma_imx51, },
452 { .compatible = "fsl,imx35-sdma", .data = &sdma_imx35, },
453 { .compatible = "fsl,imx31-sdma", .data = &sdma_imx31, },
454 { .compatible = "fsl,imx25-sdma", .data = &sdma_imx25, },
455 { /* sentinel */ }
456 };
457 MODULE_DEVICE_TABLE(of, sdma_dt_ids);
458
459 #define SDMA_H_CONFIG_DSPDMA BIT(12) /* indicates if the DSPDMA is used */
460 #define SDMA_H_CONFIG_RTD_PINS BIT(11) /* indicates if Real-Time Debug pins are enabled */
461 #define SDMA_H_CONFIG_ACR BIT(4) /* indicates if AHB freq /core freq = 2 or 1 */
462 #define SDMA_H_CONFIG_CSM (3) /* indicates which context switch mode is selected*/
463
chnenbl_ofs(struct sdma_engine * sdma,unsigned int event)464 static inline u32 chnenbl_ofs(struct sdma_engine *sdma, unsigned int event)
465 {
466 u32 chnenbl0 = sdma->drvdata->chnenbl0;
467 return chnenbl0 + event * 4;
468 }
469
sdma_config_ownership(struct sdma_channel * sdmac,bool event_override,bool mcu_override,bool dsp_override)470 static int sdma_config_ownership(struct sdma_channel *sdmac,
471 bool event_override, bool mcu_override, bool dsp_override)
472 {
473 struct sdma_engine *sdma = sdmac->sdma;
474 int channel = sdmac->channel;
475 unsigned long evt, mcu, dsp;
476
477 if (event_override && mcu_override && dsp_override)
478 return -EINVAL;
479
480 evt = readl_relaxed(sdma->regs + SDMA_H_EVTOVR);
481 mcu = readl_relaxed(sdma->regs + SDMA_H_HOSTOVR);
482 dsp = readl_relaxed(sdma->regs + SDMA_H_DSPOVR);
483
484 if (dsp_override)
485 __clear_bit(channel, &dsp);
486 else
487 __set_bit(channel, &dsp);
488
489 if (event_override)
490 __clear_bit(channel, &evt);
491 else
492 __set_bit(channel, &evt);
493
494 if (mcu_override)
495 __clear_bit(channel, &mcu);
496 else
497 __set_bit(channel, &mcu);
498
499 writel_relaxed(evt, sdma->regs + SDMA_H_EVTOVR);
500 writel_relaxed(mcu, sdma->regs + SDMA_H_HOSTOVR);
501 writel_relaxed(dsp, sdma->regs + SDMA_H_DSPOVR);
502
503 return 0;
504 }
505
sdma_enable_channel(struct sdma_engine * sdma,int channel)506 static void sdma_enable_channel(struct sdma_engine *sdma, int channel)
507 {
508 writel(BIT(channel), sdma->regs + SDMA_H_START);
509 }
510
511 /*
512 * sdma_run_channel0 - run a channel and wait till it's done
513 */
sdma_run_channel0(struct sdma_engine * sdma)514 static int sdma_run_channel0(struct sdma_engine *sdma)
515 {
516 int ret;
517 unsigned long timeout = 500;
518
519 sdma_enable_channel(sdma, 0);
520
521 while (!(ret = readl_relaxed(sdma->regs + SDMA_H_INTR) & 1)) {
522 if (timeout-- <= 0)
523 break;
524 udelay(1);
525 }
526
527 if (ret) {
528 /* Clear the interrupt status */
529 writel_relaxed(ret, sdma->regs + SDMA_H_INTR);
530 } else {
531 dev_err(sdma->dev, "Timeout waiting for CH0 ready\n");
532 }
533
534 /* Set bits of CONFIG register with dynamic context switching */
535 if (readl(sdma->regs + SDMA_H_CONFIG) == 0)
536 writel_relaxed(SDMA_H_CONFIG_CSM, sdma->regs + SDMA_H_CONFIG);
537
538 return ret ? 0 : -ETIMEDOUT;
539 }
540
sdma_load_script(struct sdma_engine * sdma,void * buf,int size,u32 address)541 static int sdma_load_script(struct sdma_engine *sdma, void *buf, int size,
542 u32 address)
543 {
544 struct sdma_buffer_descriptor *bd0 = sdma->channel[0].bd;
545 void *buf_virt;
546 dma_addr_t buf_phys;
547 int ret;
548 unsigned long flags;
549
550 buf_virt = dma_alloc_coherent(NULL,
551 size,
552 &buf_phys, GFP_KERNEL);
553 if (!buf_virt) {
554 return -ENOMEM;
555 }
556
557 spin_lock_irqsave(&sdma->channel_0_lock, flags);
558
559 bd0->mode.command = C0_SETPM;
560 bd0->mode.status = BD_DONE | BD_INTR | BD_WRAP | BD_EXTD;
561 bd0->mode.count = size / 2;
562 bd0->buffer_addr = buf_phys;
563 bd0->ext_buffer_addr = address;
564
565 memcpy(buf_virt, buf, size);
566
567 ret = sdma_run_channel0(sdma);
568
569 spin_unlock_irqrestore(&sdma->channel_0_lock, flags);
570
571 dma_free_coherent(NULL, size, buf_virt, buf_phys);
572
573 return ret;
574 }
575
sdma_event_enable(struct sdma_channel * sdmac,unsigned int event)576 static void sdma_event_enable(struct sdma_channel *sdmac, unsigned int event)
577 {
578 struct sdma_engine *sdma = sdmac->sdma;
579 int channel = sdmac->channel;
580 unsigned long val;
581 u32 chnenbl = chnenbl_ofs(sdma, event);
582
583 val = readl_relaxed(sdma->regs + chnenbl);
584 __set_bit(channel, &val);
585 writel_relaxed(val, sdma->regs + chnenbl);
586 }
587
sdma_event_disable(struct sdma_channel * sdmac,unsigned int event)588 static void sdma_event_disable(struct sdma_channel *sdmac, unsigned int event)
589 {
590 struct sdma_engine *sdma = sdmac->sdma;
591 int channel = sdmac->channel;
592 u32 chnenbl = chnenbl_ofs(sdma, event);
593 unsigned long val;
594
595 val = readl_relaxed(sdma->regs + chnenbl);
596 __clear_bit(channel, &val);
597 writel_relaxed(val, sdma->regs + chnenbl);
598 }
599
sdma_handle_channel_loop(struct sdma_channel * sdmac)600 static void sdma_handle_channel_loop(struct sdma_channel *sdmac)
601 {
602 if (sdmac->desc.callback)
603 sdmac->desc.callback(sdmac->desc.callback_param);
604 }
605
sdma_update_channel_loop(struct sdma_channel * sdmac)606 static void sdma_update_channel_loop(struct sdma_channel *sdmac)
607 {
608 struct sdma_buffer_descriptor *bd;
609
610 /*
611 * loop mode. Iterate over descriptors, re-setup them and
612 * call callback function.
613 */
614 while (1) {
615 bd = &sdmac->bd[sdmac->buf_tail];
616
617 if (bd->mode.status & BD_DONE)
618 break;
619
620 if (bd->mode.status & BD_RROR)
621 sdmac->status = DMA_ERROR;
622
623 bd->mode.status |= BD_DONE;
624 sdmac->buf_tail++;
625 sdmac->buf_tail %= sdmac->num_bd;
626 }
627 }
628
mxc_sdma_handle_channel_normal(struct sdma_channel * sdmac)629 static void mxc_sdma_handle_channel_normal(struct sdma_channel *sdmac)
630 {
631 struct sdma_buffer_descriptor *bd;
632 int i, error = 0;
633
634 sdmac->chn_real_count = 0;
635 /*
636 * non loop mode. Iterate over all descriptors, collect
637 * errors and call callback function
638 */
639 for (i = 0; i < sdmac->num_bd; i++) {
640 bd = &sdmac->bd[i];
641
642 if (bd->mode.status & (BD_DONE | BD_RROR))
643 error = -EIO;
644 sdmac->chn_real_count += bd->mode.count;
645 }
646
647 if (error)
648 sdmac->status = DMA_ERROR;
649 else
650 sdmac->status = DMA_COMPLETE;
651
652 dma_cookie_complete(&sdmac->desc);
653 if (sdmac->desc.callback)
654 sdmac->desc.callback(sdmac->desc.callback_param);
655 }
656
sdma_tasklet(unsigned long data)657 static void sdma_tasklet(unsigned long data)
658 {
659 struct sdma_channel *sdmac = (struct sdma_channel *) data;
660
661 if (sdmac->flags & IMX_DMA_SG_LOOP)
662 sdma_handle_channel_loop(sdmac);
663 else
664 mxc_sdma_handle_channel_normal(sdmac);
665 }
666
sdma_int_handler(int irq,void * dev_id)667 static irqreturn_t sdma_int_handler(int irq, void *dev_id)
668 {
669 struct sdma_engine *sdma = dev_id;
670 unsigned long stat;
671
672 stat = readl_relaxed(sdma->regs + SDMA_H_INTR);
673 /* not interested in channel 0 interrupts */
674 stat &= ~1;
675 writel_relaxed(stat, sdma->regs + SDMA_H_INTR);
676
677 while (stat) {
678 int channel = fls(stat) - 1;
679 struct sdma_channel *sdmac = &sdma->channel[channel];
680
681 if (sdmac->flags & IMX_DMA_SG_LOOP)
682 sdma_update_channel_loop(sdmac);
683
684 tasklet_schedule(&sdmac->tasklet);
685
686 __clear_bit(channel, &stat);
687 }
688
689 return IRQ_HANDLED;
690 }
691
692 /*
693 * sets the pc of SDMA script according to the peripheral type
694 */
sdma_get_pc(struct sdma_channel * sdmac,enum sdma_peripheral_type peripheral_type)695 static void sdma_get_pc(struct sdma_channel *sdmac,
696 enum sdma_peripheral_type peripheral_type)
697 {
698 struct sdma_engine *sdma = sdmac->sdma;
699 int per_2_emi = 0, emi_2_per = 0;
700 /*
701 * These are needed once we start to support transfers between
702 * two peripherals or memory-to-memory transfers
703 */
704 int per_2_per = 0, emi_2_emi = 0;
705
706 sdmac->pc_from_device = 0;
707 sdmac->pc_to_device = 0;
708
709 switch (peripheral_type) {
710 case IMX_DMATYPE_MEMORY:
711 emi_2_emi = sdma->script_addrs->ap_2_ap_addr;
712 break;
713 case IMX_DMATYPE_DSP:
714 emi_2_per = sdma->script_addrs->bp_2_ap_addr;
715 per_2_emi = sdma->script_addrs->ap_2_bp_addr;
716 break;
717 case IMX_DMATYPE_FIRI:
718 per_2_emi = sdma->script_addrs->firi_2_mcu_addr;
719 emi_2_per = sdma->script_addrs->mcu_2_firi_addr;
720 break;
721 case IMX_DMATYPE_UART:
722 per_2_emi = sdma->script_addrs->uart_2_mcu_addr;
723 emi_2_per = sdma->script_addrs->mcu_2_app_addr;
724 break;
725 case IMX_DMATYPE_UART_SP:
726 per_2_emi = sdma->script_addrs->uartsh_2_mcu_addr;
727 emi_2_per = sdma->script_addrs->mcu_2_shp_addr;
728 break;
729 case IMX_DMATYPE_ATA:
730 per_2_emi = sdma->script_addrs->ata_2_mcu_addr;
731 emi_2_per = sdma->script_addrs->mcu_2_ata_addr;
732 break;
733 case IMX_DMATYPE_CSPI:
734 case IMX_DMATYPE_EXT:
735 case IMX_DMATYPE_SSI:
736 per_2_emi = sdma->script_addrs->app_2_mcu_addr;
737 emi_2_per = sdma->script_addrs->mcu_2_app_addr;
738 break;
739 case IMX_DMATYPE_SSI_DUAL:
740 per_2_emi = sdma->script_addrs->ssish_2_mcu_addr;
741 emi_2_per = sdma->script_addrs->mcu_2_ssish_addr;
742 break;
743 case IMX_DMATYPE_SSI_SP:
744 case IMX_DMATYPE_MMC:
745 case IMX_DMATYPE_SDHC:
746 case IMX_DMATYPE_CSPI_SP:
747 case IMX_DMATYPE_ESAI:
748 case IMX_DMATYPE_MSHC_SP:
749 per_2_emi = sdma->script_addrs->shp_2_mcu_addr;
750 emi_2_per = sdma->script_addrs->mcu_2_shp_addr;
751 break;
752 case IMX_DMATYPE_ASRC:
753 per_2_emi = sdma->script_addrs->asrc_2_mcu_addr;
754 emi_2_per = sdma->script_addrs->asrc_2_mcu_addr;
755 per_2_per = sdma->script_addrs->per_2_per_addr;
756 break;
757 case IMX_DMATYPE_ASRC_SP:
758 per_2_emi = sdma->script_addrs->shp_2_mcu_addr;
759 emi_2_per = sdma->script_addrs->mcu_2_shp_addr;
760 per_2_per = sdma->script_addrs->per_2_per_addr;
761 break;
762 case IMX_DMATYPE_MSHC:
763 per_2_emi = sdma->script_addrs->mshc_2_mcu_addr;
764 emi_2_per = sdma->script_addrs->mcu_2_mshc_addr;
765 break;
766 case IMX_DMATYPE_CCM:
767 per_2_emi = sdma->script_addrs->dptc_dvfs_addr;
768 break;
769 case IMX_DMATYPE_SPDIF:
770 per_2_emi = sdma->script_addrs->spdif_2_mcu_addr;
771 emi_2_per = sdma->script_addrs->mcu_2_spdif_addr;
772 break;
773 case IMX_DMATYPE_IPU_MEMORY:
774 emi_2_per = sdma->script_addrs->ext_mem_2_ipu_addr;
775 break;
776 default:
777 break;
778 }
779
780 sdmac->pc_from_device = per_2_emi;
781 sdmac->pc_to_device = emi_2_per;
782 }
783
sdma_load_context(struct sdma_channel * sdmac)784 static int sdma_load_context(struct sdma_channel *sdmac)
785 {
786 struct sdma_engine *sdma = sdmac->sdma;
787 int channel = sdmac->channel;
788 int load_address;
789 struct sdma_context_data *context = sdma->context;
790 struct sdma_buffer_descriptor *bd0 = sdma->channel[0].bd;
791 int ret;
792 unsigned long flags;
793
794 if (sdmac->direction == DMA_DEV_TO_MEM) {
795 load_address = sdmac->pc_from_device;
796 } else {
797 load_address = sdmac->pc_to_device;
798 }
799
800 if (load_address < 0)
801 return load_address;
802
803 dev_dbg(sdma->dev, "load_address = %d\n", load_address);
804 dev_dbg(sdma->dev, "wml = 0x%08x\n", (u32)sdmac->watermark_level);
805 dev_dbg(sdma->dev, "shp_addr = 0x%08x\n", sdmac->shp_addr);
806 dev_dbg(sdma->dev, "per_addr = 0x%08x\n", sdmac->per_addr);
807 dev_dbg(sdma->dev, "event_mask0 = 0x%08x\n", (u32)sdmac->event_mask[0]);
808 dev_dbg(sdma->dev, "event_mask1 = 0x%08x\n", (u32)sdmac->event_mask[1]);
809
810 spin_lock_irqsave(&sdma->channel_0_lock, flags);
811
812 memset(context, 0, sizeof(*context));
813 context->channel_state.pc = load_address;
814
815 /* Send by context the event mask,base address for peripheral
816 * and watermark level
817 */
818 context->gReg[0] = sdmac->event_mask[1];
819 context->gReg[1] = sdmac->event_mask[0];
820 context->gReg[2] = sdmac->per_addr;
821 context->gReg[6] = sdmac->shp_addr;
822 context->gReg[7] = sdmac->watermark_level;
823
824 bd0->mode.command = C0_SETDM;
825 bd0->mode.status = BD_DONE | BD_INTR | BD_WRAP | BD_EXTD;
826 bd0->mode.count = sizeof(*context) / 4;
827 bd0->buffer_addr = sdma->context_phys;
828 bd0->ext_buffer_addr = 2048 + (sizeof(*context) / 4) * channel;
829 ret = sdma_run_channel0(sdma);
830
831 spin_unlock_irqrestore(&sdma->channel_0_lock, flags);
832
833 return ret;
834 }
835
sdma_disable_channel(struct sdma_channel * sdmac)836 static void sdma_disable_channel(struct sdma_channel *sdmac)
837 {
838 struct sdma_engine *sdma = sdmac->sdma;
839 int channel = sdmac->channel;
840
841 writel_relaxed(BIT(channel), sdma->regs + SDMA_H_STATSTOP);
842 sdmac->status = DMA_ERROR;
843 }
844
sdma_config_channel(struct sdma_channel * sdmac)845 static int sdma_config_channel(struct sdma_channel *sdmac)
846 {
847 int ret;
848
849 sdma_disable_channel(sdmac);
850
851 sdmac->event_mask[0] = 0;
852 sdmac->event_mask[1] = 0;
853 sdmac->shp_addr = 0;
854 sdmac->per_addr = 0;
855
856 if (sdmac->event_id0) {
857 if (sdmac->event_id0 >= sdmac->sdma->drvdata->num_events)
858 return -EINVAL;
859 sdma_event_enable(sdmac, sdmac->event_id0);
860 }
861
862 switch (sdmac->peripheral_type) {
863 case IMX_DMATYPE_DSP:
864 sdma_config_ownership(sdmac, false, true, true);
865 break;
866 case IMX_DMATYPE_MEMORY:
867 sdma_config_ownership(sdmac, false, true, false);
868 break;
869 default:
870 sdma_config_ownership(sdmac, true, true, false);
871 break;
872 }
873
874 sdma_get_pc(sdmac, sdmac->peripheral_type);
875
876 if ((sdmac->peripheral_type != IMX_DMATYPE_MEMORY) &&
877 (sdmac->peripheral_type != IMX_DMATYPE_DSP)) {
878 /* Handle multiple event channels differently */
879 if (sdmac->event_id1) {
880 sdmac->event_mask[1] = BIT(sdmac->event_id1 % 32);
881 if (sdmac->event_id1 > 31)
882 __set_bit(31, &sdmac->watermark_level);
883 sdmac->event_mask[0] = BIT(sdmac->event_id0 % 32);
884 if (sdmac->event_id0 > 31)
885 __set_bit(30, &sdmac->watermark_level);
886 } else {
887 __set_bit(sdmac->event_id0, sdmac->event_mask);
888 }
889 /* Watermark Level */
890 sdmac->watermark_level |= sdmac->watermark_level;
891 /* Address */
892 sdmac->shp_addr = sdmac->per_address;
893 } else {
894 sdmac->watermark_level = 0; /* FIXME: M3_BASE_ADDRESS */
895 }
896
897 ret = sdma_load_context(sdmac);
898
899 return ret;
900 }
901
sdma_set_channel_priority(struct sdma_channel * sdmac,unsigned int priority)902 static int sdma_set_channel_priority(struct sdma_channel *sdmac,
903 unsigned int priority)
904 {
905 struct sdma_engine *sdma = sdmac->sdma;
906 int channel = sdmac->channel;
907
908 if (priority < MXC_SDMA_MIN_PRIORITY
909 || priority > MXC_SDMA_MAX_PRIORITY) {
910 return -EINVAL;
911 }
912
913 writel_relaxed(priority, sdma->regs + SDMA_CHNPRI_0 + 4 * channel);
914
915 return 0;
916 }
917
sdma_request_channel(struct sdma_channel * sdmac)918 static int sdma_request_channel(struct sdma_channel *sdmac)
919 {
920 struct sdma_engine *sdma = sdmac->sdma;
921 int channel = sdmac->channel;
922 int ret = -EBUSY;
923
924 sdmac->bd = dma_zalloc_coherent(NULL, PAGE_SIZE, &sdmac->bd_phys,
925 GFP_KERNEL);
926 if (!sdmac->bd) {
927 ret = -ENOMEM;
928 goto out;
929 }
930
931 sdma->channel_control[channel].base_bd_ptr = sdmac->bd_phys;
932 sdma->channel_control[channel].current_bd_ptr = sdmac->bd_phys;
933
934 sdma_set_channel_priority(sdmac, MXC_SDMA_DEFAULT_PRIORITY);
935 return 0;
936 out:
937
938 return ret;
939 }
940
to_sdma_chan(struct dma_chan * chan)941 static struct sdma_channel *to_sdma_chan(struct dma_chan *chan)
942 {
943 return container_of(chan, struct sdma_channel, chan);
944 }
945
sdma_tx_submit(struct dma_async_tx_descriptor * tx)946 static dma_cookie_t sdma_tx_submit(struct dma_async_tx_descriptor *tx)
947 {
948 unsigned long flags;
949 struct sdma_channel *sdmac = to_sdma_chan(tx->chan);
950 dma_cookie_t cookie;
951
952 spin_lock_irqsave(&sdmac->lock, flags);
953
954 cookie = dma_cookie_assign(tx);
955
956 spin_unlock_irqrestore(&sdmac->lock, flags);
957
958 return cookie;
959 }
960
sdma_alloc_chan_resources(struct dma_chan * chan)961 static int sdma_alloc_chan_resources(struct dma_chan *chan)
962 {
963 struct sdma_channel *sdmac = to_sdma_chan(chan);
964 struct imx_dma_data *data = chan->private;
965 int prio, ret;
966
967 if (!data)
968 return -EINVAL;
969
970 switch (data->priority) {
971 case DMA_PRIO_HIGH:
972 prio = 3;
973 break;
974 case DMA_PRIO_MEDIUM:
975 prio = 2;
976 break;
977 case DMA_PRIO_LOW:
978 default:
979 prio = 1;
980 break;
981 }
982
983 sdmac->peripheral_type = data->peripheral_type;
984 sdmac->event_id0 = data->dma_request;
985
986 clk_enable(sdmac->sdma->clk_ipg);
987 clk_enable(sdmac->sdma->clk_ahb);
988
989 ret = sdma_request_channel(sdmac);
990 if (ret)
991 return ret;
992
993 ret = sdma_set_channel_priority(sdmac, prio);
994 if (ret)
995 return ret;
996
997 dma_async_tx_descriptor_init(&sdmac->desc, chan);
998 sdmac->desc.tx_submit = sdma_tx_submit;
999 /* txd.flags will be overwritten in prep funcs */
1000 sdmac->desc.flags = DMA_CTRL_ACK;
1001
1002 return 0;
1003 }
1004
sdma_free_chan_resources(struct dma_chan * chan)1005 static void sdma_free_chan_resources(struct dma_chan *chan)
1006 {
1007 struct sdma_channel *sdmac = to_sdma_chan(chan);
1008 struct sdma_engine *sdma = sdmac->sdma;
1009
1010 sdma_disable_channel(sdmac);
1011
1012 if (sdmac->event_id0)
1013 sdma_event_disable(sdmac, sdmac->event_id0);
1014 if (sdmac->event_id1)
1015 sdma_event_disable(sdmac, sdmac->event_id1);
1016
1017 sdmac->event_id0 = 0;
1018 sdmac->event_id1 = 0;
1019
1020 sdma_set_channel_priority(sdmac, 0);
1021
1022 dma_free_coherent(NULL, PAGE_SIZE, sdmac->bd, sdmac->bd_phys);
1023
1024 clk_disable(sdma->clk_ipg);
1025 clk_disable(sdma->clk_ahb);
1026 }
1027
sdma_prep_slave_sg(struct dma_chan * chan,struct scatterlist * sgl,unsigned int sg_len,enum dma_transfer_direction direction,unsigned long flags,void * context)1028 static struct dma_async_tx_descriptor *sdma_prep_slave_sg(
1029 struct dma_chan *chan, struct scatterlist *sgl,
1030 unsigned int sg_len, enum dma_transfer_direction direction,
1031 unsigned long flags, void *context)
1032 {
1033 struct sdma_channel *sdmac = to_sdma_chan(chan);
1034 struct sdma_engine *sdma = sdmac->sdma;
1035 int ret, i, count;
1036 int channel = sdmac->channel;
1037 struct scatterlist *sg;
1038
1039 if (sdmac->status == DMA_IN_PROGRESS)
1040 return NULL;
1041 sdmac->status = DMA_IN_PROGRESS;
1042
1043 sdmac->flags = 0;
1044
1045 sdmac->buf_tail = 0;
1046
1047 dev_dbg(sdma->dev, "setting up %d entries for channel %d.\n",
1048 sg_len, channel);
1049
1050 sdmac->direction = direction;
1051 ret = sdma_load_context(sdmac);
1052 if (ret)
1053 goto err_out;
1054
1055 if (sg_len > NUM_BD) {
1056 dev_err(sdma->dev, "SDMA channel %d: maximum number of sg exceeded: %d > %d\n",
1057 channel, sg_len, NUM_BD);
1058 ret = -EINVAL;
1059 goto err_out;
1060 }
1061
1062 sdmac->chn_count = 0;
1063 for_each_sg(sgl, sg, sg_len, i) {
1064 struct sdma_buffer_descriptor *bd = &sdmac->bd[i];
1065 int param;
1066
1067 bd->buffer_addr = sg->dma_address;
1068
1069 count = sg_dma_len(sg);
1070
1071 if (count > 0xffff) {
1072 dev_err(sdma->dev, "SDMA channel %d: maximum bytes for sg entry exceeded: %d > %d\n",
1073 channel, count, 0xffff);
1074 ret = -EINVAL;
1075 goto err_out;
1076 }
1077
1078 bd->mode.count = count;
1079 sdmac->chn_count += count;
1080
1081 if (sdmac->word_size > DMA_SLAVE_BUSWIDTH_4_BYTES) {
1082 ret = -EINVAL;
1083 goto err_out;
1084 }
1085
1086 switch (sdmac->word_size) {
1087 case DMA_SLAVE_BUSWIDTH_4_BYTES:
1088 bd->mode.command = 0;
1089 if (count & 3 || sg->dma_address & 3)
1090 return NULL;
1091 break;
1092 case DMA_SLAVE_BUSWIDTH_2_BYTES:
1093 bd->mode.command = 2;
1094 if (count & 1 || sg->dma_address & 1)
1095 return NULL;
1096 break;
1097 case DMA_SLAVE_BUSWIDTH_1_BYTE:
1098 bd->mode.command = 1;
1099 break;
1100 default:
1101 return NULL;
1102 }
1103
1104 param = BD_DONE | BD_EXTD | BD_CONT;
1105
1106 if (i + 1 == sg_len) {
1107 param |= BD_INTR;
1108 param |= BD_LAST;
1109 param &= ~BD_CONT;
1110 }
1111
1112 dev_dbg(sdma->dev, "entry %d: count: %d dma: %#llx %s%s\n",
1113 i, count, (u64)sg->dma_address,
1114 param & BD_WRAP ? "wrap" : "",
1115 param & BD_INTR ? " intr" : "");
1116
1117 bd->mode.status = param;
1118 }
1119
1120 sdmac->num_bd = sg_len;
1121 sdma->channel_control[channel].current_bd_ptr = sdmac->bd_phys;
1122
1123 return &sdmac->desc;
1124 err_out:
1125 sdmac->status = DMA_ERROR;
1126 return NULL;
1127 }
1128
sdma_prep_dma_cyclic(struct dma_chan * chan,dma_addr_t dma_addr,size_t buf_len,size_t period_len,enum dma_transfer_direction direction,unsigned long flags)1129 static struct dma_async_tx_descriptor *sdma_prep_dma_cyclic(
1130 struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len,
1131 size_t period_len, enum dma_transfer_direction direction,
1132 unsigned long flags)
1133 {
1134 struct sdma_channel *sdmac = to_sdma_chan(chan);
1135 struct sdma_engine *sdma = sdmac->sdma;
1136 int num_periods = buf_len / period_len;
1137 int channel = sdmac->channel;
1138 int ret, i = 0, buf = 0;
1139
1140 dev_dbg(sdma->dev, "%s channel: %d\n", __func__, channel);
1141
1142 if (sdmac->status == DMA_IN_PROGRESS)
1143 return NULL;
1144
1145 sdmac->status = DMA_IN_PROGRESS;
1146
1147 sdmac->buf_tail = 0;
1148 sdmac->period_len = period_len;
1149
1150 sdmac->flags |= IMX_DMA_SG_LOOP;
1151 sdmac->direction = direction;
1152 ret = sdma_load_context(sdmac);
1153 if (ret)
1154 goto err_out;
1155
1156 if (num_periods > NUM_BD) {
1157 dev_err(sdma->dev, "SDMA channel %d: maximum number of sg exceeded: %d > %d\n",
1158 channel, num_periods, NUM_BD);
1159 goto err_out;
1160 }
1161
1162 if (period_len > 0xffff) {
1163 dev_err(sdma->dev, "SDMA channel %d: maximum period size exceeded: %d > %d\n",
1164 channel, period_len, 0xffff);
1165 goto err_out;
1166 }
1167
1168 while (buf < buf_len) {
1169 struct sdma_buffer_descriptor *bd = &sdmac->bd[i];
1170 int param;
1171
1172 bd->buffer_addr = dma_addr;
1173
1174 bd->mode.count = period_len;
1175
1176 if (sdmac->word_size > DMA_SLAVE_BUSWIDTH_4_BYTES)
1177 goto err_out;
1178 if (sdmac->word_size == DMA_SLAVE_BUSWIDTH_4_BYTES)
1179 bd->mode.command = 0;
1180 else
1181 bd->mode.command = sdmac->word_size;
1182
1183 param = BD_DONE | BD_EXTD | BD_CONT | BD_INTR;
1184 if (i + 1 == num_periods)
1185 param |= BD_WRAP;
1186
1187 dev_dbg(sdma->dev, "entry %d: count: %d dma: %#llx %s%s\n",
1188 i, period_len, (u64)dma_addr,
1189 param & BD_WRAP ? "wrap" : "",
1190 param & BD_INTR ? " intr" : "");
1191
1192 bd->mode.status = param;
1193
1194 dma_addr += period_len;
1195 buf += period_len;
1196
1197 i++;
1198 }
1199
1200 sdmac->num_bd = num_periods;
1201 sdma->channel_control[channel].current_bd_ptr = sdmac->bd_phys;
1202
1203 return &sdmac->desc;
1204 err_out:
1205 sdmac->status = DMA_ERROR;
1206 return NULL;
1207 }
1208
sdma_control(struct dma_chan * chan,enum dma_ctrl_cmd cmd,unsigned long arg)1209 static int sdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
1210 unsigned long arg)
1211 {
1212 struct sdma_channel *sdmac = to_sdma_chan(chan);
1213 struct dma_slave_config *dmaengine_cfg = (void *)arg;
1214
1215 switch (cmd) {
1216 case DMA_TERMINATE_ALL:
1217 sdma_disable_channel(sdmac);
1218 return 0;
1219 case DMA_SLAVE_CONFIG:
1220 if (dmaengine_cfg->direction == DMA_DEV_TO_MEM) {
1221 sdmac->per_address = dmaengine_cfg->src_addr;
1222 sdmac->watermark_level = dmaengine_cfg->src_maxburst *
1223 dmaengine_cfg->src_addr_width;
1224 sdmac->word_size = dmaengine_cfg->src_addr_width;
1225 } else {
1226 sdmac->per_address = dmaengine_cfg->dst_addr;
1227 sdmac->watermark_level = dmaengine_cfg->dst_maxburst *
1228 dmaengine_cfg->dst_addr_width;
1229 sdmac->word_size = dmaengine_cfg->dst_addr_width;
1230 }
1231 sdmac->direction = dmaengine_cfg->direction;
1232 return sdma_config_channel(sdmac);
1233 default:
1234 return -ENOSYS;
1235 }
1236
1237 return -EINVAL;
1238 }
1239
sdma_tx_status(struct dma_chan * chan,dma_cookie_t cookie,struct dma_tx_state * txstate)1240 static enum dma_status sdma_tx_status(struct dma_chan *chan,
1241 dma_cookie_t cookie,
1242 struct dma_tx_state *txstate)
1243 {
1244 struct sdma_channel *sdmac = to_sdma_chan(chan);
1245 u32 residue;
1246
1247 if (sdmac->flags & IMX_DMA_SG_LOOP)
1248 residue = (sdmac->num_bd - sdmac->buf_tail) * sdmac->period_len;
1249 else
1250 residue = sdmac->chn_count - sdmac->chn_real_count;
1251
1252 dma_set_tx_state(txstate, chan->completed_cookie, chan->cookie,
1253 residue);
1254
1255 return sdmac->status;
1256 }
1257
sdma_issue_pending(struct dma_chan * chan)1258 static void sdma_issue_pending(struct dma_chan *chan)
1259 {
1260 struct sdma_channel *sdmac = to_sdma_chan(chan);
1261 struct sdma_engine *sdma = sdmac->sdma;
1262
1263 if (sdmac->status == DMA_IN_PROGRESS)
1264 sdma_enable_channel(sdma, sdmac->channel);
1265 }
1266
1267 #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1 34
1268 #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V2 38
1269
sdma_add_scripts(struct sdma_engine * sdma,const struct sdma_script_start_addrs * addr)1270 static void sdma_add_scripts(struct sdma_engine *sdma,
1271 const struct sdma_script_start_addrs *addr)
1272 {
1273 s32 *addr_arr = (u32 *)addr;
1274 s32 *saddr_arr = (u32 *)sdma->script_addrs;
1275 int i;
1276
1277 /* use the default firmware in ROM if missing external firmware */
1278 if (!sdma->script_number)
1279 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1;
1280
1281 for (i = 0; i < sdma->script_number; i++)
1282 if (addr_arr[i] > 0)
1283 saddr_arr[i] = addr_arr[i];
1284 }
1285
sdma_load_firmware(const struct firmware * fw,void * context)1286 static void sdma_load_firmware(const struct firmware *fw, void *context)
1287 {
1288 struct sdma_engine *sdma = context;
1289 const struct sdma_firmware_header *header;
1290 const struct sdma_script_start_addrs *addr;
1291 unsigned short *ram_code;
1292
1293 if (!fw) {
1294 dev_err(sdma->dev, "firmware not found\n");
1295 return;
1296 }
1297
1298 if (fw->size < sizeof(*header))
1299 goto err_firmware;
1300
1301 header = (struct sdma_firmware_header *)fw->data;
1302
1303 if (header->magic != SDMA_FIRMWARE_MAGIC)
1304 goto err_firmware;
1305 if (header->ram_code_start + header->ram_code_size > fw->size)
1306 goto err_firmware;
1307 switch (header->version_major) {
1308 case 1:
1309 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1;
1310 break;
1311 case 2:
1312 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V2;
1313 break;
1314 default:
1315 dev_err(sdma->dev, "unknown firmware version\n");
1316 goto err_firmware;
1317 }
1318
1319 addr = (void *)header + header->script_addrs_start;
1320 ram_code = (void *)header + header->ram_code_start;
1321
1322 clk_enable(sdma->clk_ipg);
1323 clk_enable(sdma->clk_ahb);
1324 /* download the RAM image for SDMA */
1325 sdma_load_script(sdma, ram_code,
1326 header->ram_code_size,
1327 addr->ram_code_start_addr);
1328 clk_disable(sdma->clk_ipg);
1329 clk_disable(sdma->clk_ahb);
1330
1331 sdma_add_scripts(sdma, addr);
1332
1333 dev_info(sdma->dev, "loaded firmware %d.%d\n",
1334 header->version_major,
1335 header->version_minor);
1336
1337 err_firmware:
1338 release_firmware(fw);
1339 }
1340
sdma_get_firmware(struct sdma_engine * sdma,const char * fw_name)1341 static int sdma_get_firmware(struct sdma_engine *sdma,
1342 const char *fw_name)
1343 {
1344 int ret;
1345
1346 ret = request_firmware_nowait(THIS_MODULE,
1347 FW_ACTION_HOTPLUG, fw_name, sdma->dev,
1348 GFP_KERNEL, sdma, sdma_load_firmware);
1349
1350 return ret;
1351 }
1352
sdma_init(struct sdma_engine * sdma)1353 static int __init sdma_init(struct sdma_engine *sdma)
1354 {
1355 int i, ret;
1356 dma_addr_t ccb_phys;
1357
1358 clk_enable(sdma->clk_ipg);
1359 clk_enable(sdma->clk_ahb);
1360
1361 /* Be sure SDMA has not started yet */
1362 writel_relaxed(0, sdma->regs + SDMA_H_C0PTR);
1363
1364 sdma->channel_control = dma_alloc_coherent(NULL,
1365 MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control) +
1366 sizeof(struct sdma_context_data),
1367 &ccb_phys, GFP_KERNEL);
1368
1369 if (!sdma->channel_control) {
1370 ret = -ENOMEM;
1371 goto err_dma_alloc;
1372 }
1373
1374 sdma->context = (void *)sdma->channel_control +
1375 MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control);
1376 sdma->context_phys = ccb_phys +
1377 MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control);
1378
1379 /* Zero-out the CCB structures array just allocated */
1380 memset(sdma->channel_control, 0,
1381 MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control));
1382
1383 /* disable all channels */
1384 for (i = 0; i < sdma->drvdata->num_events; i++)
1385 writel_relaxed(0, sdma->regs + chnenbl_ofs(sdma, i));
1386
1387 /* All channels have priority 0 */
1388 for (i = 0; i < MAX_DMA_CHANNELS; i++)
1389 writel_relaxed(0, sdma->regs + SDMA_CHNPRI_0 + i * 4);
1390
1391 ret = sdma_request_channel(&sdma->channel[0]);
1392 if (ret)
1393 goto err_dma_alloc;
1394
1395 sdma_config_ownership(&sdma->channel[0], false, true, false);
1396
1397 /* Set Command Channel (Channel Zero) */
1398 writel_relaxed(0x4050, sdma->regs + SDMA_CHN0ADDR);
1399
1400 /* Set bits of CONFIG register but with static context switching */
1401 /* FIXME: Check whether to set ACR bit depending on clock ratios */
1402 writel_relaxed(0, sdma->regs + SDMA_H_CONFIG);
1403
1404 writel_relaxed(ccb_phys, sdma->regs + SDMA_H_C0PTR);
1405
1406 /* Initializes channel's priorities */
1407 sdma_set_channel_priority(&sdma->channel[0], 7);
1408
1409 clk_disable(sdma->clk_ipg);
1410 clk_disable(sdma->clk_ahb);
1411
1412 return 0;
1413
1414 err_dma_alloc:
1415 clk_disable(sdma->clk_ipg);
1416 clk_disable(sdma->clk_ahb);
1417 dev_err(sdma->dev, "initialisation failed with %d\n", ret);
1418 return ret;
1419 }
1420
sdma_filter_fn(struct dma_chan * chan,void * fn_param)1421 static bool sdma_filter_fn(struct dma_chan *chan, void *fn_param)
1422 {
1423 struct sdma_channel *sdmac = to_sdma_chan(chan);
1424 struct imx_dma_data *data = fn_param;
1425
1426 if (!imx_dma_is_general_purpose(chan))
1427 return false;
1428
1429 sdmac->data = *data;
1430 chan->private = &sdmac->data;
1431
1432 return true;
1433 }
1434
sdma_xlate(struct of_phandle_args * dma_spec,struct of_dma * ofdma)1435 static struct dma_chan *sdma_xlate(struct of_phandle_args *dma_spec,
1436 struct of_dma *ofdma)
1437 {
1438 struct sdma_engine *sdma = ofdma->of_dma_data;
1439 dma_cap_mask_t mask = sdma->dma_device.cap_mask;
1440 struct imx_dma_data data;
1441
1442 if (dma_spec->args_count != 3)
1443 return NULL;
1444
1445 data.dma_request = dma_spec->args[0];
1446 data.peripheral_type = dma_spec->args[1];
1447 data.priority = dma_spec->args[2];
1448
1449 return dma_request_channel(mask, sdma_filter_fn, &data);
1450 }
1451
sdma_probe(struct platform_device * pdev)1452 static int sdma_probe(struct platform_device *pdev)
1453 {
1454 const struct of_device_id *of_id =
1455 of_match_device(sdma_dt_ids, &pdev->dev);
1456 struct device_node *np = pdev->dev.of_node;
1457 const char *fw_name;
1458 int ret;
1459 int irq;
1460 struct resource *iores;
1461 struct sdma_platform_data *pdata = dev_get_platdata(&pdev->dev);
1462 int i;
1463 struct sdma_engine *sdma;
1464 s32 *saddr_arr;
1465 const struct sdma_driver_data *drvdata = NULL;
1466
1467 if (of_id)
1468 drvdata = of_id->data;
1469 else if (pdev->id_entry)
1470 drvdata = (void *)pdev->id_entry->driver_data;
1471
1472 if (!drvdata) {
1473 dev_err(&pdev->dev, "unable to find driver data\n");
1474 return -EINVAL;
1475 }
1476
1477 ret = dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
1478 if (ret)
1479 return ret;
1480
1481 sdma = kzalloc(sizeof(*sdma), GFP_KERNEL);
1482 if (!sdma)
1483 return -ENOMEM;
1484
1485 spin_lock_init(&sdma->channel_0_lock);
1486
1487 sdma->dev = &pdev->dev;
1488 sdma->drvdata = drvdata;
1489
1490 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1491 irq = platform_get_irq(pdev, 0);
1492 if (!iores || irq < 0) {
1493 ret = -EINVAL;
1494 goto err_irq;
1495 }
1496
1497 if (!request_mem_region(iores->start, resource_size(iores), pdev->name)) {
1498 ret = -EBUSY;
1499 goto err_request_region;
1500 }
1501
1502 sdma->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1503 if (IS_ERR(sdma->clk_ipg)) {
1504 ret = PTR_ERR(sdma->clk_ipg);
1505 goto err_clk;
1506 }
1507
1508 sdma->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
1509 if (IS_ERR(sdma->clk_ahb)) {
1510 ret = PTR_ERR(sdma->clk_ahb);
1511 goto err_clk;
1512 }
1513
1514 clk_prepare(sdma->clk_ipg);
1515 clk_prepare(sdma->clk_ahb);
1516
1517 sdma->regs = ioremap(iores->start, resource_size(iores));
1518 if (!sdma->regs) {
1519 ret = -ENOMEM;
1520 goto err_ioremap;
1521 }
1522
1523 ret = request_irq(irq, sdma_int_handler, 0, "sdma", sdma);
1524 if (ret)
1525 goto err_request_irq;
1526
1527 sdma->script_addrs = kzalloc(sizeof(*sdma->script_addrs), GFP_KERNEL);
1528 if (!sdma->script_addrs) {
1529 ret = -ENOMEM;
1530 goto err_alloc;
1531 }
1532
1533 /* initially no scripts available */
1534 saddr_arr = (s32 *)sdma->script_addrs;
1535 for (i = 0; i < SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1; i++)
1536 saddr_arr[i] = -EINVAL;
1537
1538 dma_cap_set(DMA_SLAVE, sdma->dma_device.cap_mask);
1539 dma_cap_set(DMA_CYCLIC, sdma->dma_device.cap_mask);
1540
1541 INIT_LIST_HEAD(&sdma->dma_device.channels);
1542 /* Initialize channel parameters */
1543 for (i = 0; i < MAX_DMA_CHANNELS; i++) {
1544 struct sdma_channel *sdmac = &sdma->channel[i];
1545
1546 sdmac->sdma = sdma;
1547 spin_lock_init(&sdmac->lock);
1548
1549 sdmac->chan.device = &sdma->dma_device;
1550 dma_cookie_init(&sdmac->chan);
1551 sdmac->channel = i;
1552
1553 tasklet_init(&sdmac->tasklet, sdma_tasklet,
1554 (unsigned long) sdmac);
1555 /*
1556 * Add the channel to the DMAC list. Do not add channel 0 though
1557 * because we need it internally in the SDMA driver. This also means
1558 * that channel 0 in dmaengine counting matches sdma channel 1.
1559 */
1560 if (i)
1561 list_add_tail(&sdmac->chan.device_node,
1562 &sdma->dma_device.channels);
1563 }
1564
1565 ret = sdma_init(sdma);
1566 if (ret)
1567 goto err_init;
1568
1569 if (sdma->drvdata->script_addrs)
1570 sdma_add_scripts(sdma, sdma->drvdata->script_addrs);
1571 if (pdata && pdata->script_addrs)
1572 sdma_add_scripts(sdma, pdata->script_addrs);
1573
1574 if (pdata) {
1575 ret = sdma_get_firmware(sdma, pdata->fw_name);
1576 if (ret)
1577 dev_warn(&pdev->dev, "failed to get firmware from platform data\n");
1578 } else {
1579 /*
1580 * Because that device tree does not encode ROM script address,
1581 * the RAM script in firmware is mandatory for device tree
1582 * probe, otherwise it fails.
1583 */
1584 ret = of_property_read_string(np, "fsl,sdma-ram-script-name",
1585 &fw_name);
1586 if (ret)
1587 dev_warn(&pdev->dev, "failed to get firmware name\n");
1588 else {
1589 ret = sdma_get_firmware(sdma, fw_name);
1590 if (ret)
1591 dev_warn(&pdev->dev, "failed to get firmware from device tree\n");
1592 }
1593 }
1594
1595 sdma->dma_device.dev = &pdev->dev;
1596
1597 sdma->dma_device.device_alloc_chan_resources = sdma_alloc_chan_resources;
1598 sdma->dma_device.device_free_chan_resources = sdma_free_chan_resources;
1599 sdma->dma_device.device_tx_status = sdma_tx_status;
1600 sdma->dma_device.device_prep_slave_sg = sdma_prep_slave_sg;
1601 sdma->dma_device.device_prep_dma_cyclic = sdma_prep_dma_cyclic;
1602 sdma->dma_device.device_control = sdma_control;
1603 sdma->dma_device.device_issue_pending = sdma_issue_pending;
1604 sdma->dma_device.dev->dma_parms = &sdma->dma_parms;
1605 dma_set_max_seg_size(sdma->dma_device.dev, 65535);
1606
1607 platform_set_drvdata(pdev, sdma);
1608
1609 ret = dma_async_device_register(&sdma->dma_device);
1610 if (ret) {
1611 dev_err(&pdev->dev, "unable to register\n");
1612 goto err_init;
1613 }
1614
1615 if (np) {
1616 ret = of_dma_controller_register(np, sdma_xlate, sdma);
1617 if (ret) {
1618 dev_err(&pdev->dev, "failed to register controller\n");
1619 goto err_register;
1620 }
1621 }
1622
1623 dev_info(sdma->dev, "initialized\n");
1624
1625 return 0;
1626
1627 err_register:
1628 dma_async_device_unregister(&sdma->dma_device);
1629 err_init:
1630 kfree(sdma->script_addrs);
1631 err_alloc:
1632 free_irq(irq, sdma);
1633 err_request_irq:
1634 iounmap(sdma->regs);
1635 err_ioremap:
1636 err_clk:
1637 release_mem_region(iores->start, resource_size(iores));
1638 err_request_region:
1639 err_irq:
1640 kfree(sdma);
1641 return ret;
1642 }
1643
sdma_remove(struct platform_device * pdev)1644 static int sdma_remove(struct platform_device *pdev)
1645 {
1646 struct sdma_engine *sdma = platform_get_drvdata(pdev);
1647 struct resource *iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1648 int irq = platform_get_irq(pdev, 0);
1649 int i;
1650
1651 dma_async_device_unregister(&sdma->dma_device);
1652 kfree(sdma->script_addrs);
1653 free_irq(irq, sdma);
1654 iounmap(sdma->regs);
1655 release_mem_region(iores->start, resource_size(iores));
1656 /* Kill the tasklet */
1657 for (i = 0; i < MAX_DMA_CHANNELS; i++) {
1658 struct sdma_channel *sdmac = &sdma->channel[i];
1659
1660 tasklet_kill(&sdmac->tasklet);
1661 }
1662 kfree(sdma);
1663
1664 platform_set_drvdata(pdev, NULL);
1665 dev_info(&pdev->dev, "Removed...\n");
1666 return 0;
1667 }
1668
1669 static struct platform_driver sdma_driver = {
1670 .driver = {
1671 .name = "imx-sdma",
1672 .of_match_table = sdma_dt_ids,
1673 },
1674 .id_table = sdma_devtypes,
1675 .remove = sdma_remove,
1676 .probe = sdma_probe,
1677 };
1678
1679 module_platform_driver(sdma_driver);
1680
1681 MODULE_AUTHOR("Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>");
1682 MODULE_DESCRIPTION("i.MX SDMA driver");
1683 MODULE_LICENSE("GPL");
1684