1 #ifndef __NVKM_DISP_DPORT_H__ 2 #define __NVKM_DISP_DPORT_H__ 3 4 /* DPCD Receiver Capabilities */ 5 #define DPCD_RC00_DPCD_REV 0x00000 6 #define DPCD_RC01_MAX_LINK_RATE 0x00001 7 #define DPCD_RC02 0x00002 8 #define DPCD_RC02_ENHANCED_FRAME_CAP 0x80 9 #define DPCD_RC02_TPS3_SUPPORTED 0x40 10 #define DPCD_RC02_MAX_LANE_COUNT 0x1f 11 #define DPCD_RC03 0x00003 12 #define DPCD_RC03_MAX_DOWNSPREAD 0x01 13 #define DPCD_RC0E_AUX_RD_INTERVAL 0x0000e 14 15 /* DPCD Link Configuration */ 16 #define DPCD_LC00_LINK_BW_SET 0x00100 17 #define DPCD_LC01 0x00101 18 #define DPCD_LC01_ENHANCED_FRAME_EN 0x80 19 #define DPCD_LC01_LANE_COUNT_SET 0x1f 20 #define DPCD_LC02 0x00102 21 #define DPCD_LC02_TRAINING_PATTERN_SET 0x03 22 #define DPCD_LC03(l) ((l) + 0x00103) 23 #define DPCD_LC03_MAX_PRE_EMPHASIS_REACHED 0x20 24 #define DPCD_LC03_PRE_EMPHASIS_SET 0x18 25 #define DPCD_LC03_MAX_SWING_REACHED 0x04 26 #define DPCD_LC03_VOLTAGE_SWING_SET 0x03 27 #define DPCD_LC0F 0x0010f 28 #define DPCD_LC0F_LANE1_MAX_POST_CURSOR2_REACHED 0x40 29 #define DPCD_LC0F_LANE1_POST_CURSOR2_SET 0x30 30 #define DPCD_LC0F_LANE0_MAX_POST_CURSOR2_REACHED 0x04 31 #define DPCD_LC0F_LANE0_POST_CURSOR2_SET 0x03 32 #define DPCD_LC10 0x00110 33 #define DPCD_LC10_LANE3_MAX_POST_CURSOR2_REACHED 0x40 34 #define DPCD_LC10_LANE3_POST_CURSOR2_SET 0x30 35 #define DPCD_LC10_LANE2_MAX_POST_CURSOR2_REACHED 0x04 36 #define DPCD_LC10_LANE2_POST_CURSOR2_SET 0x03 37 38 /* DPCD Link/Sink Status */ 39 #define DPCD_LS02 0x00202 40 #define DPCD_LS02_LANE1_SYMBOL_LOCKED 0x40 41 #define DPCD_LS02_LANE1_CHANNEL_EQ_DONE 0x20 42 #define DPCD_LS02_LANE1_CR_DONE 0x10 43 #define DPCD_LS02_LANE0_SYMBOL_LOCKED 0x04 44 #define DPCD_LS02_LANE0_CHANNEL_EQ_DONE 0x02 45 #define DPCD_LS02_LANE0_CR_DONE 0x01 46 #define DPCD_LS03 0x00203 47 #define DPCD_LS03_LANE3_SYMBOL_LOCKED 0x40 48 #define DPCD_LS03_LANE3_CHANNEL_EQ_DONE 0x20 49 #define DPCD_LS03_LANE3_CR_DONE 0x10 50 #define DPCD_LS03_LANE2_SYMBOL_LOCKED 0x04 51 #define DPCD_LS03_LANE2_CHANNEL_EQ_DONE 0x02 52 #define DPCD_LS03_LANE2_CR_DONE 0x01 53 #define DPCD_LS04 0x00204 54 #define DPCD_LS04_LINK_STATUS_UPDATED 0x80 55 #define DPCD_LS04_DOWNSTREAM_PORT_STATUS_CHANGED 0x40 56 #define DPCD_LS04_INTERLANE_ALIGN_DONE 0x01 57 #define DPCD_LS06 0x00206 58 #define DPCD_LS06_LANE1_PRE_EMPHASIS 0xc0 59 #define DPCD_LS06_LANE1_VOLTAGE_SWING 0x30 60 #define DPCD_LS06_LANE0_PRE_EMPHASIS 0x0c 61 #define DPCD_LS06_LANE0_VOLTAGE_SWING 0x03 62 #define DPCD_LS07 0x00207 63 #define DPCD_LS07_LANE3_PRE_EMPHASIS 0xc0 64 #define DPCD_LS07_LANE3_VOLTAGE_SWING 0x30 65 #define DPCD_LS07_LANE2_PRE_EMPHASIS 0x0c 66 #define DPCD_LS07_LANE2_VOLTAGE_SWING 0x03 67 #define DPCD_LS0C 0x0020c 68 #define DPCD_LS0C_LANE3_POST_CURSOR2 0xc0 69 #define DPCD_LS0C_LANE2_POST_CURSOR2 0x30 70 #define DPCD_LS0C_LANE1_POST_CURSOR2 0x0c 71 #define DPCD_LS0C_LANE0_POST_CURSOR2 0x03 72 73 void nouveau_dp_train(struct work_struct *); 74 75 #endif 76