1 /*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
25 #include <engine/software.h>
26 #include <engine/disp.h>
27
28 #include <nvif/class.h>
29
30 #include "nv50.h"
31
32 /*******************************************************************************
33 * EVO overlay channel objects
34 ******************************************************************************/
35
36 static const struct nv50_disp_mthd_list
37 nva0_disp_ovly_mthd_base = {
38 .mthd = 0x0000,
39 .addr = 0x000000,
40 .data = {
41 { 0x0080, 0x000000 },
42 { 0x0084, 0x6109a0 },
43 { 0x0088, 0x6109c0 },
44 { 0x008c, 0x6109c8 },
45 { 0x0090, 0x6109b4 },
46 { 0x0094, 0x610970 },
47 { 0x00a0, 0x610998 },
48 { 0x00a4, 0x610964 },
49 { 0x00b0, 0x610c98 },
50 { 0x00b4, 0x610ca4 },
51 { 0x00b8, 0x610cac },
52 { 0x00c0, 0x610958 },
53 { 0x00e0, 0x6109a8 },
54 { 0x00e4, 0x6109d0 },
55 { 0x00e8, 0x6109d8 },
56 { 0x0100, 0x61094c },
57 { 0x0104, 0x610984 },
58 { 0x0108, 0x61098c },
59 { 0x0800, 0x6109f8 },
60 { 0x0808, 0x610a08 },
61 { 0x080c, 0x610a10 },
62 { 0x0810, 0x610a00 },
63 {}
64 }
65 };
66
67 static const struct nv50_disp_mthd_chan
68 nva0_disp_ovly_mthd_chan = {
69 .name = "Overlay",
70 .addr = 0x000540,
71 .data = {
72 { "Global", 1, &nva0_disp_ovly_mthd_base },
73 {}
74 }
75 };
76
77 /*******************************************************************************
78 * Base display object
79 ******************************************************************************/
80
81 static struct nouveau_oclass
82 nva0_disp_sclass[] = {
83 { GT200_DISP_CORE_CHANNEL_DMA, &nv50_disp_mast_ofuncs.base },
84 { GT200_DISP_BASE_CHANNEL_DMA, &nv50_disp_sync_ofuncs.base },
85 { GT200_DISP_OVERLAY_CHANNEL_DMA, &nv50_disp_ovly_ofuncs.base },
86 { G82_DISP_OVERLAY, &nv50_disp_oimm_ofuncs.base },
87 { G82_DISP_CURSOR, &nv50_disp_curs_ofuncs.base },
88 {}
89 };
90
91 static struct nouveau_oclass
92 nva0_disp_base_oclass[] = {
93 { GT200_DISP, &nv50_disp_base_ofuncs },
94 {}
95 };
96
97 /*******************************************************************************
98 * Display engine implementation
99 ******************************************************************************/
100
101 static int
nva0_disp_ctor(struct nouveau_object * parent,struct nouveau_object * engine,struct nouveau_oclass * oclass,void * data,u32 size,struct nouveau_object ** pobject)102 nva0_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
103 struct nouveau_oclass *oclass, void *data, u32 size,
104 struct nouveau_object **pobject)
105 {
106 struct nv50_disp_priv *priv;
107 int ret;
108
109 ret = nouveau_disp_create(parent, engine, oclass, 2, "PDISP",
110 "display", &priv);
111 *pobject = nv_object(priv);
112 if (ret)
113 return ret;
114
115 ret = nvkm_event_init(&nv50_disp_chan_uevent, 1, 9, &priv->uevent);
116 if (ret)
117 return ret;
118
119 nv_engine(priv)->sclass = nva0_disp_base_oclass;
120 nv_engine(priv)->cclass = &nv50_disp_cclass;
121 nv_subdev(priv)->intr = nv50_disp_intr;
122 INIT_WORK(&priv->supervisor, nv50_disp_intr_supervisor);
123 priv->sclass = nva0_disp_sclass;
124 priv->head.nr = 2;
125 priv->dac.nr = 3;
126 priv->sor.nr = 2;
127 priv->pior.nr = 3;
128 priv->dac.power = nv50_dac_power;
129 priv->dac.sense = nv50_dac_sense;
130 priv->sor.power = nv50_sor_power;
131 priv->sor.hdmi = nv84_hdmi_ctrl;
132 priv->pior.power = nv50_pior_power;
133 return 0;
134 }
135
136 struct nouveau_oclass *
137 nva0_disp_oclass = &(struct nv50_disp_impl) {
138 .base.base.handle = NV_ENGINE(DISP, 0x83),
139 .base.base.ofuncs = &(struct nouveau_ofuncs) {
140 .ctor = nva0_disp_ctor,
141 .dtor = _nouveau_disp_dtor,
142 .init = _nouveau_disp_init,
143 .fini = _nouveau_disp_fini,
144 },
145 .base.vblank = &nv50_disp_vblank_func,
146 .base.outp = nv50_disp_outp_sclass,
147 .mthd.core = &nv84_disp_mast_mthd_chan,
148 .mthd.base = &nv84_disp_sync_mthd_chan,
149 .mthd.ovly = &nva0_disp_ovly_mthd_chan,
150 .mthd.prev = 0x000004,
151 .head.scanoutpos = nv50_disp_base_scanoutpos,
152 }.base.base;
153