1 /*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
25 #include <core/object.h>
26 #include <core/client.h>
27 #include <nvif/unpack.h>
28 #include <nvif/class.h>
29
30 #include <subdev/fb.h>
31 #include <subdev/instmem.h>
32
33 #include "priv.h"
34
35 static int
nvkm_dmaobj_bind(struct nouveau_dmaobj * dmaobj,struct nouveau_object * parent,struct nouveau_gpuobj ** pgpuobj)36 nvkm_dmaobj_bind(struct nouveau_dmaobj *dmaobj, struct nouveau_object *parent,
37 struct nouveau_gpuobj **pgpuobj)
38 {
39 const struct nvkm_dmaeng_impl *impl = (void *)
40 nv_oclass(nv_object(dmaobj)->engine);
41 int ret = 0;
42
43 if (nv_object(dmaobj) == parent) { /* ctor bind */
44 if (nv_mclass(parent->parent) == NV_DEVICE) {
45 /* delayed, or no, binding */
46 return 0;
47 }
48 ret = impl->bind(dmaobj, parent, pgpuobj);
49 if (ret == 0)
50 nouveau_object_ref(NULL, &parent);
51 return ret;
52 }
53
54 return impl->bind(dmaobj, parent, pgpuobj);
55 }
56
57 int
nvkm_dmaobj_create_(struct nouveau_object * parent,struct nouveau_object * engine,struct nouveau_oclass * oclass,void ** pdata,u32 * psize,int length,void ** pobject)58 nvkm_dmaobj_create_(struct nouveau_object *parent,
59 struct nouveau_object *engine,
60 struct nouveau_oclass *oclass, void **pdata, u32 *psize,
61 int length, void **pobject)
62 {
63 union {
64 struct nv_dma_v0 v0;
65 } *args = *pdata;
66 struct nouveau_instmem *instmem = nouveau_instmem(parent);
67 struct nouveau_client *client = nouveau_client(parent);
68 struct nouveau_device *device = nv_device(parent);
69 struct nouveau_fb *pfb = nouveau_fb(parent);
70 struct nouveau_dmaobj *dmaobj;
71 void *data = *pdata;
72 u32 size = *psize;
73 int ret;
74
75 ret = nouveau_object_create_(parent, engine, oclass, 0, length, pobject);
76 dmaobj = *pobject;
77 if (ret)
78 return ret;
79
80 nv_ioctl(parent, "create dma size %d\n", *psize);
81 if (nvif_unpack(args->v0, 0, 0, true)) {
82 nv_ioctl(parent, "create dma vers %d target %d access %d "
83 "start %016llx limit %016llx\n",
84 args->v0.version, args->v0.target, args->v0.access,
85 args->v0.start, args->v0.limit);
86 dmaobj->target = args->v0.target;
87 dmaobj->access = args->v0.access;
88 dmaobj->start = args->v0.start;
89 dmaobj->limit = args->v0.limit;
90 } else
91 return ret;
92
93 *pdata = data;
94 *psize = size;
95
96 if (dmaobj->start > dmaobj->limit)
97 return -EINVAL;
98
99 switch (dmaobj->target) {
100 case NV_DMA_V0_TARGET_VM:
101 dmaobj->target = NV_MEM_TARGET_VM;
102 break;
103 case NV_DMA_V0_TARGET_VRAM:
104 if (!client->super) {
105 if (dmaobj->limit >= pfb->ram->size - instmem->reserved)
106 return -EACCES;
107 if (device->card_type >= NV_50)
108 return -EACCES;
109 }
110 dmaobj->target = NV_MEM_TARGET_VRAM;
111 break;
112 case NV_DMA_V0_TARGET_PCI:
113 if (!client->super)
114 return -EACCES;
115 dmaobj->target = NV_MEM_TARGET_PCI;
116 break;
117 case NV_DMA_V0_TARGET_PCI_US:
118 case NV_DMA_V0_TARGET_AGP:
119 if (!client->super)
120 return -EACCES;
121 dmaobj->target = NV_MEM_TARGET_PCI_NOSNOOP;
122 break;
123 default:
124 return -EINVAL;
125 }
126
127 switch (dmaobj->access) {
128 case NV_DMA_V0_ACCESS_VM:
129 dmaobj->access = NV_MEM_ACCESS_VM;
130 break;
131 case NV_DMA_V0_ACCESS_RD:
132 dmaobj->access = NV_MEM_ACCESS_RO;
133 break;
134 case NV_DMA_V0_ACCESS_WR:
135 dmaobj->access = NV_MEM_ACCESS_WO;
136 break;
137 case NV_DMA_V0_ACCESS_RDWR:
138 dmaobj->access = NV_MEM_ACCESS_RW;
139 break;
140 default:
141 return -EINVAL;
142 }
143
144 return ret;
145 }
146
147 int
_nvkm_dmaeng_ctor(struct nouveau_object * parent,struct nouveau_object * engine,struct nouveau_oclass * oclass,void * data,u32 size,struct nouveau_object ** pobject)148 _nvkm_dmaeng_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
149 struct nouveau_oclass *oclass, void *data, u32 size,
150 struct nouveau_object **pobject)
151 {
152 const struct nvkm_dmaeng_impl *impl = (void *)oclass;
153 struct nouveau_dmaeng *dmaeng;
154 int ret;
155
156 ret = nouveau_engine_create(parent, engine, oclass, true, "DMAOBJ",
157 "dmaobj", &dmaeng);
158 *pobject = nv_object(dmaeng);
159 if (ret)
160 return ret;
161
162 nv_engine(dmaeng)->sclass = impl->sclass;
163 dmaeng->bind = nvkm_dmaobj_bind;
164 return 0;
165 }
166