1 /*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
25 #include <core/gpuobj.h>
26 #include <nvif/class.h>
27
28 #include <subdev/fb.h>
29 #include <subdev/vm/nv04.h>
30
31 #include "priv.h"
32
33 struct nv04_dmaobj_priv {
34 struct nouveau_dmaobj base;
35 bool clone;
36 u32 flags0;
37 u32 flags2;
38 };
39
40 static int
nv04_dmaobj_bind(struct nouveau_dmaobj * dmaobj,struct nouveau_object * parent,struct nouveau_gpuobj ** pgpuobj)41 nv04_dmaobj_bind(struct nouveau_dmaobj *dmaobj,
42 struct nouveau_object *parent,
43 struct nouveau_gpuobj **pgpuobj)
44 {
45 struct nv04_dmaobj_priv *priv = (void *)dmaobj;
46 struct nouveau_gpuobj *gpuobj;
47 u64 offset = priv->base.start & 0xfffff000;
48 u64 adjust = priv->base.start & 0x00000fff;
49 u32 length = priv->base.limit - priv->base.start;
50 int ret;
51
52 if (!nv_iclass(parent, NV_ENGCTX_CLASS)) {
53 switch (nv_mclass(parent->parent)) {
54 case NV03_CHANNEL_DMA:
55 case NV10_CHANNEL_DMA:
56 case NV17_CHANNEL_DMA:
57 case NV40_CHANNEL_DMA:
58 break;
59 default:
60 return -EINVAL;
61 }
62 }
63
64 if (priv->clone) {
65 struct nv04_vmmgr_priv *vmm = nv04_vmmgr(dmaobj);
66 struct nouveau_gpuobj *pgt = vmm->vm->pgt[0].obj[0];
67 if (!dmaobj->start)
68 return nouveau_gpuobj_dup(parent, pgt, pgpuobj);
69 offset = nv_ro32(pgt, 8 + (offset >> 10));
70 offset &= 0xfffff000;
71 }
72
73 ret = nouveau_gpuobj_new(parent, parent, 16, 16, 0, &gpuobj);
74 *pgpuobj = gpuobj;
75 if (ret == 0) {
76 nv_wo32(*pgpuobj, 0x00, priv->flags0 | (adjust << 20));
77 nv_wo32(*pgpuobj, 0x04, length);
78 nv_wo32(*pgpuobj, 0x08, priv->flags2 | offset);
79 nv_wo32(*pgpuobj, 0x0c, priv->flags2 | offset);
80 }
81
82 return ret;
83 }
84
85 static int
nv04_dmaobj_ctor(struct nouveau_object * parent,struct nouveau_object * engine,struct nouveau_oclass * oclass,void * data,u32 size,struct nouveau_object ** pobject)86 nv04_dmaobj_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
87 struct nouveau_oclass *oclass, void *data, u32 size,
88 struct nouveau_object **pobject)
89 {
90 struct nouveau_dmaeng *dmaeng = (void *)engine;
91 struct nv04_vmmgr_priv *vmm = nv04_vmmgr(engine);
92 struct nv04_dmaobj_priv *priv;
93 int ret;
94
95 ret = nvkm_dmaobj_create(parent, engine, oclass, &data, &size, &priv);
96 *pobject = nv_object(priv);
97 if (ret || (ret = -ENOSYS, size))
98 return ret;
99
100 if (priv->base.target == NV_MEM_TARGET_VM) {
101 if (nv_object(vmm)->oclass == &nv04_vmmgr_oclass)
102 priv->clone = true;
103 priv->base.target = NV_MEM_TARGET_PCI;
104 priv->base.access = NV_MEM_ACCESS_RW;
105 }
106
107 priv->flags0 = nv_mclass(priv);
108 switch (priv->base.target) {
109 case NV_MEM_TARGET_VRAM:
110 priv->flags0 |= 0x00003000;
111 break;
112 case NV_MEM_TARGET_PCI:
113 priv->flags0 |= 0x00023000;
114 break;
115 case NV_MEM_TARGET_PCI_NOSNOOP:
116 priv->flags0 |= 0x00033000;
117 break;
118 default:
119 return -EINVAL;
120 }
121
122 switch (priv->base.access) {
123 case NV_MEM_ACCESS_RO:
124 priv->flags0 |= 0x00004000;
125 break;
126 case NV_MEM_ACCESS_WO:
127 priv->flags0 |= 0x00008000;
128 case NV_MEM_ACCESS_RW:
129 priv->flags2 |= 0x00000002;
130 break;
131 default:
132 return -EINVAL;
133 }
134
135 return dmaeng->bind(&priv->base, nv_object(priv), (void *)pobject);
136 }
137
138 static struct nouveau_ofuncs
139 nv04_dmaobj_ofuncs = {
140 .ctor = nv04_dmaobj_ctor,
141 .dtor = _nvkm_dmaobj_dtor,
142 .init = _nvkm_dmaobj_init,
143 .fini = _nvkm_dmaobj_fini,
144 };
145
146 static struct nouveau_oclass
147 nv04_dmaeng_sclass[] = {
148 { NV_DMA_FROM_MEMORY, &nv04_dmaobj_ofuncs },
149 { NV_DMA_TO_MEMORY, &nv04_dmaobj_ofuncs },
150 { NV_DMA_IN_MEMORY, &nv04_dmaobj_ofuncs },
151 {}
152 };
153
154 struct nouveau_oclass *
155 nv04_dmaeng_oclass = &(struct nvkm_dmaeng_impl) {
156 .base.handle = NV_ENGINE(DMAOBJ, 0x04),
157 .base.ofuncs = &(struct nouveau_ofuncs) {
158 .ctor = _nvkm_dmaeng_ctor,
159 .dtor = _nvkm_dmaeng_dtor,
160 .init = _nvkm_dmaeng_init,
161 .fini = _nvkm_dmaeng_fini,
162 },
163 .sclass = nv04_dmaeng_sclass,
164 .bind = nv04_dmaobj_bind,
165 }.base;
166