1 /*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
25 #include <core/client.h>
26 #include <core/gpuobj.h>
27 #include <nvif/unpack.h>
28 #include <nvif/class.h>
29
30 #include <subdev/fb.h>
31
32 #include "priv.h"
33
34 struct nv50_dmaobj_priv {
35 struct nouveau_dmaobj base;
36 u32 flags0;
37 u32 flags5;
38 };
39
40 static int
nv50_dmaobj_bind(struct nouveau_dmaobj * dmaobj,struct nouveau_object * parent,struct nouveau_gpuobj ** pgpuobj)41 nv50_dmaobj_bind(struct nouveau_dmaobj *dmaobj,
42 struct nouveau_object *parent,
43 struct nouveau_gpuobj **pgpuobj)
44 {
45 struct nv50_dmaobj_priv *priv = (void *)dmaobj;
46 int ret;
47
48 if (!nv_iclass(parent, NV_ENGCTX_CLASS)) {
49 switch (nv_mclass(parent->parent)) {
50 case NV40_CHANNEL_DMA:
51 case NV50_CHANNEL_GPFIFO:
52 case G82_CHANNEL_GPFIFO:
53 case NV50_DISP_CORE_CHANNEL_DMA:
54 case G82_DISP_CORE_CHANNEL_DMA:
55 case GT206_DISP_CORE_CHANNEL_DMA:
56 case GT200_DISP_CORE_CHANNEL_DMA:
57 case GT214_DISP_CORE_CHANNEL_DMA:
58 case NV50_DISP_BASE_CHANNEL_DMA:
59 case G82_DISP_BASE_CHANNEL_DMA:
60 case GT200_DISP_BASE_CHANNEL_DMA:
61 case GT214_DISP_BASE_CHANNEL_DMA:
62 case NV50_DISP_OVERLAY_CHANNEL_DMA:
63 case G82_DISP_OVERLAY_CHANNEL_DMA:
64 case GT200_DISP_OVERLAY_CHANNEL_DMA:
65 case GT214_DISP_OVERLAY_CHANNEL_DMA:
66 break;
67 default:
68 return -EINVAL;
69 }
70 }
71
72 ret = nouveau_gpuobj_new(parent, parent, 24, 32, 0, pgpuobj);
73 if (ret == 0) {
74 nv_wo32(*pgpuobj, 0x00, priv->flags0 | nv_mclass(dmaobj));
75 nv_wo32(*pgpuobj, 0x04, lower_32_bits(priv->base.limit));
76 nv_wo32(*pgpuobj, 0x08, lower_32_bits(priv->base.start));
77 nv_wo32(*pgpuobj, 0x0c, upper_32_bits(priv->base.limit) << 24 |
78 upper_32_bits(priv->base.start));
79 nv_wo32(*pgpuobj, 0x10, 0x00000000);
80 nv_wo32(*pgpuobj, 0x14, priv->flags5);
81 }
82
83 return ret;
84 }
85
86 static int
nv50_dmaobj_ctor(struct nouveau_object * parent,struct nouveau_object * engine,struct nouveau_oclass * oclass,void * data,u32 size,struct nouveau_object ** pobject)87 nv50_dmaobj_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
88 struct nouveau_oclass *oclass, void *data, u32 size,
89 struct nouveau_object **pobject)
90 {
91 struct nouveau_dmaeng *dmaeng = (void *)engine;
92 union {
93 struct nv50_dma_v0 v0;
94 } *args;
95 struct nv50_dmaobj_priv *priv;
96 u32 user, part, comp, kind;
97 int ret;
98
99 ret = nvkm_dmaobj_create(parent, engine, oclass, &data, &size, &priv);
100 *pobject = nv_object(priv);
101 if (ret)
102 return ret;
103 args = data;
104
105 nv_ioctl(parent, "create nv50 dma size %d\n", size);
106 if (nvif_unpack(args->v0, 0, 0, false)) {
107 nv_ioctl(parent, "create nv50 dma vers %d priv %d part %d "
108 "comp %d kind %02x\n", args->v0.version,
109 args->v0.priv, args->v0.part, args->v0.comp,
110 args->v0.kind);
111 user = args->v0.priv;
112 part = args->v0.part;
113 comp = args->v0.comp;
114 kind = args->v0.kind;
115 } else
116 if (size == 0) {
117 if (priv->base.target != NV_MEM_TARGET_VM) {
118 user = NV50_DMA_V0_PRIV_US;
119 part = NV50_DMA_V0_PART_256;
120 comp = NV50_DMA_V0_COMP_NONE;
121 kind = NV50_DMA_V0_KIND_PITCH;
122 } else {
123 user = NV50_DMA_V0_PRIV_VM;
124 part = NV50_DMA_V0_PART_VM;
125 comp = NV50_DMA_V0_COMP_VM;
126 kind = NV50_DMA_V0_KIND_VM;
127 }
128 } else
129 return ret;
130
131 if (user > 2 || part > 2 || comp > 3 || kind > 0x7f)
132 return -EINVAL;
133 priv->flags0 = (comp << 29) | (kind << 22) | (user << 20);
134 priv->flags5 = (part << 16);
135
136 switch (priv->base.target) {
137 case NV_MEM_TARGET_VM:
138 priv->flags0 |= 0x00000000;
139 break;
140 case NV_MEM_TARGET_VRAM:
141 priv->flags0 |= 0x00010000;
142 break;
143 case NV_MEM_TARGET_PCI:
144 priv->flags0 |= 0x00020000;
145 break;
146 case NV_MEM_TARGET_PCI_NOSNOOP:
147 priv->flags0 |= 0x00030000;
148 break;
149 default:
150 return -EINVAL;
151 }
152
153 switch (priv->base.access) {
154 case NV_MEM_ACCESS_VM:
155 break;
156 case NV_MEM_ACCESS_RO:
157 priv->flags0 |= 0x00040000;
158 break;
159 case NV_MEM_ACCESS_WO:
160 case NV_MEM_ACCESS_RW:
161 priv->flags0 |= 0x00080000;
162 break;
163 default:
164 return -EINVAL;
165 }
166
167 return dmaeng->bind(&priv->base, nv_object(priv), (void *)pobject);
168 }
169
170 static struct nouveau_ofuncs
171 nv50_dmaobj_ofuncs = {
172 .ctor = nv50_dmaobj_ctor,
173 .dtor = _nvkm_dmaobj_dtor,
174 .init = _nvkm_dmaobj_init,
175 .fini = _nvkm_dmaobj_fini,
176 };
177
178 static struct nouveau_oclass
179 nv50_dmaeng_sclass[] = {
180 { NV_DMA_FROM_MEMORY, &nv50_dmaobj_ofuncs },
181 { NV_DMA_TO_MEMORY, &nv50_dmaobj_ofuncs },
182 { NV_DMA_IN_MEMORY, &nv50_dmaobj_ofuncs },
183 {}
184 };
185
186 struct nouveau_oclass *
187 nv50_dmaeng_oclass = &(struct nvkm_dmaeng_impl) {
188 .base.handle = NV_ENGINE(DMAOBJ, 0x50),
189 .base.ofuncs = &(struct nouveau_ofuncs) {
190 .ctor = _nvkm_dmaeng_ctor,
191 .dtor = _nvkm_dmaeng_dtor,
192 .init = _nvkm_dmaeng_init,
193 .fini = _nvkm_dmaeng_fini,
194 },
195 .sclass = nv50_dmaeng_sclass,
196 .bind = nv50_dmaobj_bind,
197 }.base;
198