1 /*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
25 #include <core/os.h>
26 #include <core/client.h>
27 #include <core/engctx.h>
28 #include <core/ramht.h>
29 #include <core/event.h>
30 #include <nvif/unpack.h>
31 #include <nvif/class.h>
32
33 #include <subdev/timer.h>
34 #include <subdev/bar.h>
35
36 #include <engine/dmaobj.h>
37 #include <engine/fifo.h>
38
39 #include "nv04.h"
40 #include "nv50.h"
41
42 /*******************************************************************************
43 * FIFO channel objects
44 ******************************************************************************/
45
46 static int
nv84_fifo_context_attach(struct nouveau_object * parent,struct nouveau_object * object)47 nv84_fifo_context_attach(struct nouveau_object *parent,
48 struct nouveau_object *object)
49 {
50 struct nouveau_bar *bar = nouveau_bar(parent);
51 struct nv50_fifo_base *base = (void *)parent->parent;
52 struct nouveau_gpuobj *ectx = (void *)object;
53 u64 limit = ectx->addr + ectx->size - 1;
54 u64 start = ectx->addr;
55 u32 addr;
56
57 switch (nv_engidx(object->engine)) {
58 case NVDEV_ENGINE_SW : return 0;
59 case NVDEV_ENGINE_GR : addr = 0x0020; break;
60 case NVDEV_ENGINE_VP : addr = 0x0040; break;
61 case NVDEV_ENGINE_PPP :
62 case NVDEV_ENGINE_MPEG : addr = 0x0060; break;
63 case NVDEV_ENGINE_BSP : addr = 0x0080; break;
64 case NVDEV_ENGINE_CRYPT: addr = 0x00a0; break;
65 case NVDEV_ENGINE_COPY0: addr = 0x00c0; break;
66 default:
67 return -EINVAL;
68 }
69
70 nv_engctx(ectx)->addr = nv_gpuobj(base)->addr >> 12;
71 nv_wo32(base->eng, addr + 0x00, 0x00190000);
72 nv_wo32(base->eng, addr + 0x04, lower_32_bits(limit));
73 nv_wo32(base->eng, addr + 0x08, lower_32_bits(start));
74 nv_wo32(base->eng, addr + 0x0c, upper_32_bits(limit) << 24 |
75 upper_32_bits(start));
76 nv_wo32(base->eng, addr + 0x10, 0x00000000);
77 nv_wo32(base->eng, addr + 0x14, 0x00000000);
78 bar->flush(bar);
79 return 0;
80 }
81
82 static int
nv84_fifo_context_detach(struct nouveau_object * parent,bool suspend,struct nouveau_object * object)83 nv84_fifo_context_detach(struct nouveau_object *parent, bool suspend,
84 struct nouveau_object *object)
85 {
86 struct nouveau_bar *bar = nouveau_bar(parent);
87 struct nv50_fifo_priv *priv = (void *)parent->engine;
88 struct nv50_fifo_base *base = (void *)parent->parent;
89 struct nv50_fifo_chan *chan = (void *)parent;
90 u32 addr, save, engn;
91 bool done;
92
93 switch (nv_engidx(object->engine)) {
94 case NVDEV_ENGINE_SW : return 0;
95 case NVDEV_ENGINE_GR : engn = 0; addr = 0x0020; break;
96 case NVDEV_ENGINE_VP : engn = 3; addr = 0x0040; break;
97 case NVDEV_ENGINE_PPP :
98 case NVDEV_ENGINE_MPEG : engn = 1; addr = 0x0060; break;
99 case NVDEV_ENGINE_BSP : engn = 5; addr = 0x0080; break;
100 case NVDEV_ENGINE_CRYPT: engn = 4; addr = 0x00a0; break;
101 case NVDEV_ENGINE_COPY0: engn = 2; addr = 0x00c0; break;
102 default:
103 return -EINVAL;
104 }
105
106 save = nv_mask(priv, 0x002520, 0x0000003f, 1 << engn);
107 nv_wr32(priv, 0x0032fc, nv_gpuobj(base)->addr >> 12);
108 done = nv_wait_ne(priv, 0x0032fc, 0xffffffff, 0xffffffff);
109 nv_wr32(priv, 0x002520, save);
110 if (!done) {
111 nv_error(priv, "channel %d [%s] unload timeout\n",
112 chan->base.chid, nouveau_client_name(chan));
113 if (suspend)
114 return -EBUSY;
115 }
116
117 nv_wo32(base->eng, addr + 0x00, 0x00000000);
118 nv_wo32(base->eng, addr + 0x04, 0x00000000);
119 nv_wo32(base->eng, addr + 0x08, 0x00000000);
120 nv_wo32(base->eng, addr + 0x0c, 0x00000000);
121 nv_wo32(base->eng, addr + 0x10, 0x00000000);
122 nv_wo32(base->eng, addr + 0x14, 0x00000000);
123 bar->flush(bar);
124 return 0;
125 }
126
127 static int
nv84_fifo_object_attach(struct nouveau_object * parent,struct nouveau_object * object,u32 handle)128 nv84_fifo_object_attach(struct nouveau_object *parent,
129 struct nouveau_object *object, u32 handle)
130 {
131 struct nv50_fifo_chan *chan = (void *)parent;
132 u32 context;
133
134 if (nv_iclass(object, NV_GPUOBJ_CLASS))
135 context = nv_gpuobj(object)->node->offset >> 4;
136 else
137 context = 0x00000004; /* just non-zero */
138
139 switch (nv_engidx(object->engine)) {
140 case NVDEV_ENGINE_DMAOBJ:
141 case NVDEV_ENGINE_SW : context |= 0x00000000; break;
142 case NVDEV_ENGINE_GR : context |= 0x00100000; break;
143 case NVDEV_ENGINE_MPEG :
144 case NVDEV_ENGINE_PPP : context |= 0x00200000; break;
145 case NVDEV_ENGINE_ME :
146 case NVDEV_ENGINE_COPY0 : context |= 0x00300000; break;
147 case NVDEV_ENGINE_VP : context |= 0x00400000; break;
148 case NVDEV_ENGINE_CRYPT :
149 case NVDEV_ENGINE_VIC : context |= 0x00500000; break;
150 case NVDEV_ENGINE_BSP : context |= 0x00600000; break;
151 default:
152 return -EINVAL;
153 }
154
155 return nouveau_ramht_insert(chan->ramht, 0, handle, context);
156 }
157
158 static int
nv84_fifo_chan_ctor_dma(struct nouveau_object * parent,struct nouveau_object * engine,struct nouveau_oclass * oclass,void * data,u32 size,struct nouveau_object ** pobject)159 nv84_fifo_chan_ctor_dma(struct nouveau_object *parent,
160 struct nouveau_object *engine,
161 struct nouveau_oclass *oclass, void *data, u32 size,
162 struct nouveau_object **pobject)
163 {
164 union {
165 struct nv03_channel_dma_v0 v0;
166 } *args = data;
167 struct nouveau_bar *bar = nouveau_bar(parent);
168 struct nv50_fifo_base *base = (void *)parent;
169 struct nv50_fifo_chan *chan;
170 int ret;
171
172 nv_ioctl(parent, "create channel dma size %d\n", size);
173 if (nvif_unpack(args->v0, 0, 0, false)) {
174 nv_ioctl(parent, "create channel dma vers %d pushbuf %08x "
175 "offset %016llx\n", args->v0.version,
176 args->v0.pushbuf, args->v0.offset);
177 } else
178 return ret;
179
180 ret = nouveau_fifo_channel_create(parent, engine, oclass, 0, 0xc00000,
181 0x2000, args->v0.pushbuf,
182 (1ULL << NVDEV_ENGINE_DMAOBJ) |
183 (1ULL << NVDEV_ENGINE_SW) |
184 (1ULL << NVDEV_ENGINE_GR) |
185 (1ULL << NVDEV_ENGINE_MPEG) |
186 (1ULL << NVDEV_ENGINE_ME) |
187 (1ULL << NVDEV_ENGINE_VP) |
188 (1ULL << NVDEV_ENGINE_CRYPT) |
189 (1ULL << NVDEV_ENGINE_BSP) |
190 (1ULL << NVDEV_ENGINE_PPP) |
191 (1ULL << NVDEV_ENGINE_COPY0) |
192 (1ULL << NVDEV_ENGINE_VIC), &chan);
193 *pobject = nv_object(chan);
194 if (ret)
195 return ret;
196
197 args->v0.chid = chan->base.chid;
198
199 ret = nouveau_ramht_new(nv_object(chan), nv_object(chan), 0x8000, 16,
200 &chan->ramht);
201 if (ret)
202 return ret;
203
204 nv_parent(chan)->context_attach = nv84_fifo_context_attach;
205 nv_parent(chan)->context_detach = nv84_fifo_context_detach;
206 nv_parent(chan)->object_attach = nv84_fifo_object_attach;
207 nv_parent(chan)->object_detach = nv50_fifo_object_detach;
208
209 nv_wo32(base->ramfc, 0x08, lower_32_bits(args->v0.offset));
210 nv_wo32(base->ramfc, 0x0c, upper_32_bits(args->v0.offset));
211 nv_wo32(base->ramfc, 0x10, lower_32_bits(args->v0.offset));
212 nv_wo32(base->ramfc, 0x14, upper_32_bits(args->v0.offset));
213 nv_wo32(base->ramfc, 0x3c, 0x003f6078);
214 nv_wo32(base->ramfc, 0x44, 0x01003fff);
215 nv_wo32(base->ramfc, 0x48, chan->base.pushgpu->node->offset >> 4);
216 nv_wo32(base->ramfc, 0x4c, 0xffffffff);
217 nv_wo32(base->ramfc, 0x60, 0x7fffffff);
218 nv_wo32(base->ramfc, 0x78, 0x00000000);
219 nv_wo32(base->ramfc, 0x7c, 0x30000001);
220 nv_wo32(base->ramfc, 0x80, ((chan->ramht->bits - 9) << 27) |
221 (4 << 24) /* SEARCH_FULL */ |
222 (chan->ramht->base.node->offset >> 4));
223 nv_wo32(base->ramfc, 0x88, base->cache->addr >> 10);
224 nv_wo32(base->ramfc, 0x98, nv_gpuobj(base)->addr >> 12);
225 bar->flush(bar);
226 return 0;
227 }
228
229 static int
nv84_fifo_chan_ctor_ind(struct nouveau_object * parent,struct nouveau_object * engine,struct nouveau_oclass * oclass,void * data,u32 size,struct nouveau_object ** pobject)230 nv84_fifo_chan_ctor_ind(struct nouveau_object *parent,
231 struct nouveau_object *engine,
232 struct nouveau_oclass *oclass, void *data, u32 size,
233 struct nouveau_object **pobject)
234 {
235 union {
236 struct nv50_channel_gpfifo_v0 v0;
237 } *args = data;
238 struct nouveau_bar *bar = nouveau_bar(parent);
239 struct nv50_fifo_base *base = (void *)parent;
240 struct nv50_fifo_chan *chan;
241 u64 ioffset, ilength;
242 int ret;
243
244 nv_ioctl(parent, "create channel gpfifo size %d\n", size);
245 if (nvif_unpack(args->v0, 0, 0, false)) {
246 nv_ioctl(parent, "create channel gpfifo vers %d pushbuf %08x "
247 "ioffset %016llx ilength %08x\n",
248 args->v0.version, args->v0.pushbuf, args->v0.ioffset,
249 args->v0.ilength);
250 } else
251 return ret;
252
253 ret = nouveau_fifo_channel_create(parent, engine, oclass, 0, 0xc00000,
254 0x2000, args->v0.pushbuf,
255 (1ULL << NVDEV_ENGINE_DMAOBJ) |
256 (1ULL << NVDEV_ENGINE_SW) |
257 (1ULL << NVDEV_ENGINE_GR) |
258 (1ULL << NVDEV_ENGINE_MPEG) |
259 (1ULL << NVDEV_ENGINE_ME) |
260 (1ULL << NVDEV_ENGINE_VP) |
261 (1ULL << NVDEV_ENGINE_CRYPT) |
262 (1ULL << NVDEV_ENGINE_BSP) |
263 (1ULL << NVDEV_ENGINE_PPP) |
264 (1ULL << NVDEV_ENGINE_COPY0) |
265 (1ULL << NVDEV_ENGINE_VIC), &chan);
266 *pobject = nv_object(chan);
267 if (ret)
268 return ret;
269
270 args->v0.chid = chan->base.chid;
271
272 ret = nouveau_ramht_new(nv_object(chan), nv_object(chan), 0x8000, 16,
273 &chan->ramht);
274 if (ret)
275 return ret;
276
277 nv_parent(chan)->context_attach = nv84_fifo_context_attach;
278 nv_parent(chan)->context_detach = nv84_fifo_context_detach;
279 nv_parent(chan)->object_attach = nv84_fifo_object_attach;
280 nv_parent(chan)->object_detach = nv50_fifo_object_detach;
281
282 ioffset = args->v0.ioffset;
283 ilength = order_base_2(args->v0.ilength / 8);
284
285 nv_wo32(base->ramfc, 0x3c, 0x403f6078);
286 nv_wo32(base->ramfc, 0x44, 0x01003fff);
287 nv_wo32(base->ramfc, 0x48, chan->base.pushgpu->node->offset >> 4);
288 nv_wo32(base->ramfc, 0x50, lower_32_bits(ioffset));
289 nv_wo32(base->ramfc, 0x54, upper_32_bits(ioffset) | (ilength << 16));
290 nv_wo32(base->ramfc, 0x60, 0x7fffffff);
291 nv_wo32(base->ramfc, 0x78, 0x00000000);
292 nv_wo32(base->ramfc, 0x7c, 0x30000001);
293 nv_wo32(base->ramfc, 0x80, ((chan->ramht->bits - 9) << 27) |
294 (4 << 24) /* SEARCH_FULL */ |
295 (chan->ramht->base.node->offset >> 4));
296 nv_wo32(base->ramfc, 0x88, base->cache->addr >> 10);
297 nv_wo32(base->ramfc, 0x98, nv_gpuobj(base)->addr >> 12);
298 bar->flush(bar);
299 return 0;
300 }
301
302 static int
nv84_fifo_chan_init(struct nouveau_object * object)303 nv84_fifo_chan_init(struct nouveau_object *object)
304 {
305 struct nv50_fifo_priv *priv = (void *)object->engine;
306 struct nv50_fifo_base *base = (void *)object->parent;
307 struct nv50_fifo_chan *chan = (void *)object;
308 struct nouveau_gpuobj *ramfc = base->ramfc;
309 u32 chid = chan->base.chid;
310 int ret;
311
312 ret = nouveau_fifo_channel_init(&chan->base);
313 if (ret)
314 return ret;
315
316 nv_wr32(priv, 0x002600 + (chid * 4), 0x80000000 | ramfc->addr >> 8);
317 nv50_fifo_playlist_update(priv);
318 return 0;
319 }
320
321 static struct nouveau_ofuncs
322 nv84_fifo_ofuncs_dma = {
323 .ctor = nv84_fifo_chan_ctor_dma,
324 .dtor = nv50_fifo_chan_dtor,
325 .init = nv84_fifo_chan_init,
326 .fini = nv50_fifo_chan_fini,
327 .map = _nouveau_fifo_channel_map,
328 .rd32 = _nouveau_fifo_channel_rd32,
329 .wr32 = _nouveau_fifo_channel_wr32,
330 .ntfy = _nouveau_fifo_channel_ntfy
331 };
332
333 static struct nouveau_ofuncs
334 nv84_fifo_ofuncs_ind = {
335 .ctor = nv84_fifo_chan_ctor_ind,
336 .dtor = nv50_fifo_chan_dtor,
337 .init = nv84_fifo_chan_init,
338 .fini = nv50_fifo_chan_fini,
339 .map = _nouveau_fifo_channel_map,
340 .rd32 = _nouveau_fifo_channel_rd32,
341 .wr32 = _nouveau_fifo_channel_wr32,
342 .ntfy = _nouveau_fifo_channel_ntfy
343 };
344
345 static struct nouveau_oclass
346 nv84_fifo_sclass[] = {
347 { G82_CHANNEL_DMA, &nv84_fifo_ofuncs_dma },
348 { G82_CHANNEL_GPFIFO, &nv84_fifo_ofuncs_ind },
349 {}
350 };
351
352 /*******************************************************************************
353 * FIFO context - basically just the instmem reserved for the channel
354 ******************************************************************************/
355
356 static int
nv84_fifo_context_ctor(struct nouveau_object * parent,struct nouveau_object * engine,struct nouveau_oclass * oclass,void * data,u32 size,struct nouveau_object ** pobject)357 nv84_fifo_context_ctor(struct nouveau_object *parent,
358 struct nouveau_object *engine,
359 struct nouveau_oclass *oclass, void *data, u32 size,
360 struct nouveau_object **pobject)
361 {
362 struct nv50_fifo_base *base;
363 int ret;
364
365 ret = nouveau_fifo_context_create(parent, engine, oclass, NULL, 0x10000,
366 0x1000, NVOBJ_FLAG_HEAP, &base);
367 *pobject = nv_object(base);
368 if (ret)
369 return ret;
370
371 ret = nouveau_gpuobj_new(nv_object(base), nv_object(base), 0x0200, 0,
372 NVOBJ_FLAG_ZERO_ALLOC, &base->eng);
373 if (ret)
374 return ret;
375
376 ret = nouveau_gpuobj_new(nv_object(base), nv_object(base), 0x4000, 0,
377 0, &base->pgd);
378 if (ret)
379 return ret;
380
381 ret = nouveau_vm_ref(nouveau_client(parent)->vm, &base->vm, base->pgd);
382 if (ret)
383 return ret;
384
385 ret = nouveau_gpuobj_new(nv_object(base), nv_object(base), 0x1000,
386 0x400, NVOBJ_FLAG_ZERO_ALLOC, &base->cache);
387 if (ret)
388 return ret;
389
390 ret = nouveau_gpuobj_new(nv_object(base), nv_object(base), 0x0100,
391 0x100, NVOBJ_FLAG_ZERO_ALLOC, &base->ramfc);
392 if (ret)
393 return ret;
394
395 return 0;
396 }
397
398 static struct nouveau_oclass
399 nv84_fifo_cclass = {
400 .handle = NV_ENGCTX(FIFO, 0x84),
401 .ofuncs = &(struct nouveau_ofuncs) {
402 .ctor = nv84_fifo_context_ctor,
403 .dtor = nv50_fifo_context_dtor,
404 .init = _nouveau_fifo_context_init,
405 .fini = _nouveau_fifo_context_fini,
406 .rd32 = _nouveau_fifo_context_rd32,
407 .wr32 = _nouveau_fifo_context_wr32,
408 },
409 };
410
411 /*******************************************************************************
412 * PFIFO engine
413 ******************************************************************************/
414
415 static void
nv84_fifo_uevent_init(struct nvkm_event * event,int type,int index)416 nv84_fifo_uevent_init(struct nvkm_event *event, int type, int index)
417 {
418 struct nouveau_fifo *fifo = container_of(event, typeof(*fifo), uevent);
419 nv_mask(fifo, 0x002140, 0x40000000, 0x40000000);
420 }
421
422 static void
nv84_fifo_uevent_fini(struct nvkm_event * event,int type,int index)423 nv84_fifo_uevent_fini(struct nvkm_event *event, int type, int index)
424 {
425 struct nouveau_fifo *fifo = container_of(event, typeof(*fifo), uevent);
426 nv_mask(fifo, 0x002140, 0x40000000, 0x00000000);
427 }
428
429 static const struct nvkm_event_func
430 nv84_fifo_uevent_func = {
431 .ctor = nouveau_fifo_uevent_ctor,
432 .init = nv84_fifo_uevent_init,
433 .fini = nv84_fifo_uevent_fini,
434 };
435
436 static int
nv84_fifo_ctor(struct nouveau_object * parent,struct nouveau_object * engine,struct nouveau_oclass * oclass,void * data,u32 size,struct nouveau_object ** pobject)437 nv84_fifo_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
438 struct nouveau_oclass *oclass, void *data, u32 size,
439 struct nouveau_object **pobject)
440 {
441 struct nv50_fifo_priv *priv;
442 int ret;
443
444 ret = nouveau_fifo_create(parent, engine, oclass, 1, 127, &priv);
445 *pobject = nv_object(priv);
446 if (ret)
447 return ret;
448
449 ret = nouveau_gpuobj_new(nv_object(priv), NULL, 128 * 4, 0x1000, 0,
450 &priv->playlist[0]);
451 if (ret)
452 return ret;
453
454 ret = nouveau_gpuobj_new(nv_object(priv), NULL, 128 * 4, 0x1000, 0,
455 &priv->playlist[1]);
456 if (ret)
457 return ret;
458
459 ret = nvkm_event_init(&nv84_fifo_uevent_func, 1, 1, &priv->base.uevent);
460 if (ret)
461 return ret;
462
463 nv_subdev(priv)->unit = 0x00000100;
464 nv_subdev(priv)->intr = nv04_fifo_intr;
465 nv_engine(priv)->cclass = &nv84_fifo_cclass;
466 nv_engine(priv)->sclass = nv84_fifo_sclass;
467 priv->base.pause = nv04_fifo_pause;
468 priv->base.start = nv04_fifo_start;
469 return 0;
470 }
471
472 struct nouveau_oclass *
473 nv84_fifo_oclass = &(struct nouveau_oclass) {
474 .handle = NV_ENGINE(FIFO, 0x84),
475 .ofuncs = &(struct nouveau_ofuncs) {
476 .ctor = nv84_fifo_ctor,
477 .dtor = nv50_fifo_dtor,
478 .init = nv50_fifo_init,
479 .fini = _nouveau_fifo_fini,
480 },
481 };
482