1 /*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
25 #include <core/client.h>
26 #include <core/handle.h>
27 #include <core/namedb.h>
28 #include <core/gpuobj.h>
29 #include <core/engctx.h>
30 #include <core/event.h>
31 #include <nvif/unpack.h>
32 #include <nvif/class.h>
33 #include <core/enum.h>
34
35 #include <subdev/timer.h>
36 #include <subdev/bar.h>
37 #include <subdev/fb.h>
38 #include <subdev/vm.h>
39
40 #include <engine/dmaobj.h>
41 #include <engine/fifo.h>
42
43 struct nvc0_fifo_priv {
44 struct nouveau_fifo base;
45
46 struct work_struct fault;
47 u64 mask;
48
49 struct {
50 struct nouveau_gpuobj *mem[2];
51 int active;
52 wait_queue_head_t wait;
53 } runlist;
54
55 struct {
56 struct nouveau_gpuobj *mem;
57 struct nouveau_vma bar;
58 } user;
59 int spoon_nr;
60 };
61
62 struct nvc0_fifo_base {
63 struct nouveau_fifo_base base;
64 struct nouveau_gpuobj *pgd;
65 struct nouveau_vm *vm;
66 };
67
68 struct nvc0_fifo_chan {
69 struct nouveau_fifo_chan base;
70 enum {
71 STOPPED,
72 RUNNING,
73 KILLED
74 } state;
75 };
76
77 /*******************************************************************************
78 * FIFO channel objects
79 ******************************************************************************/
80
81 static void
nvc0_fifo_runlist_update(struct nvc0_fifo_priv * priv)82 nvc0_fifo_runlist_update(struct nvc0_fifo_priv *priv)
83 {
84 struct nouveau_bar *bar = nouveau_bar(priv);
85 struct nouveau_gpuobj *cur;
86 int i, p;
87
88 mutex_lock(&nv_subdev(priv)->mutex);
89 cur = priv->runlist.mem[priv->runlist.active];
90 priv->runlist.active = !priv->runlist.active;
91
92 for (i = 0, p = 0; i < 128; i++) {
93 struct nvc0_fifo_chan *chan = (void *)priv->base.channel[i];
94 if (chan && chan->state == RUNNING) {
95 nv_wo32(cur, p + 0, i);
96 nv_wo32(cur, p + 4, 0x00000004);
97 p += 8;
98 }
99 }
100 bar->flush(bar);
101
102 nv_wr32(priv, 0x002270, cur->addr >> 12);
103 nv_wr32(priv, 0x002274, 0x01f00000 | (p >> 3));
104
105 if (wait_event_timeout(priv->runlist.wait,
106 !(nv_rd32(priv, 0x00227c) & 0x00100000),
107 msecs_to_jiffies(2000)) == 0)
108 nv_error(priv, "runlist update timeout\n");
109 mutex_unlock(&nv_subdev(priv)->mutex);
110 }
111
112 static int
nvc0_fifo_context_attach(struct nouveau_object * parent,struct nouveau_object * object)113 nvc0_fifo_context_attach(struct nouveau_object *parent,
114 struct nouveau_object *object)
115 {
116 struct nouveau_bar *bar = nouveau_bar(parent);
117 struct nvc0_fifo_base *base = (void *)parent->parent;
118 struct nouveau_engctx *ectx = (void *)object;
119 u32 addr;
120 int ret;
121
122 switch (nv_engidx(object->engine)) {
123 case NVDEV_ENGINE_SW : return 0;
124 case NVDEV_ENGINE_GR : addr = 0x0210; break;
125 case NVDEV_ENGINE_COPY0: addr = 0x0230; break;
126 case NVDEV_ENGINE_COPY1: addr = 0x0240; break;
127 case NVDEV_ENGINE_BSP : addr = 0x0270; break;
128 case NVDEV_ENGINE_VP : addr = 0x0250; break;
129 case NVDEV_ENGINE_PPP : addr = 0x0260; break;
130 default:
131 return -EINVAL;
132 }
133
134 if (!ectx->vma.node) {
135 ret = nouveau_gpuobj_map_vm(nv_gpuobj(ectx), base->vm,
136 NV_MEM_ACCESS_RW, &ectx->vma);
137 if (ret)
138 return ret;
139
140 nv_engctx(ectx)->addr = nv_gpuobj(base)->addr >> 12;
141 }
142
143 nv_wo32(base, addr + 0x00, lower_32_bits(ectx->vma.offset) | 4);
144 nv_wo32(base, addr + 0x04, upper_32_bits(ectx->vma.offset));
145 bar->flush(bar);
146 return 0;
147 }
148
149 static int
nvc0_fifo_context_detach(struct nouveau_object * parent,bool suspend,struct nouveau_object * object)150 nvc0_fifo_context_detach(struct nouveau_object *parent, bool suspend,
151 struct nouveau_object *object)
152 {
153 struct nouveau_bar *bar = nouveau_bar(parent);
154 struct nvc0_fifo_priv *priv = (void *)parent->engine;
155 struct nvc0_fifo_base *base = (void *)parent->parent;
156 struct nvc0_fifo_chan *chan = (void *)parent;
157 u32 addr;
158
159 switch (nv_engidx(object->engine)) {
160 case NVDEV_ENGINE_SW : return 0;
161 case NVDEV_ENGINE_GR : addr = 0x0210; break;
162 case NVDEV_ENGINE_COPY0: addr = 0x0230; break;
163 case NVDEV_ENGINE_COPY1: addr = 0x0240; break;
164 case NVDEV_ENGINE_BSP : addr = 0x0270; break;
165 case NVDEV_ENGINE_VP : addr = 0x0250; break;
166 case NVDEV_ENGINE_PPP : addr = 0x0260; break;
167 default:
168 return -EINVAL;
169 }
170
171 nv_wr32(priv, 0x002634, chan->base.chid);
172 if (!nv_wait(priv, 0x002634, 0xffffffff, chan->base.chid)) {
173 nv_error(priv, "channel %d [%s] kick timeout\n",
174 chan->base.chid, nouveau_client_name(chan));
175 if (suspend)
176 return -EBUSY;
177 }
178
179 nv_wo32(base, addr + 0x00, 0x00000000);
180 nv_wo32(base, addr + 0x04, 0x00000000);
181 bar->flush(bar);
182 return 0;
183 }
184
185 static int
nvc0_fifo_chan_ctor(struct nouveau_object * parent,struct nouveau_object * engine,struct nouveau_oclass * oclass,void * data,u32 size,struct nouveau_object ** pobject)186 nvc0_fifo_chan_ctor(struct nouveau_object *parent,
187 struct nouveau_object *engine,
188 struct nouveau_oclass *oclass, void *data, u32 size,
189 struct nouveau_object **pobject)
190 {
191 union {
192 struct nv50_channel_gpfifo_v0 v0;
193 } *args = data;
194 struct nouveau_bar *bar = nouveau_bar(parent);
195 struct nvc0_fifo_priv *priv = (void *)engine;
196 struct nvc0_fifo_base *base = (void *)parent;
197 struct nvc0_fifo_chan *chan;
198 u64 usermem, ioffset, ilength;
199 int ret, i;
200
201 nv_ioctl(parent, "create channel gpfifo size %d\n", size);
202 if (nvif_unpack(args->v0, 0, 0, false)) {
203 nv_ioctl(parent, "create channel gpfifo vers %d pushbuf %08x "
204 "ioffset %016llx ilength %08x\n",
205 args->v0.version, args->v0.pushbuf, args->v0.ioffset,
206 args->v0.ilength);
207 } else
208 return ret;
209
210 ret = nouveau_fifo_channel_create(parent, engine, oclass, 1,
211 priv->user.bar.offset, 0x1000,
212 args->v0.pushbuf,
213 (1ULL << NVDEV_ENGINE_SW) |
214 (1ULL << NVDEV_ENGINE_GR) |
215 (1ULL << NVDEV_ENGINE_COPY0) |
216 (1ULL << NVDEV_ENGINE_COPY1) |
217 (1ULL << NVDEV_ENGINE_BSP) |
218 (1ULL << NVDEV_ENGINE_VP) |
219 (1ULL << NVDEV_ENGINE_PPP), &chan);
220 *pobject = nv_object(chan);
221 if (ret)
222 return ret;
223
224 args->v0.chid = chan->base.chid;
225
226 nv_parent(chan)->context_attach = nvc0_fifo_context_attach;
227 nv_parent(chan)->context_detach = nvc0_fifo_context_detach;
228
229 usermem = chan->base.chid * 0x1000;
230 ioffset = args->v0.ioffset;
231 ilength = order_base_2(args->v0.ilength / 8);
232
233 for (i = 0; i < 0x1000; i += 4)
234 nv_wo32(priv->user.mem, usermem + i, 0x00000000);
235
236 nv_wo32(base, 0x08, lower_32_bits(priv->user.mem->addr + usermem));
237 nv_wo32(base, 0x0c, upper_32_bits(priv->user.mem->addr + usermem));
238 nv_wo32(base, 0x10, 0x0000face);
239 nv_wo32(base, 0x30, 0xfffff902);
240 nv_wo32(base, 0x48, lower_32_bits(ioffset));
241 nv_wo32(base, 0x4c, upper_32_bits(ioffset) | (ilength << 16));
242 nv_wo32(base, 0x54, 0x00000002);
243 nv_wo32(base, 0x84, 0x20400000);
244 nv_wo32(base, 0x94, 0x30000001);
245 nv_wo32(base, 0x9c, 0x00000100);
246 nv_wo32(base, 0xa4, 0x1f1f1f1f);
247 nv_wo32(base, 0xa8, 0x1f1f1f1f);
248 nv_wo32(base, 0xac, 0x0000001f);
249 nv_wo32(base, 0xb8, 0xf8000000);
250 nv_wo32(base, 0xf8, 0x10003080); /* 0x002310 */
251 nv_wo32(base, 0xfc, 0x10000010); /* 0x002350 */
252 bar->flush(bar);
253 return 0;
254 }
255
256 static int
nvc0_fifo_chan_init(struct nouveau_object * object)257 nvc0_fifo_chan_init(struct nouveau_object *object)
258 {
259 struct nouveau_gpuobj *base = nv_gpuobj(object->parent);
260 struct nvc0_fifo_priv *priv = (void *)object->engine;
261 struct nvc0_fifo_chan *chan = (void *)object;
262 u32 chid = chan->base.chid;
263 int ret;
264
265 ret = nouveau_fifo_channel_init(&chan->base);
266 if (ret)
267 return ret;
268
269 nv_wr32(priv, 0x003000 + (chid * 8), 0xc0000000 | base->addr >> 12);
270
271 if (chan->state == STOPPED && (chan->state = RUNNING) == RUNNING) {
272 nv_wr32(priv, 0x003004 + (chid * 8), 0x001f0001);
273 nvc0_fifo_runlist_update(priv);
274 }
275
276 return 0;
277 }
278
279 static void nvc0_fifo_intr_engine(struct nvc0_fifo_priv *priv);
280
281 static int
nvc0_fifo_chan_fini(struct nouveau_object * object,bool suspend)282 nvc0_fifo_chan_fini(struct nouveau_object *object, bool suspend)
283 {
284 struct nvc0_fifo_priv *priv = (void *)object->engine;
285 struct nvc0_fifo_chan *chan = (void *)object;
286 u32 chid = chan->base.chid;
287
288 if (chan->state == RUNNING && (chan->state = STOPPED) == STOPPED) {
289 nv_mask(priv, 0x003004 + (chid * 8), 0x00000001, 0x00000000);
290 nvc0_fifo_runlist_update(priv);
291 }
292
293 nvc0_fifo_intr_engine(priv);
294
295 nv_wr32(priv, 0x003000 + (chid * 8), 0x00000000);
296 return nouveau_fifo_channel_fini(&chan->base, suspend);
297 }
298
299 static struct nouveau_ofuncs
300 nvc0_fifo_ofuncs = {
301 .ctor = nvc0_fifo_chan_ctor,
302 .dtor = _nouveau_fifo_channel_dtor,
303 .init = nvc0_fifo_chan_init,
304 .fini = nvc0_fifo_chan_fini,
305 .map = _nouveau_fifo_channel_map,
306 .rd32 = _nouveau_fifo_channel_rd32,
307 .wr32 = _nouveau_fifo_channel_wr32,
308 .ntfy = _nouveau_fifo_channel_ntfy
309 };
310
311 static struct nouveau_oclass
312 nvc0_fifo_sclass[] = {
313 { FERMI_CHANNEL_GPFIFO, &nvc0_fifo_ofuncs },
314 {}
315 };
316
317 /*******************************************************************************
318 * FIFO context - instmem heap and vm setup
319 ******************************************************************************/
320
321 static int
nvc0_fifo_context_ctor(struct nouveau_object * parent,struct nouveau_object * engine,struct nouveau_oclass * oclass,void * data,u32 size,struct nouveau_object ** pobject)322 nvc0_fifo_context_ctor(struct nouveau_object *parent,
323 struct nouveau_object *engine,
324 struct nouveau_oclass *oclass, void *data, u32 size,
325 struct nouveau_object **pobject)
326 {
327 struct nvc0_fifo_base *base;
328 int ret;
329
330 ret = nouveau_fifo_context_create(parent, engine, oclass, NULL, 0x1000,
331 0x1000, NVOBJ_FLAG_ZERO_ALLOC |
332 NVOBJ_FLAG_HEAP, &base);
333 *pobject = nv_object(base);
334 if (ret)
335 return ret;
336
337 ret = nouveau_gpuobj_new(nv_object(base), NULL, 0x10000, 0x1000, 0,
338 &base->pgd);
339 if (ret)
340 return ret;
341
342 nv_wo32(base, 0x0200, lower_32_bits(base->pgd->addr));
343 nv_wo32(base, 0x0204, upper_32_bits(base->pgd->addr));
344 nv_wo32(base, 0x0208, 0xffffffff);
345 nv_wo32(base, 0x020c, 0x000000ff);
346
347 ret = nouveau_vm_ref(nouveau_client(parent)->vm, &base->vm, base->pgd);
348 if (ret)
349 return ret;
350
351 return 0;
352 }
353
354 static void
nvc0_fifo_context_dtor(struct nouveau_object * object)355 nvc0_fifo_context_dtor(struct nouveau_object *object)
356 {
357 struct nvc0_fifo_base *base = (void *)object;
358 nouveau_vm_ref(NULL, &base->vm, base->pgd);
359 nouveau_gpuobj_ref(NULL, &base->pgd);
360 nouveau_fifo_context_destroy(&base->base);
361 }
362
363 static struct nouveau_oclass
364 nvc0_fifo_cclass = {
365 .handle = NV_ENGCTX(FIFO, 0xc0),
366 .ofuncs = &(struct nouveau_ofuncs) {
367 .ctor = nvc0_fifo_context_ctor,
368 .dtor = nvc0_fifo_context_dtor,
369 .init = _nouveau_fifo_context_init,
370 .fini = _nouveau_fifo_context_fini,
371 .rd32 = _nouveau_fifo_context_rd32,
372 .wr32 = _nouveau_fifo_context_wr32,
373 },
374 };
375
376 /*******************************************************************************
377 * PFIFO engine
378 ******************************************************************************/
379
380 static inline int
nvc0_fifo_engidx(struct nvc0_fifo_priv * priv,u32 engn)381 nvc0_fifo_engidx(struct nvc0_fifo_priv *priv, u32 engn)
382 {
383 switch (engn) {
384 case NVDEV_ENGINE_GR : engn = 0; break;
385 case NVDEV_ENGINE_BSP : engn = 1; break;
386 case NVDEV_ENGINE_PPP : engn = 2; break;
387 case NVDEV_ENGINE_VP : engn = 3; break;
388 case NVDEV_ENGINE_COPY0: engn = 4; break;
389 case NVDEV_ENGINE_COPY1: engn = 5; break;
390 default:
391 return -1;
392 }
393
394 return engn;
395 }
396
397 static inline struct nouveau_engine *
nvc0_fifo_engine(struct nvc0_fifo_priv * priv,u32 engn)398 nvc0_fifo_engine(struct nvc0_fifo_priv *priv, u32 engn)
399 {
400 switch (engn) {
401 case 0: engn = NVDEV_ENGINE_GR; break;
402 case 1: engn = NVDEV_ENGINE_BSP; break;
403 case 2: engn = NVDEV_ENGINE_PPP; break;
404 case 3: engn = NVDEV_ENGINE_VP; break;
405 case 4: engn = NVDEV_ENGINE_COPY0; break;
406 case 5: engn = NVDEV_ENGINE_COPY1; break;
407 default:
408 return NULL;
409 }
410
411 return nouveau_engine(priv, engn);
412 }
413
414 static void
nvc0_fifo_recover_work(struct work_struct * work)415 nvc0_fifo_recover_work(struct work_struct *work)
416 {
417 struct nvc0_fifo_priv *priv = container_of(work, typeof(*priv), fault);
418 struct nouveau_object *engine;
419 unsigned long flags;
420 u32 engn, engm = 0;
421 u64 mask, todo;
422
423 spin_lock_irqsave(&priv->base.lock, flags);
424 mask = priv->mask;
425 priv->mask = 0ULL;
426 spin_unlock_irqrestore(&priv->base.lock, flags);
427
428 for (todo = mask; engn = __ffs64(todo), todo; todo &= ~(1 << engn))
429 engm |= 1 << nvc0_fifo_engidx(priv, engn);
430 nv_mask(priv, 0x002630, engm, engm);
431
432 for (todo = mask; engn = __ffs64(todo), todo; todo &= ~(1 << engn)) {
433 if ((engine = (void *)nouveau_engine(priv, engn))) {
434 nv_ofuncs(engine)->fini(engine, false);
435 WARN_ON(nv_ofuncs(engine)->init(engine));
436 }
437 }
438
439 nvc0_fifo_runlist_update(priv);
440 nv_wr32(priv, 0x00262c, engm);
441 nv_mask(priv, 0x002630, engm, 0x00000000);
442 }
443
444 static void
nvc0_fifo_recover(struct nvc0_fifo_priv * priv,struct nouveau_engine * engine,struct nvc0_fifo_chan * chan)445 nvc0_fifo_recover(struct nvc0_fifo_priv *priv, struct nouveau_engine *engine,
446 struct nvc0_fifo_chan *chan)
447 {
448 struct nouveau_object *engobj = nv_object(engine);
449 u32 chid = chan->base.chid;
450 unsigned long flags;
451
452 nv_error(priv, "%s engine fault on channel %d, recovering...\n",
453 nv_subdev(engine)->name, chid);
454
455 nv_mask(priv, 0x003004 + (chid * 0x08), 0x00000001, 0x00000000);
456 chan->state = KILLED;
457
458 spin_lock_irqsave(&priv->base.lock, flags);
459 priv->mask |= 1ULL << nv_engidx(engobj);
460 spin_unlock_irqrestore(&priv->base.lock, flags);
461 schedule_work(&priv->fault);
462 }
463
464 static int
nvc0_fifo_swmthd(struct nvc0_fifo_priv * priv,u32 chid,u32 mthd,u32 data)465 nvc0_fifo_swmthd(struct nvc0_fifo_priv *priv, u32 chid, u32 mthd, u32 data)
466 {
467 struct nvc0_fifo_chan *chan = NULL;
468 struct nouveau_handle *bind;
469 unsigned long flags;
470 int ret = -EINVAL;
471
472 spin_lock_irqsave(&priv->base.lock, flags);
473 if (likely(chid >= priv->base.min && chid <= priv->base.max))
474 chan = (void *)priv->base.channel[chid];
475 if (unlikely(!chan))
476 goto out;
477
478 bind = nouveau_namedb_get_class(nv_namedb(chan), 0x906e);
479 if (likely(bind)) {
480 if (!mthd || !nv_call(bind->object, mthd, data))
481 ret = 0;
482 nouveau_namedb_put(bind);
483 }
484
485 out:
486 spin_unlock_irqrestore(&priv->base.lock, flags);
487 return ret;
488 }
489
490 static const struct nouveau_enum
491 nvc0_fifo_sched_reason[] = {
492 { 0x0a, "CTXSW_TIMEOUT" },
493 {}
494 };
495
496 static void
nvc0_fifo_intr_sched_ctxsw(struct nvc0_fifo_priv * priv)497 nvc0_fifo_intr_sched_ctxsw(struct nvc0_fifo_priv *priv)
498 {
499 struct nouveau_engine *engine;
500 struct nvc0_fifo_chan *chan;
501 u32 engn;
502
503 for (engn = 0; engn < 6; engn++) {
504 u32 stat = nv_rd32(priv, 0x002640 + (engn * 0x04));
505 u32 busy = (stat & 0x80000000);
506 u32 save = (stat & 0x00100000); /* maybe? */
507 u32 unk0 = (stat & 0x00040000);
508 u32 unk1 = (stat & 0x00001000);
509 u32 chid = (stat & 0x0000007f);
510 (void)save;
511
512 if (busy && unk0 && unk1) {
513 if (!(chan = (void *)priv->base.channel[chid]))
514 continue;
515 if (!(engine = nvc0_fifo_engine(priv, engn)))
516 continue;
517 nvc0_fifo_recover(priv, engine, chan);
518 }
519 }
520 }
521
522 static void
nvc0_fifo_intr_sched(struct nvc0_fifo_priv * priv)523 nvc0_fifo_intr_sched(struct nvc0_fifo_priv *priv)
524 {
525 u32 intr = nv_rd32(priv, 0x00254c);
526 u32 code = intr & 0x000000ff;
527 const struct nouveau_enum *en;
528 char enunk[6] = "";
529
530 en = nouveau_enum_find(nvc0_fifo_sched_reason, code);
531 if (!en)
532 snprintf(enunk, sizeof(enunk), "UNK%02x", code);
533
534 nv_error(priv, "SCHED_ERROR [ %s ]\n", en ? en->name : enunk);
535
536 switch (code) {
537 case 0x0a:
538 nvc0_fifo_intr_sched_ctxsw(priv);
539 break;
540 default:
541 break;
542 }
543 }
544
545 static const struct nouveau_enum
546 nvc0_fifo_fault_engine[] = {
547 { 0x00, "PGRAPH", NULL, NVDEV_ENGINE_GR },
548 { 0x03, "PEEPHOLE", NULL, NVDEV_ENGINE_IFB },
549 { 0x04, "BAR1", NULL, NVDEV_SUBDEV_BAR },
550 { 0x05, "BAR3", NULL, NVDEV_SUBDEV_INSTMEM },
551 { 0x07, "PFIFO", NULL, NVDEV_ENGINE_FIFO },
552 { 0x10, "PBSP", NULL, NVDEV_ENGINE_BSP },
553 { 0x11, "PPPP", NULL, NVDEV_ENGINE_PPP },
554 { 0x13, "PCOUNTER" },
555 { 0x14, "PVP", NULL, NVDEV_ENGINE_VP },
556 { 0x15, "PCOPY0", NULL, NVDEV_ENGINE_COPY0 },
557 { 0x16, "PCOPY1", NULL, NVDEV_ENGINE_COPY1 },
558 { 0x17, "PDAEMON" },
559 {}
560 };
561
562 static const struct nouveau_enum
563 nvc0_fifo_fault_reason[] = {
564 { 0x00, "PT_NOT_PRESENT" },
565 { 0x01, "PT_TOO_SHORT" },
566 { 0x02, "PAGE_NOT_PRESENT" },
567 { 0x03, "VM_LIMIT_EXCEEDED" },
568 { 0x04, "NO_CHANNEL" },
569 { 0x05, "PAGE_SYSTEM_ONLY" },
570 { 0x06, "PAGE_READ_ONLY" },
571 { 0x0a, "COMPRESSED_SYSRAM" },
572 { 0x0c, "INVALID_STORAGE_TYPE" },
573 {}
574 };
575
576 static const struct nouveau_enum
577 nvc0_fifo_fault_hubclient[] = {
578 { 0x01, "PCOPY0" },
579 { 0x02, "PCOPY1" },
580 { 0x04, "DISPATCH" },
581 { 0x05, "CTXCTL" },
582 { 0x06, "PFIFO" },
583 { 0x07, "BAR_READ" },
584 { 0x08, "BAR_WRITE" },
585 { 0x0b, "PVP" },
586 { 0x0c, "PPPP" },
587 { 0x0d, "PBSP" },
588 { 0x11, "PCOUNTER" },
589 { 0x12, "PDAEMON" },
590 { 0x14, "CCACHE" },
591 { 0x15, "CCACHE_POST" },
592 {}
593 };
594
595 static const struct nouveau_enum
596 nvc0_fifo_fault_gpcclient[] = {
597 { 0x01, "TEX" },
598 { 0x0c, "ESETUP" },
599 { 0x0e, "CTXCTL" },
600 { 0x0f, "PROP" },
601 {}
602 };
603
604 static void
nvc0_fifo_intr_fault(struct nvc0_fifo_priv * priv,int unit)605 nvc0_fifo_intr_fault(struct nvc0_fifo_priv *priv, int unit)
606 {
607 u32 inst = nv_rd32(priv, 0x002800 + (unit * 0x10));
608 u32 valo = nv_rd32(priv, 0x002804 + (unit * 0x10));
609 u32 vahi = nv_rd32(priv, 0x002808 + (unit * 0x10));
610 u32 stat = nv_rd32(priv, 0x00280c + (unit * 0x10));
611 u32 gpc = (stat & 0x1f000000) >> 24;
612 u32 client = (stat & 0x00001f00) >> 8;
613 u32 write = (stat & 0x00000080);
614 u32 hub = (stat & 0x00000040);
615 u32 reason = (stat & 0x0000000f);
616 struct nouveau_object *engctx = NULL, *object;
617 struct nouveau_engine *engine = NULL;
618 const struct nouveau_enum *er, *eu, *ec;
619 char erunk[6] = "";
620 char euunk[6] = "";
621 char ecunk[6] = "";
622 char gpcid[3] = "";
623
624 er = nouveau_enum_find(nvc0_fifo_fault_reason, reason);
625 if (!er)
626 snprintf(erunk, sizeof(erunk), "UNK%02X", reason);
627
628 eu = nouveau_enum_find(nvc0_fifo_fault_engine, unit);
629 if (eu) {
630 switch (eu->data2) {
631 case NVDEV_SUBDEV_BAR:
632 nv_mask(priv, 0x001704, 0x00000000, 0x00000000);
633 break;
634 case NVDEV_SUBDEV_INSTMEM:
635 nv_mask(priv, 0x001714, 0x00000000, 0x00000000);
636 break;
637 case NVDEV_ENGINE_IFB:
638 nv_mask(priv, 0x001718, 0x00000000, 0x00000000);
639 break;
640 default:
641 engine = nouveau_engine(priv, eu->data2);
642 if (engine)
643 engctx = nouveau_engctx_get(engine, inst);
644 break;
645 }
646 } else {
647 snprintf(euunk, sizeof(euunk), "UNK%02x", unit);
648 }
649
650 if (hub) {
651 ec = nouveau_enum_find(nvc0_fifo_fault_hubclient, client);
652 } else {
653 ec = nouveau_enum_find(nvc0_fifo_fault_gpcclient, client);
654 snprintf(gpcid, sizeof(gpcid), "%d", gpc);
655 }
656
657 if (!ec)
658 snprintf(ecunk, sizeof(ecunk), "UNK%02x", client);
659
660 nv_error(priv, "%s fault at 0x%010llx [%s] from %s/%s%s%s%s on "
661 "channel 0x%010llx [%s]\n", write ? "write" : "read",
662 (u64)vahi << 32 | valo, er ? er->name : erunk,
663 eu ? eu->name : euunk, hub ? "" : "GPC", gpcid, hub ? "" : "/",
664 ec ? ec->name : ecunk, (u64)inst << 12,
665 nouveau_client_name(engctx));
666
667 object = engctx;
668 while (object) {
669 switch (nv_mclass(object)) {
670 case FERMI_CHANNEL_GPFIFO:
671 nvc0_fifo_recover(priv, engine, (void *)object);
672 break;
673 }
674 object = object->parent;
675 }
676
677 nouveau_engctx_put(engctx);
678 }
679
680 static const struct nouveau_bitfield
681 nvc0_fifo_pbdma_intr[] = {
682 /* { 0x00008000, "" } seen with null ib push */
683 { 0x00200000, "ILLEGAL_MTHD" },
684 { 0x00800000, "EMPTY_SUBC" },
685 {}
686 };
687
688 static void
nvc0_fifo_intr_pbdma(struct nvc0_fifo_priv * priv,int unit)689 nvc0_fifo_intr_pbdma(struct nvc0_fifo_priv *priv, int unit)
690 {
691 u32 stat = nv_rd32(priv, 0x040108 + (unit * 0x2000));
692 u32 addr = nv_rd32(priv, 0x0400c0 + (unit * 0x2000));
693 u32 data = nv_rd32(priv, 0x0400c4 + (unit * 0x2000));
694 u32 chid = nv_rd32(priv, 0x040120 + (unit * 0x2000)) & 0x7f;
695 u32 subc = (addr & 0x00070000) >> 16;
696 u32 mthd = (addr & 0x00003ffc);
697 u32 show = stat;
698
699 if (stat & 0x00800000) {
700 if (!nvc0_fifo_swmthd(priv, chid, mthd, data))
701 show &= ~0x00800000;
702 }
703
704 if (show) {
705 nv_error(priv, "PBDMA%d:", unit);
706 nouveau_bitfield_print(nvc0_fifo_pbdma_intr, show);
707 pr_cont("\n");
708 nv_error(priv,
709 "PBDMA%d: ch %d [%s] subc %d mthd 0x%04x data 0x%08x\n",
710 unit, chid,
711 nouveau_client_name_for_fifo_chid(&priv->base, chid),
712 subc, mthd, data);
713 }
714
715 nv_wr32(priv, 0x0400c0 + (unit * 0x2000), 0x80600008);
716 nv_wr32(priv, 0x040108 + (unit * 0x2000), stat);
717 }
718
719 static void
nvc0_fifo_intr_runlist(struct nvc0_fifo_priv * priv)720 nvc0_fifo_intr_runlist(struct nvc0_fifo_priv *priv)
721 {
722 u32 intr = nv_rd32(priv, 0x002a00);
723
724 if (intr & 0x10000000) {
725 wake_up(&priv->runlist.wait);
726 nv_wr32(priv, 0x002a00, 0x10000000);
727 intr &= ~0x10000000;
728 }
729
730 if (intr) {
731 nv_error(priv, "RUNLIST 0x%08x\n", intr);
732 nv_wr32(priv, 0x002a00, intr);
733 }
734 }
735
736 static void
nvc0_fifo_intr_engine_unit(struct nvc0_fifo_priv * priv,int engn)737 nvc0_fifo_intr_engine_unit(struct nvc0_fifo_priv *priv, int engn)
738 {
739 u32 intr = nv_rd32(priv, 0x0025a8 + (engn * 0x04));
740 u32 inte = nv_rd32(priv, 0x002628);
741 u32 unkn;
742
743 nv_wr32(priv, 0x0025a8 + (engn * 0x04), intr);
744
745 for (unkn = 0; unkn < 8; unkn++) {
746 u32 ints = (intr >> (unkn * 0x04)) & inte;
747 if (ints & 0x1) {
748 nouveau_fifo_uevent(&priv->base);
749 ints &= ~1;
750 }
751 if (ints) {
752 nv_error(priv, "ENGINE %d %d %01x", engn, unkn, ints);
753 nv_mask(priv, 0x002628, ints, 0);
754 }
755 }
756 }
757
758 static void
nvc0_fifo_intr_engine(struct nvc0_fifo_priv * priv)759 nvc0_fifo_intr_engine(struct nvc0_fifo_priv *priv)
760 {
761 u32 mask = nv_rd32(priv, 0x0025a4);
762 while (mask) {
763 u32 unit = __ffs(mask);
764 nvc0_fifo_intr_engine_unit(priv, unit);
765 mask &= ~(1 << unit);
766 }
767 }
768
769 static void
nvc0_fifo_intr(struct nouveau_subdev * subdev)770 nvc0_fifo_intr(struct nouveau_subdev *subdev)
771 {
772 struct nvc0_fifo_priv *priv = (void *)subdev;
773 u32 mask = nv_rd32(priv, 0x002140);
774 u32 stat = nv_rd32(priv, 0x002100) & mask;
775
776 if (stat & 0x00000001) {
777 u32 intr = nv_rd32(priv, 0x00252c);
778 nv_warn(priv, "INTR 0x00000001: 0x%08x\n", intr);
779 nv_wr32(priv, 0x002100, 0x00000001);
780 stat &= ~0x00000001;
781 }
782
783 if (stat & 0x00000100) {
784 nvc0_fifo_intr_sched(priv);
785 nv_wr32(priv, 0x002100, 0x00000100);
786 stat &= ~0x00000100;
787 }
788
789 if (stat & 0x00010000) {
790 u32 intr = nv_rd32(priv, 0x00256c);
791 nv_warn(priv, "INTR 0x00010000: 0x%08x\n", intr);
792 nv_wr32(priv, 0x002100, 0x00010000);
793 stat &= ~0x00010000;
794 }
795
796 if (stat & 0x01000000) {
797 u32 intr = nv_rd32(priv, 0x00258c);
798 nv_warn(priv, "INTR 0x01000000: 0x%08x\n", intr);
799 nv_wr32(priv, 0x002100, 0x01000000);
800 stat &= ~0x01000000;
801 }
802
803 if (stat & 0x10000000) {
804 u32 mask = nv_rd32(priv, 0x00259c);
805 while (mask) {
806 u32 unit = __ffs(mask);
807 nvc0_fifo_intr_fault(priv, unit);
808 nv_wr32(priv, 0x00259c, (1 << unit));
809 mask &= ~(1 << unit);
810 }
811 stat &= ~0x10000000;
812 }
813
814 if (stat & 0x20000000) {
815 u32 mask = nv_rd32(priv, 0x0025a0);
816 while (mask) {
817 u32 unit = __ffs(mask);
818 nvc0_fifo_intr_pbdma(priv, unit);
819 nv_wr32(priv, 0x0025a0, (1 << unit));
820 mask &= ~(1 << unit);
821 }
822 stat &= ~0x20000000;
823 }
824
825 if (stat & 0x40000000) {
826 nvc0_fifo_intr_runlist(priv);
827 stat &= ~0x40000000;
828 }
829
830 if (stat & 0x80000000) {
831 nvc0_fifo_intr_engine(priv);
832 stat &= ~0x80000000;
833 }
834
835 if (stat) {
836 nv_error(priv, "INTR 0x%08x\n", stat);
837 nv_mask(priv, 0x002140, stat, 0x00000000);
838 nv_wr32(priv, 0x002100, stat);
839 }
840 }
841
842 static void
nvc0_fifo_uevent_init(struct nvkm_event * event,int type,int index)843 nvc0_fifo_uevent_init(struct nvkm_event *event, int type, int index)
844 {
845 struct nouveau_fifo *fifo = container_of(event, typeof(*fifo), uevent);
846 nv_mask(fifo, 0x002140, 0x80000000, 0x80000000);
847 }
848
849 static void
nvc0_fifo_uevent_fini(struct nvkm_event * event,int type,int index)850 nvc0_fifo_uevent_fini(struct nvkm_event *event, int type, int index)
851 {
852 struct nouveau_fifo *fifo = container_of(event, typeof(*fifo), uevent);
853 nv_mask(fifo, 0x002140, 0x80000000, 0x00000000);
854 }
855
856 static const struct nvkm_event_func
857 nvc0_fifo_uevent_func = {
858 .ctor = nouveau_fifo_uevent_ctor,
859 .init = nvc0_fifo_uevent_init,
860 .fini = nvc0_fifo_uevent_fini,
861 };
862
863 static int
nvc0_fifo_ctor(struct nouveau_object * parent,struct nouveau_object * engine,struct nouveau_oclass * oclass,void * data,u32 size,struct nouveau_object ** pobject)864 nvc0_fifo_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
865 struct nouveau_oclass *oclass, void *data, u32 size,
866 struct nouveau_object **pobject)
867 {
868 struct nvc0_fifo_priv *priv;
869 int ret;
870
871 ret = nouveau_fifo_create(parent, engine, oclass, 0, 127, &priv);
872 *pobject = nv_object(priv);
873 if (ret)
874 return ret;
875
876 INIT_WORK(&priv->fault, nvc0_fifo_recover_work);
877
878 ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x1000, 0x1000, 0,
879 &priv->runlist.mem[0]);
880 if (ret)
881 return ret;
882
883 ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x1000, 0x1000, 0,
884 &priv->runlist.mem[1]);
885 if (ret)
886 return ret;
887
888 init_waitqueue_head(&priv->runlist.wait);
889
890 ret = nouveau_gpuobj_new(nv_object(priv), NULL, 128 * 0x1000, 0x1000, 0,
891 &priv->user.mem);
892 if (ret)
893 return ret;
894
895 ret = nouveau_gpuobj_map(priv->user.mem, NV_MEM_ACCESS_RW,
896 &priv->user.bar);
897 if (ret)
898 return ret;
899
900 ret = nvkm_event_init(&nvc0_fifo_uevent_func, 1, 1, &priv->base.uevent);
901 if (ret)
902 return ret;
903
904 nv_subdev(priv)->unit = 0x00000100;
905 nv_subdev(priv)->intr = nvc0_fifo_intr;
906 nv_engine(priv)->cclass = &nvc0_fifo_cclass;
907 nv_engine(priv)->sclass = nvc0_fifo_sclass;
908 return 0;
909 }
910
911 static void
nvc0_fifo_dtor(struct nouveau_object * object)912 nvc0_fifo_dtor(struct nouveau_object *object)
913 {
914 struct nvc0_fifo_priv *priv = (void *)object;
915
916 nouveau_gpuobj_unmap(&priv->user.bar);
917 nouveau_gpuobj_ref(NULL, &priv->user.mem);
918 nouveau_gpuobj_ref(NULL, &priv->runlist.mem[0]);
919 nouveau_gpuobj_ref(NULL, &priv->runlist.mem[1]);
920
921 nouveau_fifo_destroy(&priv->base);
922 }
923
924 static int
nvc0_fifo_init(struct nouveau_object * object)925 nvc0_fifo_init(struct nouveau_object *object)
926 {
927 struct nvc0_fifo_priv *priv = (void *)object;
928 int ret, i;
929
930 ret = nouveau_fifo_init(&priv->base);
931 if (ret)
932 return ret;
933
934 nv_wr32(priv, 0x000204, 0xffffffff);
935 nv_wr32(priv, 0x002204, 0xffffffff);
936
937 priv->spoon_nr = hweight32(nv_rd32(priv, 0x002204));
938 nv_debug(priv, "%d PBDMA unit(s)\n", priv->spoon_nr);
939
940 /* assign engines to PBDMAs */
941 if (priv->spoon_nr >= 3) {
942 nv_wr32(priv, 0x002208, ~(1 << 0)); /* PGRAPH */
943 nv_wr32(priv, 0x00220c, ~(1 << 1)); /* PVP */
944 nv_wr32(priv, 0x002210, ~(1 << 1)); /* PPP */
945 nv_wr32(priv, 0x002214, ~(1 << 1)); /* PBSP */
946 nv_wr32(priv, 0x002218, ~(1 << 2)); /* PCE0 */
947 nv_wr32(priv, 0x00221c, ~(1 << 1)); /* PCE1 */
948 }
949
950 /* PBDMA[n] */
951 for (i = 0; i < priv->spoon_nr; i++) {
952 nv_mask(priv, 0x04013c + (i * 0x2000), 0x10000100, 0x00000000);
953 nv_wr32(priv, 0x040108 + (i * 0x2000), 0xffffffff); /* INTR */
954 nv_wr32(priv, 0x04010c + (i * 0x2000), 0xfffffeff); /* INTREN */
955 }
956
957 nv_mask(priv, 0x002200, 0x00000001, 0x00000001);
958 nv_wr32(priv, 0x002254, 0x10000000 | priv->user.bar.offset >> 12);
959
960 nv_wr32(priv, 0x002100, 0xffffffff);
961 nv_wr32(priv, 0x002140, 0x7fffffff);
962 nv_wr32(priv, 0x002628, 0x00000001); /* ENGINE_INTR_EN */
963 return 0;
964 }
965
966 struct nouveau_oclass *
967 nvc0_fifo_oclass = &(struct nouveau_oclass) {
968 .handle = NV_ENGINE(FIFO, 0xc0),
969 .ofuncs = &(struct nouveau_ofuncs) {
970 .ctor = nvc0_fifo_ctor,
971 .dtor = nvc0_fifo_dtor,
972 .init = nvc0_fifo_init,
973 .fini = _nouveau_fifo_fini,
974 },
975 };
976