1 /*
2 * Copyright 2013 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
25 #include <subdev/bios.h>
26 #include <subdev/bios/bit.h>
27 #include <subdev/bios/ramcfg.h>
28 #include <subdev/bios/timing.h>
29
30 u16
nvbios_timingTe(struct nouveau_bios * bios,u8 * ver,u8 * hdr,u8 * cnt,u8 * len,u8 * snr,u8 * ssz)31 nvbios_timingTe(struct nouveau_bios *bios,
32 u8 *ver, u8 *hdr, u8 *cnt, u8 *len, u8 *snr, u8 *ssz)
33 {
34 struct bit_entry bit_P;
35 u16 timing = 0x0000;
36
37 if (!bit_entry(bios, 'P', &bit_P)) {
38 if (bit_P.version == 1)
39 timing = nv_ro16(bios, bit_P.offset + 4);
40 else
41 if (bit_P.version == 2)
42 timing = nv_ro16(bios, bit_P.offset + 8);
43
44 if (timing) {
45 *ver = nv_ro08(bios, timing + 0);
46 switch (*ver) {
47 case 0x10:
48 *hdr = nv_ro08(bios, timing + 1);
49 *cnt = nv_ro08(bios, timing + 2);
50 *len = nv_ro08(bios, timing + 3);
51 *snr = 0;
52 *ssz = 0;
53 return timing;
54 case 0x20:
55 *hdr = nv_ro08(bios, timing + 1);
56 *cnt = nv_ro08(bios, timing + 5);
57 *len = nv_ro08(bios, timing + 2);
58 *snr = nv_ro08(bios, timing + 4);
59 *ssz = nv_ro08(bios, timing + 3);
60 return timing;
61 default:
62 break;
63 }
64 }
65 }
66
67 return 0x0000;
68 }
69
70 u16
nvbios_timingEe(struct nouveau_bios * bios,int idx,u8 * ver,u8 * hdr,u8 * cnt,u8 * len)71 nvbios_timingEe(struct nouveau_bios *bios, int idx,
72 u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
73 {
74 u8 snr, ssz;
75 u16 timing = nvbios_timingTe(bios, ver, hdr, cnt, len, &snr, &ssz);
76 if (timing && idx < *cnt) {
77 timing += *hdr + idx * (*len + (snr * ssz));
78 *hdr = *len;
79 *cnt = snr;
80 *len = ssz;
81 return timing;
82 }
83 return 0x0000;
84 }
85
86 u16
nvbios_timingEp(struct nouveau_bios * bios,int idx,u8 * ver,u8 * hdr,u8 * cnt,u8 * len,struct nvbios_ramcfg * p)87 nvbios_timingEp(struct nouveau_bios *bios, int idx,
88 u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
89 struct nvbios_ramcfg *p)
90 {
91 u16 data = nvbios_timingEe(bios, idx, ver, hdr, cnt, len), temp;
92 p->timing_ver = *ver;
93 p->timing_hdr = *hdr;
94 switch (!!data * *ver) {
95 case 0x10:
96 p->timing_10_WR = nv_ro08(bios, data + 0x00);
97 p->timing_10_CL = nv_ro08(bios, data + 0x02);
98 p->timing_10_ODT = nv_ro08(bios, data + 0x0e) & 0x07;
99 p->timing_10_CWL = nv_ro08(bios, data + 0x13);
100 break;
101 case 0x20:
102 p->timing[0] = nv_ro32(bios, data + 0x00);
103 p->timing[1] = nv_ro32(bios, data + 0x04);
104 p->timing[2] = nv_ro32(bios, data + 0x08);
105 p->timing[3] = nv_ro32(bios, data + 0x0c);
106 p->timing[4] = nv_ro32(bios, data + 0x10);
107 p->timing[5] = nv_ro32(bios, data + 0x14);
108 p->timing[6] = nv_ro32(bios, data + 0x18);
109 p->timing[7] = nv_ro32(bios, data + 0x1c);
110 p->timing[8] = nv_ro32(bios, data + 0x20);
111 p->timing[9] = nv_ro32(bios, data + 0x24);
112 p->timing[10] = nv_ro32(bios, data + 0x28);
113 p->timing_20_2e_03 = (nv_ro08(bios, data + 0x2e) & 0x03) >> 0;
114 p->timing_20_2e_30 = (nv_ro08(bios, data + 0x2e) & 0x30) >> 4;
115 p->timing_20_2e_c0 = (nv_ro08(bios, data + 0x2e) & 0xc0) >> 6;
116 p->timing_20_2f_03 = (nv_ro08(bios, data + 0x2f) & 0x03) >> 0;
117 temp = nv_ro16(bios, data + 0x2c);
118 p->timing_20_2c_003f = (temp & 0x003f) >> 0;
119 p->timing_20_2c_1fc0 = (temp & 0x1fc0) >> 6;
120 p->timing_20_30_07 = (nv_ro08(bios, data + 0x30) & 0x07) >> 0;
121 p->timing_20_30_f8 = (nv_ro08(bios, data + 0x30) & 0xf8) >> 3;
122 temp = nv_ro16(bios, data + 0x31);
123 p->timing_20_31_0007 = (temp & 0x0007) >> 0;
124 p->timing_20_31_0078 = (temp & 0x0078) >> 3;
125 p->timing_20_31_0780 = (temp & 0x0780) >> 7;
126 p->timing_20_31_0800 = (temp & 0x0800) >> 11;
127 p->timing_20_31_7000 = (temp & 0x7000) >> 12;
128 p->timing_20_31_8000 = (temp & 0x8000) >> 15;
129 break;
130 default:
131 data = 0;
132 break;
133 }
134 return data;
135 }
136