1 /*
2 * Copyright 2012 Nouveau Community
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Martin Peres <martin.peres@labri.fr>
23 * Ben Skeggs
24 */
25
26 #include <subdev/timer.h>
27
28 #include "nv04.h"
29
30 static int
nv50_bus_hwsq_exec(struct nouveau_bus * pbus,u32 * data,u32 size)31 nv50_bus_hwsq_exec(struct nouveau_bus *pbus, u32 *data, u32 size)
32 {
33 struct nv50_bus_priv *priv = (void *)pbus;
34 int i;
35
36 nv_mask(pbus, 0x001098, 0x00000008, 0x00000000);
37 nv_wr32(pbus, 0x001304, 0x00000000);
38 for (i = 0; i < size; i++)
39 nv_wr32(priv, 0x001400 + (i * 4), data[i]);
40 nv_mask(pbus, 0x001098, 0x00000018, 0x00000018);
41 nv_wr32(pbus, 0x00130c, 0x00000003);
42
43 return nv_wait(pbus, 0x001308, 0x00000100, 0x00000000) ? 0 : -ETIMEDOUT;
44 }
45
46 void
nv50_bus_intr(struct nouveau_subdev * subdev)47 nv50_bus_intr(struct nouveau_subdev *subdev)
48 {
49 struct nouveau_bus *pbus = nouveau_bus(subdev);
50 u32 stat = nv_rd32(pbus, 0x001100) & nv_rd32(pbus, 0x001140);
51
52 if (stat & 0x00000008) {
53 u32 addr = nv_rd32(pbus, 0x009084);
54 u32 data = nv_rd32(pbus, 0x009088);
55
56 nv_error(pbus, "MMIO %s of 0x%08x FAULT at 0x%06x\n",
57 (addr & 0x00000002) ? "write" : "read", data,
58 (addr & 0x00fffffc));
59
60 stat &= ~0x00000008;
61 nv_wr32(pbus, 0x001100, 0x00000008);
62 }
63
64 if (stat & 0x00010000) {
65 subdev = nouveau_subdev(pbus, NVDEV_SUBDEV_THERM);
66 if (subdev && subdev->intr)
67 subdev->intr(subdev);
68 stat &= ~0x00010000;
69 nv_wr32(pbus, 0x001100, 0x00010000);
70 }
71
72 if (stat) {
73 nv_error(pbus, "unknown intr 0x%08x\n", stat);
74 nv_mask(pbus, 0x001140, stat, 0);
75 }
76 }
77
78 int
nv50_bus_init(struct nouveau_object * object)79 nv50_bus_init(struct nouveau_object *object)
80 {
81 struct nv04_bus_priv *priv = (void *)object;
82 int ret;
83
84 ret = nouveau_bus_init(&priv->base);
85 if (ret)
86 return ret;
87
88 nv_wr32(priv, 0x001100, 0xffffffff);
89 nv_wr32(priv, 0x001140, 0x00010008);
90 return 0;
91 }
92
93 struct nouveau_oclass *
94 nv50_bus_oclass = &(struct nv04_bus_impl) {
95 .base.handle = NV_SUBDEV(BUS, 0x50),
96 .base.ofuncs = &(struct nouveau_ofuncs) {
97 .ctor = nv04_bus_ctor,
98 .dtor = _nouveau_bus_dtor,
99 .init = nv50_bus_init,
100 .fini = _nouveau_bus_fini,
101 },
102 .intr = nv50_bus_intr,
103 .hwsq_exec = nv50_bus_hwsq_exec,
104 .hwsq_size = 64,
105 }.base;
106