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1 /*
2  * Copyright 2012 Red Hat Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: Ben Skeggs
23  */
24 
25 #include "priv.h"
26 
27 void
nv50_gpio_reset(struct nouveau_gpio * gpio,u8 match)28 nv50_gpio_reset(struct nouveau_gpio *gpio, u8 match)
29 {
30 	struct nouveau_bios *bios = nouveau_bios(gpio);
31 	u8 ver, len;
32 	u16 entry;
33 	int ent = -1;
34 
35 	while ((entry = dcb_gpio_entry(bios, 0, ++ent, &ver, &len))) {
36 		static const u32 regs[] = { 0xe100, 0xe28c };
37 		u32 data = nv_ro32(bios, entry);
38 		u8  line =   (data & 0x0000001f);
39 		u8  func =   (data & 0x0000ff00) >> 8;
40 		u8  defs = !!(data & 0x01000000);
41 		u8  unk0 = !!(data & 0x02000000);
42 		u8  unk1 = !!(data & 0x04000000);
43 		u32 val = (unk1 << 16) | unk0;
44 		u32 reg = regs[line >> 4];
45 		u32 lsh = line & 0x0f;
46 
47 		if ( func  == DCB_GPIO_UNUSED ||
48 		    (match != DCB_GPIO_UNUSED && match != func))
49 			continue;
50 
51 		gpio->set(gpio, 0, func, line, defs);
52 
53 		nv_mask(gpio, reg, 0x00010001 << lsh, val << lsh);
54 	}
55 }
56 
57 static int
nv50_gpio_location(int line,u32 * reg,u32 * shift)58 nv50_gpio_location(int line, u32 *reg, u32 *shift)
59 {
60 	const u32 nv50_gpio_reg[4] = { 0xe104, 0xe108, 0xe280, 0xe284 };
61 
62 	if (line >= 32)
63 		return -EINVAL;
64 
65 	*reg = nv50_gpio_reg[line >> 3];
66 	*shift = (line & 7) << 2;
67 	return 0;
68 }
69 
70 int
nv50_gpio_drive(struct nouveau_gpio * gpio,int line,int dir,int out)71 nv50_gpio_drive(struct nouveau_gpio *gpio, int line, int dir, int out)
72 {
73 	u32 reg, shift;
74 
75 	if (nv50_gpio_location(line, &reg, &shift))
76 		return -EINVAL;
77 
78 	nv_mask(gpio, reg, 3 << shift, (((dir ^ 1) << 1) | out) << shift);
79 	return 0;
80 }
81 
82 int
nv50_gpio_sense(struct nouveau_gpio * gpio,int line)83 nv50_gpio_sense(struct nouveau_gpio *gpio, int line)
84 {
85 	u32 reg, shift;
86 
87 	if (nv50_gpio_location(line, &reg, &shift))
88 		return -EINVAL;
89 
90 	return !!(nv_rd32(gpio, reg) & (4 << shift));
91 }
92 
93 static void
nv50_gpio_intr_stat(struct nouveau_gpio * gpio,u32 * hi,u32 * lo)94 nv50_gpio_intr_stat(struct nouveau_gpio *gpio, u32 *hi, u32 *lo)
95 {
96 	u32 intr = nv_rd32(gpio, 0x00e054);
97 	u32 stat = nv_rd32(gpio, 0x00e050) & intr;
98 	*lo = (stat & 0xffff0000) >> 16;
99 	*hi = (stat & 0x0000ffff);
100 	nv_wr32(gpio, 0x00e054, intr);
101 }
102 
103 static void
nv50_gpio_intr_mask(struct nouveau_gpio * gpio,u32 type,u32 mask,u32 data)104 nv50_gpio_intr_mask(struct nouveau_gpio *gpio, u32 type, u32 mask, u32 data)
105 {
106 	u32 inte = nv_rd32(gpio, 0x00e050);
107 	if (type & NVKM_GPIO_LO)
108 		inte = (inte & ~(mask << 16)) | (data << 16);
109 	if (type & NVKM_GPIO_HI)
110 		inte = (inte & ~mask) | data;
111 	nv_wr32(gpio, 0x00e050, inte);
112 }
113 
114 struct nouveau_oclass *
115 nv50_gpio_oclass = &(struct nouveau_gpio_impl) {
116 	.base.handle = NV_SUBDEV(GPIO, 0x50),
117 	.base.ofuncs = &(struct nouveau_ofuncs) {
118 		.ctor = _nouveau_gpio_ctor,
119 		.dtor = _nouveau_gpio_dtor,
120 		.init = _nouveau_gpio_init,
121 		.fini = _nouveau_gpio_fini,
122 	},
123 	.lines = 16,
124 	.intr_stat = nv50_gpio_intr_stat,
125 	.intr_mask = nv50_gpio_intr_mask,
126 	.drive = nv50_gpio_drive,
127 	.sense = nv50_gpio_sense,
128 	.reset = nv50_gpio_reset,
129 }.base;
130