1 /*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
25 #include "nv04.h"
26
27 static u64
nv04_timer_read(struct nouveau_timer * ptimer)28 nv04_timer_read(struct nouveau_timer *ptimer)
29 {
30 struct nv04_timer_priv *priv = (void *)ptimer;
31 u32 hi, lo;
32
33 do {
34 hi = nv_rd32(priv, NV04_PTIMER_TIME_1);
35 lo = nv_rd32(priv, NV04_PTIMER_TIME_0);
36 } while (hi != nv_rd32(priv, NV04_PTIMER_TIME_1));
37
38 return ((u64)hi << 32 | lo);
39 }
40
41 static void
nv04_timer_alarm_trigger(struct nouveau_timer * ptimer)42 nv04_timer_alarm_trigger(struct nouveau_timer *ptimer)
43 {
44 struct nv04_timer_priv *priv = (void *)ptimer;
45 struct nouveau_alarm *alarm, *atemp;
46 unsigned long flags;
47 LIST_HEAD(exec);
48
49 /* move any due alarms off the pending list */
50 spin_lock_irqsave(&priv->lock, flags);
51 list_for_each_entry_safe(alarm, atemp, &priv->alarms, head) {
52 if (alarm->timestamp <= ptimer->read(ptimer))
53 list_move_tail(&alarm->head, &exec);
54 }
55
56 /* reschedule interrupt for next alarm time */
57 if (!list_empty(&priv->alarms)) {
58 alarm = list_first_entry(&priv->alarms, typeof(*alarm), head);
59 nv_wr32(priv, NV04_PTIMER_ALARM_0, alarm->timestamp);
60 nv_wr32(priv, NV04_PTIMER_INTR_EN_0, 0x00000001);
61 } else {
62 nv_wr32(priv, NV04_PTIMER_INTR_EN_0, 0x00000000);
63 }
64 spin_unlock_irqrestore(&priv->lock, flags);
65
66 /* execute any pending alarm handlers */
67 list_for_each_entry_safe(alarm, atemp, &exec, head) {
68 list_del_init(&alarm->head);
69 alarm->func(alarm);
70 }
71 }
72
73 static void
nv04_timer_alarm(struct nouveau_timer * ptimer,u64 time,struct nouveau_alarm * alarm)74 nv04_timer_alarm(struct nouveau_timer *ptimer, u64 time,
75 struct nouveau_alarm *alarm)
76 {
77 struct nv04_timer_priv *priv = (void *)ptimer;
78 struct nouveau_alarm *list;
79 unsigned long flags;
80
81 alarm->timestamp = ptimer->read(ptimer) + time;
82
83 /* append new alarm to list, in soonest-alarm-first order */
84 spin_lock_irqsave(&priv->lock, flags);
85 if (!time) {
86 if (!list_empty(&alarm->head))
87 list_del(&alarm->head);
88 } else {
89 list_for_each_entry(list, &priv->alarms, head) {
90 if (list->timestamp > alarm->timestamp)
91 break;
92 }
93 list_add_tail(&alarm->head, &list->head);
94 }
95 spin_unlock_irqrestore(&priv->lock, flags);
96
97 /* process pending alarms */
98 nv04_timer_alarm_trigger(ptimer);
99 }
100
101 static void
nv04_timer_alarm_cancel(struct nouveau_timer * ptimer,struct nouveau_alarm * alarm)102 nv04_timer_alarm_cancel(struct nouveau_timer *ptimer,
103 struct nouveau_alarm *alarm)
104 {
105 struct nv04_timer_priv *priv = (void *)ptimer;
106 unsigned long flags;
107 spin_lock_irqsave(&priv->lock, flags);
108 list_del_init(&alarm->head);
109 spin_unlock_irqrestore(&priv->lock, flags);
110 }
111
112 static void
nv04_timer_intr(struct nouveau_subdev * subdev)113 nv04_timer_intr(struct nouveau_subdev *subdev)
114 {
115 struct nv04_timer_priv *priv = (void *)subdev;
116 u32 stat = nv_rd32(priv, NV04_PTIMER_INTR_0);
117
118 if (stat & 0x00000001) {
119 nv04_timer_alarm_trigger(&priv->base);
120 nv_wr32(priv, NV04_PTIMER_INTR_0, 0x00000001);
121 stat &= ~0x00000001;
122 }
123
124 if (stat) {
125 nv_error(priv, "unknown stat 0x%08x\n", stat);
126 nv_wr32(priv, NV04_PTIMER_INTR_0, stat);
127 }
128 }
129
130 int
nv04_timer_fini(struct nouveau_object * object,bool suspend)131 nv04_timer_fini(struct nouveau_object *object, bool suspend)
132 {
133 struct nv04_timer_priv *priv = (void *)object;
134 if (suspend)
135 priv->suspend_time = nv04_timer_read(&priv->base);
136 nv_wr32(priv, NV04_PTIMER_INTR_EN_0, 0x00000000);
137 return nouveau_timer_fini(&priv->base, suspend);
138 }
139
140 static int
nv04_timer_init(struct nouveau_object * object)141 nv04_timer_init(struct nouveau_object *object)
142 {
143 struct nouveau_device *device = nv_device(object);
144 struct nv04_timer_priv *priv = (void *)object;
145 u32 m = 1, f, n, d, lo, hi;
146 int ret;
147
148 ret = nouveau_timer_init(&priv->base);
149 if (ret)
150 return ret;
151
152 /* aim for 31.25MHz, which gives us nanosecond timestamps */
153 d = 1000000 / 32;
154
155 /* determine base clock for timer source */
156 #if 0 /*XXX*/
157 if (device->chipset < 0x40) {
158 n = nouveau_hw_get_clock(device, PLL_CORE);
159 } else
160 #endif
161 if (device->chipset <= 0x40) {
162 /*XXX: figure this out */
163 f = -1;
164 n = 0;
165 } else {
166 f = device->crystal;
167 n = f;
168 while (n < (d * 2)) {
169 n += (n / m);
170 m++;
171 }
172
173 nv_wr32(priv, 0x009220, m - 1);
174 }
175
176 if (!n) {
177 nv_warn(priv, "unknown input clock freq\n");
178 if (!nv_rd32(priv, NV04_PTIMER_NUMERATOR) ||
179 !nv_rd32(priv, NV04_PTIMER_DENOMINATOR)) {
180 nv_wr32(priv, NV04_PTIMER_NUMERATOR, 1);
181 nv_wr32(priv, NV04_PTIMER_DENOMINATOR, 1);
182 }
183 return 0;
184 }
185
186 /* reduce ratio to acceptable values */
187 while (((n % 5) == 0) && ((d % 5) == 0)) {
188 n /= 5;
189 d /= 5;
190 }
191
192 while (((n % 2) == 0) && ((d % 2) == 0)) {
193 n /= 2;
194 d /= 2;
195 }
196
197 while (n > 0xffff || d > 0xffff) {
198 n >>= 1;
199 d >>= 1;
200 }
201
202 /* restore the time before suspend */
203 lo = priv->suspend_time;
204 hi = (priv->suspend_time >> 32);
205
206 nv_debug(priv, "input frequency : %dHz\n", f);
207 nv_debug(priv, "input multiplier: %d\n", m);
208 nv_debug(priv, "numerator : 0x%08x\n", n);
209 nv_debug(priv, "denominator : 0x%08x\n", d);
210 nv_debug(priv, "timer frequency : %dHz\n", (f * m) * d / n);
211 nv_debug(priv, "time low : 0x%08x\n", lo);
212 nv_debug(priv, "time high : 0x%08x\n", hi);
213
214 nv_wr32(priv, NV04_PTIMER_NUMERATOR, n);
215 nv_wr32(priv, NV04_PTIMER_DENOMINATOR, d);
216 nv_wr32(priv, NV04_PTIMER_INTR_0, 0xffffffff);
217 nv_wr32(priv, NV04_PTIMER_INTR_EN_0, 0x00000000);
218 nv_wr32(priv, NV04_PTIMER_TIME_1, hi);
219 nv_wr32(priv, NV04_PTIMER_TIME_0, lo);
220
221 return 0;
222 }
223
224 void
nv04_timer_dtor(struct nouveau_object * object)225 nv04_timer_dtor(struct nouveau_object *object)
226 {
227 struct nv04_timer_priv *priv = (void *)object;
228 return nouveau_timer_destroy(&priv->base);
229 }
230
231 int
nv04_timer_ctor(struct nouveau_object * parent,struct nouveau_object * engine,struct nouveau_oclass * oclass,void * data,u32 size,struct nouveau_object ** pobject)232 nv04_timer_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
233 struct nouveau_oclass *oclass, void *data, u32 size,
234 struct nouveau_object **pobject)
235 {
236 struct nv04_timer_priv *priv;
237 int ret;
238
239 ret = nouveau_timer_create(parent, engine, oclass, &priv);
240 *pobject = nv_object(priv);
241 if (ret)
242 return ret;
243
244 priv->base.base.intr = nv04_timer_intr;
245 priv->base.read = nv04_timer_read;
246 priv->base.alarm = nv04_timer_alarm;
247 priv->base.alarm_cancel = nv04_timer_alarm_cancel;
248 priv->suspend_time = 0;
249
250 INIT_LIST_HEAD(&priv->alarms);
251 spin_lock_init(&priv->lock);
252 return 0;
253 }
254
255 struct nouveau_oclass
256 nv04_timer_oclass = {
257 .handle = NV_SUBDEV(TIMER, 0x04),
258 .ofuncs = &(struct nouveau_ofuncs) {
259 .ctor = nv04_timer_ctor,
260 .dtor = nv04_timer_dtor,
261 .init = nv04_timer_init,
262 .fini = nv04_timer_fini,
263 }
264 };
265