1 /*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26 #include <drm/drmP.h>
27 #include <drm/drm_crtc_helper.h>
28 #include <drm/radeon_drm.h>
29 #include <drm/drm_fixed.h>
30 #include "radeon.h"
31 #include "atom.h"
32 #include "atom-bits.h"
33
atombios_overscan_setup(struct drm_crtc * crtc,struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode)34 static void atombios_overscan_setup(struct drm_crtc *crtc,
35 struct drm_display_mode *mode,
36 struct drm_display_mode *adjusted_mode)
37 {
38 struct drm_device *dev = crtc->dev;
39 struct radeon_device *rdev = dev->dev_private;
40 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
41 SET_CRTC_OVERSCAN_PS_ALLOCATION args;
42 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_OverScan);
43 int a1, a2;
44
45 memset(&args, 0, sizeof(args));
46
47 args.ucCRTC = radeon_crtc->crtc_id;
48
49 switch (radeon_crtc->rmx_type) {
50 case RMX_CENTER:
51 args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2);
52 args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2);
53 args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2);
54 args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2);
55 break;
56 case RMX_ASPECT:
57 a1 = mode->crtc_vdisplay * adjusted_mode->crtc_hdisplay;
58 a2 = adjusted_mode->crtc_vdisplay * mode->crtc_hdisplay;
59
60 if (a1 > a2) {
61 args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2);
62 args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2);
63 } else if (a2 > a1) {
64 args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2);
65 args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2);
66 }
67 break;
68 case RMX_FULL:
69 default:
70 args.usOverscanRight = cpu_to_le16(radeon_crtc->h_border);
71 args.usOverscanLeft = cpu_to_le16(radeon_crtc->h_border);
72 args.usOverscanBottom = cpu_to_le16(radeon_crtc->v_border);
73 args.usOverscanTop = cpu_to_le16(radeon_crtc->v_border);
74 break;
75 }
76 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
77 }
78
atombios_scaler_setup(struct drm_crtc * crtc)79 static void atombios_scaler_setup(struct drm_crtc *crtc)
80 {
81 struct drm_device *dev = crtc->dev;
82 struct radeon_device *rdev = dev->dev_private;
83 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
84 ENABLE_SCALER_PS_ALLOCATION args;
85 int index = GetIndexIntoMasterTable(COMMAND, EnableScaler);
86 struct radeon_encoder *radeon_encoder =
87 to_radeon_encoder(radeon_crtc->encoder);
88 /* fixme - fill in enc_priv for atom dac */
89 enum radeon_tv_std tv_std = TV_STD_NTSC;
90 bool is_tv = false, is_cv = false;
91
92 if (!ASIC_IS_AVIVO(rdev) && radeon_crtc->crtc_id)
93 return;
94
95 if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) {
96 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
97 tv_std = tv_dac->tv_std;
98 is_tv = true;
99 }
100
101 memset(&args, 0, sizeof(args));
102
103 args.ucScaler = radeon_crtc->crtc_id;
104
105 if (is_tv) {
106 switch (tv_std) {
107 case TV_STD_NTSC:
108 default:
109 args.ucTVStandard = ATOM_TV_NTSC;
110 break;
111 case TV_STD_PAL:
112 args.ucTVStandard = ATOM_TV_PAL;
113 break;
114 case TV_STD_PAL_M:
115 args.ucTVStandard = ATOM_TV_PALM;
116 break;
117 case TV_STD_PAL_60:
118 args.ucTVStandard = ATOM_TV_PAL60;
119 break;
120 case TV_STD_NTSC_J:
121 args.ucTVStandard = ATOM_TV_NTSCJ;
122 break;
123 case TV_STD_SCART_PAL:
124 args.ucTVStandard = ATOM_TV_PAL; /* ??? */
125 break;
126 case TV_STD_SECAM:
127 args.ucTVStandard = ATOM_TV_SECAM;
128 break;
129 case TV_STD_PAL_CN:
130 args.ucTVStandard = ATOM_TV_PALCN;
131 break;
132 }
133 args.ucEnable = SCALER_ENABLE_MULTITAP_MODE;
134 } else if (is_cv) {
135 args.ucTVStandard = ATOM_TV_CV;
136 args.ucEnable = SCALER_ENABLE_MULTITAP_MODE;
137 } else {
138 switch (radeon_crtc->rmx_type) {
139 case RMX_FULL:
140 args.ucEnable = ATOM_SCALER_EXPANSION;
141 break;
142 case RMX_CENTER:
143 args.ucEnable = ATOM_SCALER_CENTER;
144 break;
145 case RMX_ASPECT:
146 args.ucEnable = ATOM_SCALER_EXPANSION;
147 break;
148 default:
149 if (ASIC_IS_AVIVO(rdev))
150 args.ucEnable = ATOM_SCALER_DISABLE;
151 else
152 args.ucEnable = ATOM_SCALER_CENTER;
153 break;
154 }
155 }
156 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
157 if ((is_tv || is_cv)
158 && rdev->family >= CHIP_RV515 && rdev->family <= CHIP_R580) {
159 atom_rv515_force_tv_scaler(rdev, radeon_crtc);
160 }
161 }
162
atombios_lock_crtc(struct drm_crtc * crtc,int lock)163 static void atombios_lock_crtc(struct drm_crtc *crtc, int lock)
164 {
165 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
166 struct drm_device *dev = crtc->dev;
167 struct radeon_device *rdev = dev->dev_private;
168 int index =
169 GetIndexIntoMasterTable(COMMAND, UpdateCRTC_DoubleBufferRegisters);
170 ENABLE_CRTC_PS_ALLOCATION args;
171
172 memset(&args, 0, sizeof(args));
173
174 args.ucCRTC = radeon_crtc->crtc_id;
175 args.ucEnable = lock;
176
177 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
178 }
179
atombios_enable_crtc(struct drm_crtc * crtc,int state)180 static void atombios_enable_crtc(struct drm_crtc *crtc, int state)
181 {
182 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
183 struct drm_device *dev = crtc->dev;
184 struct radeon_device *rdev = dev->dev_private;
185 int index = GetIndexIntoMasterTable(COMMAND, EnableCRTC);
186 ENABLE_CRTC_PS_ALLOCATION args;
187
188 memset(&args, 0, sizeof(args));
189
190 args.ucCRTC = radeon_crtc->crtc_id;
191 args.ucEnable = state;
192
193 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
194 }
195
atombios_enable_crtc_memreq(struct drm_crtc * crtc,int state)196 static void atombios_enable_crtc_memreq(struct drm_crtc *crtc, int state)
197 {
198 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
199 struct drm_device *dev = crtc->dev;
200 struct radeon_device *rdev = dev->dev_private;
201 int index = GetIndexIntoMasterTable(COMMAND, EnableCRTCMemReq);
202 ENABLE_CRTC_PS_ALLOCATION args;
203
204 memset(&args, 0, sizeof(args));
205
206 args.ucCRTC = radeon_crtc->crtc_id;
207 args.ucEnable = state;
208
209 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
210 }
211
212 static const u32 vga_control_regs[6] =
213 {
214 AVIVO_D1VGA_CONTROL,
215 AVIVO_D2VGA_CONTROL,
216 EVERGREEN_D3VGA_CONTROL,
217 EVERGREEN_D4VGA_CONTROL,
218 EVERGREEN_D5VGA_CONTROL,
219 EVERGREEN_D6VGA_CONTROL,
220 };
221
atombios_blank_crtc(struct drm_crtc * crtc,int state)222 static void atombios_blank_crtc(struct drm_crtc *crtc, int state)
223 {
224 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
225 struct drm_device *dev = crtc->dev;
226 struct radeon_device *rdev = dev->dev_private;
227 int index = GetIndexIntoMasterTable(COMMAND, BlankCRTC);
228 BLANK_CRTC_PS_ALLOCATION args;
229 u32 vga_control = 0;
230
231 memset(&args, 0, sizeof(args));
232
233 if (ASIC_IS_DCE8(rdev)) {
234 vga_control = RREG32(vga_control_regs[radeon_crtc->crtc_id]);
235 WREG32(vga_control_regs[radeon_crtc->crtc_id], vga_control | 1);
236 }
237
238 args.ucCRTC = radeon_crtc->crtc_id;
239 args.ucBlanking = state;
240
241 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
242
243 if (ASIC_IS_DCE8(rdev)) {
244 WREG32(vga_control_regs[radeon_crtc->crtc_id], vga_control);
245 }
246 }
247
atombios_powergate_crtc(struct drm_crtc * crtc,int state)248 static void atombios_powergate_crtc(struct drm_crtc *crtc, int state)
249 {
250 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
251 struct drm_device *dev = crtc->dev;
252 struct radeon_device *rdev = dev->dev_private;
253 int index = GetIndexIntoMasterTable(COMMAND, EnableDispPowerGating);
254 ENABLE_DISP_POWER_GATING_PARAMETERS_V2_1 args;
255
256 memset(&args, 0, sizeof(args));
257
258 args.ucDispPipeId = radeon_crtc->crtc_id;
259 args.ucEnable = state;
260
261 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
262 }
263
atombios_crtc_dpms(struct drm_crtc * crtc,int mode)264 void atombios_crtc_dpms(struct drm_crtc *crtc, int mode)
265 {
266 struct drm_device *dev = crtc->dev;
267 struct radeon_device *rdev = dev->dev_private;
268 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
269
270 switch (mode) {
271 case DRM_MODE_DPMS_ON:
272 radeon_crtc->enabled = true;
273 atombios_enable_crtc(crtc, ATOM_ENABLE);
274 if (ASIC_IS_DCE3(rdev) && !ASIC_IS_DCE6(rdev))
275 atombios_enable_crtc_memreq(crtc, ATOM_ENABLE);
276 atombios_blank_crtc(crtc, ATOM_DISABLE);
277 drm_vblank_post_modeset(dev, radeon_crtc->crtc_id);
278 radeon_crtc_load_lut(crtc);
279 break;
280 case DRM_MODE_DPMS_STANDBY:
281 case DRM_MODE_DPMS_SUSPEND:
282 case DRM_MODE_DPMS_OFF:
283 drm_vblank_pre_modeset(dev, radeon_crtc->crtc_id);
284 if (radeon_crtc->enabled)
285 atombios_blank_crtc(crtc, ATOM_ENABLE);
286 if (ASIC_IS_DCE3(rdev) && !ASIC_IS_DCE6(rdev))
287 atombios_enable_crtc_memreq(crtc, ATOM_DISABLE);
288 atombios_enable_crtc(crtc, ATOM_DISABLE);
289 radeon_crtc->enabled = false;
290 break;
291 }
292 /* adjust pm to dpms */
293 radeon_pm_compute_clocks(rdev);
294 }
295
296 static void
atombios_set_crtc_dtd_timing(struct drm_crtc * crtc,struct drm_display_mode * mode)297 atombios_set_crtc_dtd_timing(struct drm_crtc *crtc,
298 struct drm_display_mode *mode)
299 {
300 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
301 struct drm_device *dev = crtc->dev;
302 struct radeon_device *rdev = dev->dev_private;
303 SET_CRTC_USING_DTD_TIMING_PARAMETERS args;
304 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_UsingDTDTiming);
305 u16 misc = 0;
306
307 memset(&args, 0, sizeof(args));
308 args.usH_Size = cpu_to_le16(mode->crtc_hdisplay - (radeon_crtc->h_border * 2));
309 args.usH_Blanking_Time =
310 cpu_to_le16(mode->crtc_hblank_end - mode->crtc_hdisplay + (radeon_crtc->h_border * 2));
311 args.usV_Size = cpu_to_le16(mode->crtc_vdisplay - (radeon_crtc->v_border * 2));
312 args.usV_Blanking_Time =
313 cpu_to_le16(mode->crtc_vblank_end - mode->crtc_vdisplay + (radeon_crtc->v_border * 2));
314 args.usH_SyncOffset =
315 cpu_to_le16(mode->crtc_hsync_start - mode->crtc_hdisplay + radeon_crtc->h_border);
316 args.usH_SyncWidth =
317 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start);
318 args.usV_SyncOffset =
319 cpu_to_le16(mode->crtc_vsync_start - mode->crtc_vdisplay + radeon_crtc->v_border);
320 args.usV_SyncWidth =
321 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start);
322 args.ucH_Border = radeon_crtc->h_border;
323 args.ucV_Border = radeon_crtc->v_border;
324
325 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
326 misc |= ATOM_VSYNC_POLARITY;
327 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
328 misc |= ATOM_HSYNC_POLARITY;
329 if (mode->flags & DRM_MODE_FLAG_CSYNC)
330 misc |= ATOM_COMPOSITESYNC;
331 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
332 misc |= ATOM_INTERLACE;
333 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
334 misc |= ATOM_DOUBLE_CLOCK_MODE;
335 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
336 misc |= ATOM_H_REPLICATIONBY2 | ATOM_V_REPLICATIONBY2;
337
338 args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
339 args.ucCRTC = radeon_crtc->crtc_id;
340
341 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
342 }
343
atombios_crtc_set_timing(struct drm_crtc * crtc,struct drm_display_mode * mode)344 static void atombios_crtc_set_timing(struct drm_crtc *crtc,
345 struct drm_display_mode *mode)
346 {
347 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
348 struct drm_device *dev = crtc->dev;
349 struct radeon_device *rdev = dev->dev_private;
350 SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION args;
351 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_Timing);
352 u16 misc = 0;
353
354 memset(&args, 0, sizeof(args));
355 args.usH_Total = cpu_to_le16(mode->crtc_htotal);
356 args.usH_Disp = cpu_to_le16(mode->crtc_hdisplay);
357 args.usH_SyncStart = cpu_to_le16(mode->crtc_hsync_start);
358 args.usH_SyncWidth =
359 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start);
360 args.usV_Total = cpu_to_le16(mode->crtc_vtotal);
361 args.usV_Disp = cpu_to_le16(mode->crtc_vdisplay);
362 args.usV_SyncStart = cpu_to_le16(mode->crtc_vsync_start);
363 args.usV_SyncWidth =
364 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start);
365
366 args.ucOverscanRight = radeon_crtc->h_border;
367 args.ucOverscanLeft = radeon_crtc->h_border;
368 args.ucOverscanBottom = radeon_crtc->v_border;
369 args.ucOverscanTop = radeon_crtc->v_border;
370
371 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
372 misc |= ATOM_VSYNC_POLARITY;
373 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
374 misc |= ATOM_HSYNC_POLARITY;
375 if (mode->flags & DRM_MODE_FLAG_CSYNC)
376 misc |= ATOM_COMPOSITESYNC;
377 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
378 misc |= ATOM_INTERLACE;
379 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
380 misc |= ATOM_DOUBLE_CLOCK_MODE;
381 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
382 misc |= ATOM_H_REPLICATIONBY2 | ATOM_V_REPLICATIONBY2;
383
384 args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
385 args.ucCRTC = radeon_crtc->crtc_id;
386
387 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
388 }
389
atombios_disable_ss(struct radeon_device * rdev,int pll_id)390 static void atombios_disable_ss(struct radeon_device *rdev, int pll_id)
391 {
392 u32 ss_cntl;
393
394 if (ASIC_IS_DCE4(rdev)) {
395 switch (pll_id) {
396 case ATOM_PPLL1:
397 ss_cntl = RREG32(EVERGREEN_P1PLL_SS_CNTL);
398 ss_cntl &= ~EVERGREEN_PxPLL_SS_EN;
399 WREG32(EVERGREEN_P1PLL_SS_CNTL, ss_cntl);
400 break;
401 case ATOM_PPLL2:
402 ss_cntl = RREG32(EVERGREEN_P2PLL_SS_CNTL);
403 ss_cntl &= ~EVERGREEN_PxPLL_SS_EN;
404 WREG32(EVERGREEN_P2PLL_SS_CNTL, ss_cntl);
405 break;
406 case ATOM_DCPLL:
407 case ATOM_PPLL_INVALID:
408 return;
409 }
410 } else if (ASIC_IS_AVIVO(rdev)) {
411 switch (pll_id) {
412 case ATOM_PPLL1:
413 ss_cntl = RREG32(AVIVO_P1PLL_INT_SS_CNTL);
414 ss_cntl &= ~1;
415 WREG32(AVIVO_P1PLL_INT_SS_CNTL, ss_cntl);
416 break;
417 case ATOM_PPLL2:
418 ss_cntl = RREG32(AVIVO_P2PLL_INT_SS_CNTL);
419 ss_cntl &= ~1;
420 WREG32(AVIVO_P2PLL_INT_SS_CNTL, ss_cntl);
421 break;
422 case ATOM_DCPLL:
423 case ATOM_PPLL_INVALID:
424 return;
425 }
426 }
427 }
428
429
430 union atom_enable_ss {
431 ENABLE_LVDS_SS_PARAMETERS lvds_ss;
432 ENABLE_LVDS_SS_PARAMETERS_V2 lvds_ss_2;
433 ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION v1;
434 ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2 v2;
435 ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3 v3;
436 };
437
atombios_crtc_program_ss(struct radeon_device * rdev,int enable,int pll_id,int crtc_id,struct radeon_atom_ss * ss)438 static void atombios_crtc_program_ss(struct radeon_device *rdev,
439 int enable,
440 int pll_id,
441 int crtc_id,
442 struct radeon_atom_ss *ss)
443 {
444 unsigned i;
445 int index = GetIndexIntoMasterTable(COMMAND, EnableSpreadSpectrumOnPPLL);
446 union atom_enable_ss args;
447
448 if (enable) {
449 /* Don't mess with SS if percentage is 0 or external ss.
450 * SS is already disabled previously, and disabling it
451 * again can cause display problems if the pll is already
452 * programmed.
453 */
454 if (ss->percentage == 0)
455 return;
456 if (ss->type & ATOM_EXTERNAL_SS_MASK)
457 return;
458 } else {
459 for (i = 0; i < rdev->num_crtc; i++) {
460 if (rdev->mode_info.crtcs[i] &&
461 rdev->mode_info.crtcs[i]->enabled &&
462 i != crtc_id &&
463 pll_id == rdev->mode_info.crtcs[i]->pll_id) {
464 /* one other crtc is using this pll don't turn
465 * off spread spectrum as it might turn off
466 * display on active crtc
467 */
468 return;
469 }
470 }
471 }
472
473 memset(&args, 0, sizeof(args));
474
475 if (ASIC_IS_DCE5(rdev)) {
476 args.v3.usSpreadSpectrumAmountFrac = cpu_to_le16(0);
477 args.v3.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
478 switch (pll_id) {
479 case ATOM_PPLL1:
480 args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P1PLL;
481 break;
482 case ATOM_PPLL2:
483 args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P2PLL;
484 break;
485 case ATOM_DCPLL:
486 args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_DCPLL;
487 break;
488 case ATOM_PPLL_INVALID:
489 return;
490 }
491 args.v3.usSpreadSpectrumAmount = cpu_to_le16(ss->amount);
492 args.v3.usSpreadSpectrumStep = cpu_to_le16(ss->step);
493 args.v3.ucEnable = enable;
494 } else if (ASIC_IS_DCE4(rdev)) {
495 args.v2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
496 args.v2.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
497 switch (pll_id) {
498 case ATOM_PPLL1:
499 args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_P1PLL;
500 break;
501 case ATOM_PPLL2:
502 args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_P2PLL;
503 break;
504 case ATOM_DCPLL:
505 args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_DCPLL;
506 break;
507 case ATOM_PPLL_INVALID:
508 return;
509 }
510 args.v2.usSpreadSpectrumAmount = cpu_to_le16(ss->amount);
511 args.v2.usSpreadSpectrumStep = cpu_to_le16(ss->step);
512 args.v2.ucEnable = enable;
513 } else if (ASIC_IS_DCE3(rdev)) {
514 args.v1.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
515 args.v1.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
516 args.v1.ucSpreadSpectrumStep = ss->step;
517 args.v1.ucSpreadSpectrumDelay = ss->delay;
518 args.v1.ucSpreadSpectrumRange = ss->range;
519 args.v1.ucPpll = pll_id;
520 args.v1.ucEnable = enable;
521 } else if (ASIC_IS_AVIVO(rdev)) {
522 if ((enable == ATOM_DISABLE) || (ss->percentage == 0) ||
523 (ss->type & ATOM_EXTERNAL_SS_MASK)) {
524 atombios_disable_ss(rdev, pll_id);
525 return;
526 }
527 args.lvds_ss_2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
528 args.lvds_ss_2.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
529 args.lvds_ss_2.ucSpreadSpectrumStep = ss->step;
530 args.lvds_ss_2.ucSpreadSpectrumDelay = ss->delay;
531 args.lvds_ss_2.ucSpreadSpectrumRange = ss->range;
532 args.lvds_ss_2.ucEnable = enable;
533 } else {
534 if (enable == ATOM_DISABLE) {
535 atombios_disable_ss(rdev, pll_id);
536 return;
537 }
538 args.lvds_ss.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
539 args.lvds_ss.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
540 args.lvds_ss.ucSpreadSpectrumStepSize_Delay = (ss->step & 3) << 2;
541 args.lvds_ss.ucSpreadSpectrumStepSize_Delay |= (ss->delay & 7) << 4;
542 args.lvds_ss.ucEnable = enable;
543 }
544 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
545 }
546
547 union adjust_pixel_clock {
548 ADJUST_DISPLAY_PLL_PS_ALLOCATION v1;
549 ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3 v3;
550 };
551
atombios_adjust_pll(struct drm_crtc * crtc,struct drm_display_mode * mode)552 static u32 atombios_adjust_pll(struct drm_crtc *crtc,
553 struct drm_display_mode *mode)
554 {
555 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
556 struct drm_device *dev = crtc->dev;
557 struct radeon_device *rdev = dev->dev_private;
558 struct drm_encoder *encoder = radeon_crtc->encoder;
559 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
560 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
561 u32 adjusted_clock = mode->clock;
562 int encoder_mode = atombios_get_encoder_mode(encoder);
563 u32 dp_clock = mode->clock;
564 u32 clock = mode->clock;
565 int bpc = radeon_crtc->bpc;
566 bool is_duallink = radeon_dig_monitor_is_duallink(encoder, mode->clock);
567
568 /* reset the pll flags */
569 radeon_crtc->pll_flags = 0;
570
571 if (ASIC_IS_AVIVO(rdev)) {
572 if ((rdev->family == CHIP_RS600) ||
573 (rdev->family == CHIP_RS690) ||
574 (rdev->family == CHIP_RS740))
575 radeon_crtc->pll_flags |= (/*RADEON_PLL_USE_FRAC_FB_DIV |*/
576 RADEON_PLL_PREFER_CLOSEST_LOWER);
577
578 if (ASIC_IS_DCE32(rdev) && mode->clock > 200000) /* range limits??? */
579 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
580 else
581 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
582
583 if (rdev->family < CHIP_RV770)
584 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_MINM_OVER_MAXP;
585 /* use frac fb div on APUs */
586 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev) || ASIC_IS_DCE8(rdev))
587 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
588 /* use frac fb div on RS780/RS880 */
589 if (((rdev->family == CHIP_RS780) || (rdev->family == CHIP_RS880))
590 && !radeon_crtc->ss_enabled)
591 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
592 if (ASIC_IS_DCE32(rdev) && mode->clock > 165000)
593 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
594 } else {
595 radeon_crtc->pll_flags |= RADEON_PLL_LEGACY;
596
597 if (mode->clock > 200000) /* range limits??? */
598 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
599 else
600 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
601 }
602
603 if ((radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) ||
604 (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE)) {
605 if (connector) {
606 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
607 struct radeon_connector_atom_dig *dig_connector =
608 radeon_connector->con_priv;
609
610 dp_clock = dig_connector->dp_clock;
611 }
612 }
613
614 /* use recommended ref_div for ss */
615 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
616 if (radeon_crtc->ss_enabled) {
617 if (radeon_crtc->ss.refdiv) {
618 radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV;
619 radeon_crtc->pll_reference_div = radeon_crtc->ss.refdiv;
620 if (ASIC_IS_AVIVO(rdev) &&
621 rdev->family != CHIP_RS780 &&
622 rdev->family != CHIP_RS880)
623 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
624 }
625 }
626 }
627
628 if (ASIC_IS_AVIVO(rdev)) {
629 /* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */
630 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1)
631 adjusted_clock = mode->clock * 2;
632 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
633 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_CLOSEST_LOWER;
634 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
635 radeon_crtc->pll_flags |= RADEON_PLL_IS_LCD;
636 } else {
637 if (encoder->encoder_type != DRM_MODE_ENCODER_DAC)
638 radeon_crtc->pll_flags |= RADEON_PLL_NO_ODD_POST_DIV;
639 if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS)
640 radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV;
641 }
642
643 /* adjust pll for deep color modes */
644 if (encoder_mode == ATOM_ENCODER_MODE_HDMI) {
645 switch (bpc) {
646 case 8:
647 default:
648 break;
649 case 10:
650 clock = (clock * 5) / 4;
651 break;
652 case 12:
653 clock = (clock * 3) / 2;
654 break;
655 case 16:
656 clock = clock * 2;
657 break;
658 }
659 }
660
661 /* DCE3+ has an AdjustDisplayPll that will adjust the pixel clock
662 * accordingly based on the encoder/transmitter to work around
663 * special hw requirements.
664 */
665 if (ASIC_IS_DCE3(rdev)) {
666 union adjust_pixel_clock args;
667 u8 frev, crev;
668 int index;
669
670 index = GetIndexIntoMasterTable(COMMAND, AdjustDisplayPll);
671 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
672 &crev))
673 return adjusted_clock;
674
675 memset(&args, 0, sizeof(args));
676
677 switch (frev) {
678 case 1:
679 switch (crev) {
680 case 1:
681 case 2:
682 args.v1.usPixelClock = cpu_to_le16(clock / 10);
683 args.v1.ucTransmitterID = radeon_encoder->encoder_id;
684 args.v1.ucEncodeMode = encoder_mode;
685 if (radeon_crtc->ss_enabled && radeon_crtc->ss.percentage)
686 args.v1.ucConfig |=
687 ADJUST_DISPLAY_CONFIG_SS_ENABLE;
688
689 atom_execute_table(rdev->mode_info.atom_context,
690 index, (uint32_t *)&args);
691 adjusted_clock = le16_to_cpu(args.v1.usPixelClock) * 10;
692 break;
693 case 3:
694 args.v3.sInput.usPixelClock = cpu_to_le16(clock / 10);
695 args.v3.sInput.ucTransmitterID = radeon_encoder->encoder_id;
696 args.v3.sInput.ucEncodeMode = encoder_mode;
697 args.v3.sInput.ucDispPllConfig = 0;
698 if (radeon_crtc->ss_enabled && radeon_crtc->ss.percentage)
699 args.v3.sInput.ucDispPllConfig |=
700 DISPPLL_CONFIG_SS_ENABLE;
701 if (ENCODER_MODE_IS_DP(encoder_mode)) {
702 args.v3.sInput.ucDispPllConfig |=
703 DISPPLL_CONFIG_COHERENT_MODE;
704 /* 16200 or 27000 */
705 args.v3.sInput.usPixelClock = cpu_to_le16(dp_clock / 10);
706 } else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
707 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
708 if (dig->coherent_mode)
709 args.v3.sInput.ucDispPllConfig |=
710 DISPPLL_CONFIG_COHERENT_MODE;
711 if (is_duallink)
712 args.v3.sInput.ucDispPllConfig |=
713 DISPPLL_CONFIG_DUAL_LINK;
714 }
715 if (radeon_encoder_get_dp_bridge_encoder_id(encoder) !=
716 ENCODER_OBJECT_ID_NONE)
717 args.v3.sInput.ucExtTransmitterID =
718 radeon_encoder_get_dp_bridge_encoder_id(encoder);
719 else
720 args.v3.sInput.ucExtTransmitterID = 0;
721
722 atom_execute_table(rdev->mode_info.atom_context,
723 index, (uint32_t *)&args);
724 adjusted_clock = le32_to_cpu(args.v3.sOutput.ulDispPllFreq) * 10;
725 if (args.v3.sOutput.ucRefDiv) {
726 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
727 radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV;
728 radeon_crtc->pll_reference_div = args.v3.sOutput.ucRefDiv;
729 }
730 if (args.v3.sOutput.ucPostDiv) {
731 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
732 radeon_crtc->pll_flags |= RADEON_PLL_USE_POST_DIV;
733 radeon_crtc->pll_post_div = args.v3.sOutput.ucPostDiv;
734 }
735 break;
736 default:
737 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
738 return adjusted_clock;
739 }
740 break;
741 default:
742 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
743 return adjusted_clock;
744 }
745 }
746 return adjusted_clock;
747 }
748
749 union set_pixel_clock {
750 SET_PIXEL_CLOCK_PS_ALLOCATION base;
751 PIXEL_CLOCK_PARAMETERS v1;
752 PIXEL_CLOCK_PARAMETERS_V2 v2;
753 PIXEL_CLOCK_PARAMETERS_V3 v3;
754 PIXEL_CLOCK_PARAMETERS_V5 v5;
755 PIXEL_CLOCK_PARAMETERS_V6 v6;
756 };
757
758 /* on DCE5, make sure the voltage is high enough to support the
759 * required disp clk.
760 */
atombios_crtc_set_disp_eng_pll(struct radeon_device * rdev,u32 dispclk)761 static void atombios_crtc_set_disp_eng_pll(struct radeon_device *rdev,
762 u32 dispclk)
763 {
764 u8 frev, crev;
765 int index;
766 union set_pixel_clock args;
767
768 memset(&args, 0, sizeof(args));
769
770 index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
771 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
772 &crev))
773 return;
774
775 switch (frev) {
776 case 1:
777 switch (crev) {
778 case 5:
779 /* if the default dcpll clock is specified,
780 * SetPixelClock provides the dividers
781 */
782 args.v5.ucCRTC = ATOM_CRTC_INVALID;
783 args.v5.usPixelClock = cpu_to_le16(dispclk);
784 args.v5.ucPpll = ATOM_DCPLL;
785 break;
786 case 6:
787 /* if the default dcpll clock is specified,
788 * SetPixelClock provides the dividers
789 */
790 args.v6.ulDispEngClkFreq = cpu_to_le32(dispclk);
791 if (ASIC_IS_DCE61(rdev) || ASIC_IS_DCE8(rdev))
792 args.v6.ucPpll = ATOM_EXT_PLL1;
793 else if (ASIC_IS_DCE6(rdev))
794 args.v6.ucPpll = ATOM_PPLL0;
795 else
796 args.v6.ucPpll = ATOM_DCPLL;
797 break;
798 default:
799 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
800 return;
801 }
802 break;
803 default:
804 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
805 return;
806 }
807 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
808 }
809
atombios_crtc_program_pll(struct drm_crtc * crtc,u32 crtc_id,int pll_id,u32 encoder_mode,u32 encoder_id,u32 clock,u32 ref_div,u32 fb_div,u32 frac_fb_div,u32 post_div,int bpc,bool ss_enabled,struct radeon_atom_ss * ss)810 static void atombios_crtc_program_pll(struct drm_crtc *crtc,
811 u32 crtc_id,
812 int pll_id,
813 u32 encoder_mode,
814 u32 encoder_id,
815 u32 clock,
816 u32 ref_div,
817 u32 fb_div,
818 u32 frac_fb_div,
819 u32 post_div,
820 int bpc,
821 bool ss_enabled,
822 struct radeon_atom_ss *ss)
823 {
824 struct drm_device *dev = crtc->dev;
825 struct radeon_device *rdev = dev->dev_private;
826 u8 frev, crev;
827 int index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
828 union set_pixel_clock args;
829
830 memset(&args, 0, sizeof(args));
831
832 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
833 &crev))
834 return;
835
836 switch (frev) {
837 case 1:
838 switch (crev) {
839 case 1:
840 if (clock == ATOM_DISABLE)
841 return;
842 args.v1.usPixelClock = cpu_to_le16(clock / 10);
843 args.v1.usRefDiv = cpu_to_le16(ref_div);
844 args.v1.usFbDiv = cpu_to_le16(fb_div);
845 args.v1.ucFracFbDiv = frac_fb_div;
846 args.v1.ucPostDiv = post_div;
847 args.v1.ucPpll = pll_id;
848 args.v1.ucCRTC = crtc_id;
849 args.v1.ucRefDivSrc = 1;
850 break;
851 case 2:
852 args.v2.usPixelClock = cpu_to_le16(clock / 10);
853 args.v2.usRefDiv = cpu_to_le16(ref_div);
854 args.v2.usFbDiv = cpu_to_le16(fb_div);
855 args.v2.ucFracFbDiv = frac_fb_div;
856 args.v2.ucPostDiv = post_div;
857 args.v2.ucPpll = pll_id;
858 args.v2.ucCRTC = crtc_id;
859 args.v2.ucRefDivSrc = 1;
860 break;
861 case 3:
862 args.v3.usPixelClock = cpu_to_le16(clock / 10);
863 args.v3.usRefDiv = cpu_to_le16(ref_div);
864 args.v3.usFbDiv = cpu_to_le16(fb_div);
865 args.v3.ucFracFbDiv = frac_fb_div;
866 args.v3.ucPostDiv = post_div;
867 args.v3.ucPpll = pll_id;
868 if (crtc_id == ATOM_CRTC2)
869 args.v3.ucMiscInfo = PIXEL_CLOCK_MISC_CRTC_SEL_CRTC2;
870 else
871 args.v3.ucMiscInfo = PIXEL_CLOCK_MISC_CRTC_SEL_CRTC1;
872 if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK))
873 args.v3.ucMiscInfo |= PIXEL_CLOCK_MISC_REF_DIV_SRC;
874 args.v3.ucTransmitterId = encoder_id;
875 args.v3.ucEncoderMode = encoder_mode;
876 break;
877 case 5:
878 args.v5.ucCRTC = crtc_id;
879 args.v5.usPixelClock = cpu_to_le16(clock / 10);
880 args.v5.ucRefDiv = ref_div;
881 args.v5.usFbDiv = cpu_to_le16(fb_div);
882 args.v5.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000);
883 args.v5.ucPostDiv = post_div;
884 args.v5.ucMiscInfo = 0; /* HDMI depth, etc. */
885 if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK))
886 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_REF_DIV_SRC;
887 if (encoder_mode == ATOM_ENCODER_MODE_HDMI) {
888 switch (bpc) {
889 case 8:
890 default:
891 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_24BPP;
892 break;
893 case 10:
894 /* yes this is correct, the atom define is wrong */
895 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_32BPP;
896 break;
897 case 12:
898 /* yes this is correct, the atom define is wrong */
899 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_30BPP;
900 break;
901 }
902 }
903 args.v5.ucTransmitterID = encoder_id;
904 args.v5.ucEncoderMode = encoder_mode;
905 args.v5.ucPpll = pll_id;
906 break;
907 case 6:
908 args.v6.ulDispEngClkFreq = cpu_to_le32(crtc_id << 24 | clock / 10);
909 args.v6.ucRefDiv = ref_div;
910 args.v6.usFbDiv = cpu_to_le16(fb_div);
911 args.v6.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000);
912 args.v6.ucPostDiv = post_div;
913 args.v6.ucMiscInfo = 0; /* HDMI depth, etc. */
914 if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK))
915 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_REF_DIV_SRC;
916 if (encoder_mode == ATOM_ENCODER_MODE_HDMI) {
917 switch (bpc) {
918 case 8:
919 default:
920 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_24BPP;
921 break;
922 case 10:
923 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_30BPP_V6;
924 break;
925 case 12:
926 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_36BPP_V6;
927 break;
928 case 16:
929 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_48BPP;
930 break;
931 }
932 }
933 args.v6.ucTransmitterID = encoder_id;
934 args.v6.ucEncoderMode = encoder_mode;
935 args.v6.ucPpll = pll_id;
936 break;
937 default:
938 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
939 return;
940 }
941 break;
942 default:
943 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
944 return;
945 }
946
947 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
948 }
949
atombios_crtc_prepare_pll(struct drm_crtc * crtc,struct drm_display_mode * mode)950 static bool atombios_crtc_prepare_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
951 {
952 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
953 struct drm_device *dev = crtc->dev;
954 struct radeon_device *rdev = dev->dev_private;
955 struct radeon_encoder *radeon_encoder =
956 to_radeon_encoder(radeon_crtc->encoder);
957 int encoder_mode = atombios_get_encoder_mode(radeon_crtc->encoder);
958
959 radeon_crtc->bpc = 8;
960 radeon_crtc->ss_enabled = false;
961
962 if ((radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) ||
963 (radeon_encoder_get_dp_bridge_encoder_id(radeon_crtc->encoder) != ENCODER_OBJECT_ID_NONE)) {
964 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
965 struct drm_connector *connector =
966 radeon_get_connector_for_encoder(radeon_crtc->encoder);
967 struct radeon_connector *radeon_connector =
968 to_radeon_connector(connector);
969 struct radeon_connector_atom_dig *dig_connector =
970 radeon_connector->con_priv;
971 int dp_clock;
972
973 /* Assign mode clock for hdmi deep color max clock limit check */
974 radeon_connector->pixelclock_for_modeset = mode->clock;
975 radeon_crtc->bpc = radeon_get_monitor_bpc(connector);
976
977 switch (encoder_mode) {
978 case ATOM_ENCODER_MODE_DP_MST:
979 case ATOM_ENCODER_MODE_DP:
980 /* DP/eDP */
981 dp_clock = dig_connector->dp_clock / 10;
982 if (ASIC_IS_DCE4(rdev))
983 radeon_crtc->ss_enabled =
984 radeon_atombios_get_asic_ss_info(rdev, &radeon_crtc->ss,
985 ASIC_INTERNAL_SS_ON_DP,
986 dp_clock);
987 else {
988 if (dp_clock == 16200) {
989 radeon_crtc->ss_enabled =
990 radeon_atombios_get_ppll_ss_info(rdev,
991 &radeon_crtc->ss,
992 ATOM_DP_SS_ID2);
993 if (!radeon_crtc->ss_enabled)
994 radeon_crtc->ss_enabled =
995 radeon_atombios_get_ppll_ss_info(rdev,
996 &radeon_crtc->ss,
997 ATOM_DP_SS_ID1);
998 } else {
999 radeon_crtc->ss_enabled =
1000 radeon_atombios_get_ppll_ss_info(rdev,
1001 &radeon_crtc->ss,
1002 ATOM_DP_SS_ID1);
1003 }
1004 /* disable spread spectrum on DCE3 DP */
1005 radeon_crtc->ss_enabled = false;
1006 }
1007 break;
1008 case ATOM_ENCODER_MODE_LVDS:
1009 if (ASIC_IS_DCE4(rdev))
1010 radeon_crtc->ss_enabled =
1011 radeon_atombios_get_asic_ss_info(rdev,
1012 &radeon_crtc->ss,
1013 dig->lcd_ss_id,
1014 mode->clock / 10);
1015 else
1016 radeon_crtc->ss_enabled =
1017 radeon_atombios_get_ppll_ss_info(rdev,
1018 &radeon_crtc->ss,
1019 dig->lcd_ss_id);
1020 break;
1021 case ATOM_ENCODER_MODE_DVI:
1022 if (ASIC_IS_DCE4(rdev))
1023 radeon_crtc->ss_enabled =
1024 radeon_atombios_get_asic_ss_info(rdev,
1025 &radeon_crtc->ss,
1026 ASIC_INTERNAL_SS_ON_TMDS,
1027 mode->clock / 10);
1028 break;
1029 case ATOM_ENCODER_MODE_HDMI:
1030 if (ASIC_IS_DCE4(rdev))
1031 radeon_crtc->ss_enabled =
1032 radeon_atombios_get_asic_ss_info(rdev,
1033 &radeon_crtc->ss,
1034 ASIC_INTERNAL_SS_ON_HDMI,
1035 mode->clock / 10);
1036 break;
1037 default:
1038 break;
1039 }
1040 }
1041
1042 /* adjust pixel clock as needed */
1043 radeon_crtc->adjusted_clock = atombios_adjust_pll(crtc, mode);
1044
1045 return true;
1046 }
1047
atombios_crtc_set_pll(struct drm_crtc * crtc,struct drm_display_mode * mode)1048 static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
1049 {
1050 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1051 struct drm_device *dev = crtc->dev;
1052 struct radeon_device *rdev = dev->dev_private;
1053 struct radeon_encoder *radeon_encoder =
1054 to_radeon_encoder(radeon_crtc->encoder);
1055 u32 pll_clock = mode->clock;
1056 u32 clock = mode->clock;
1057 u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0;
1058 struct radeon_pll *pll;
1059 int encoder_mode = atombios_get_encoder_mode(radeon_crtc->encoder);
1060
1061 /* pass the actual clock to atombios_crtc_program_pll for DCE5,6 for HDMI */
1062 if (ASIC_IS_DCE5(rdev) &&
1063 (encoder_mode == ATOM_ENCODER_MODE_HDMI) &&
1064 (radeon_crtc->bpc > 8))
1065 clock = radeon_crtc->adjusted_clock;
1066
1067 switch (radeon_crtc->pll_id) {
1068 case ATOM_PPLL1:
1069 pll = &rdev->clock.p1pll;
1070 break;
1071 case ATOM_PPLL2:
1072 pll = &rdev->clock.p2pll;
1073 break;
1074 case ATOM_DCPLL:
1075 case ATOM_PPLL_INVALID:
1076 default:
1077 pll = &rdev->clock.dcpll;
1078 break;
1079 }
1080
1081 /* update pll params */
1082 pll->flags = radeon_crtc->pll_flags;
1083 pll->reference_div = radeon_crtc->pll_reference_div;
1084 pll->post_div = radeon_crtc->pll_post_div;
1085
1086 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1087 /* TV seems to prefer the legacy algo on some boards */
1088 radeon_compute_pll_legacy(pll, radeon_crtc->adjusted_clock, &pll_clock,
1089 &fb_div, &frac_fb_div, &ref_div, &post_div);
1090 else if (ASIC_IS_AVIVO(rdev))
1091 radeon_compute_pll_avivo(pll, radeon_crtc->adjusted_clock, &pll_clock,
1092 &fb_div, &frac_fb_div, &ref_div, &post_div);
1093 else
1094 radeon_compute_pll_legacy(pll, radeon_crtc->adjusted_clock, &pll_clock,
1095 &fb_div, &frac_fb_div, &ref_div, &post_div);
1096
1097 atombios_crtc_program_ss(rdev, ATOM_DISABLE, radeon_crtc->pll_id,
1098 radeon_crtc->crtc_id, &radeon_crtc->ss);
1099
1100 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
1101 encoder_mode, radeon_encoder->encoder_id, clock,
1102 ref_div, fb_div, frac_fb_div, post_div,
1103 radeon_crtc->bpc, radeon_crtc->ss_enabled, &radeon_crtc->ss);
1104
1105 if (radeon_crtc->ss_enabled) {
1106 /* calculate ss amount and step size */
1107 if (ASIC_IS_DCE4(rdev)) {
1108 u32 step_size;
1109 u32 amount = (((fb_div * 10) + frac_fb_div) *
1110 (u32)radeon_crtc->ss.percentage) /
1111 (100 * (u32)radeon_crtc->ss.percentage_divider);
1112 radeon_crtc->ss.amount = (amount / 10) & ATOM_PPLL_SS_AMOUNT_V2_FBDIV_MASK;
1113 radeon_crtc->ss.amount |= ((amount - (amount / 10)) << ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT) &
1114 ATOM_PPLL_SS_AMOUNT_V2_NFRAC_MASK;
1115 if (radeon_crtc->ss.type & ATOM_PPLL_SS_TYPE_V2_CENTRE_SPREAD)
1116 step_size = (4 * amount * ref_div * ((u32)radeon_crtc->ss.rate * 2048)) /
1117 (125 * 25 * pll->reference_freq / 100);
1118 else
1119 step_size = (2 * amount * ref_div * ((u32)radeon_crtc->ss.rate * 2048)) /
1120 (125 * 25 * pll->reference_freq / 100);
1121 radeon_crtc->ss.step = step_size;
1122 }
1123
1124 atombios_crtc_program_ss(rdev, ATOM_ENABLE, radeon_crtc->pll_id,
1125 radeon_crtc->crtc_id, &radeon_crtc->ss);
1126 }
1127 }
1128
dce4_crtc_do_set_base(struct drm_crtc * crtc,struct drm_framebuffer * fb,int x,int y,int atomic)1129 static int dce4_crtc_do_set_base(struct drm_crtc *crtc,
1130 struct drm_framebuffer *fb,
1131 int x, int y, int atomic)
1132 {
1133 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1134 struct drm_device *dev = crtc->dev;
1135 struct radeon_device *rdev = dev->dev_private;
1136 struct radeon_framebuffer *radeon_fb;
1137 struct drm_framebuffer *target_fb;
1138 struct drm_gem_object *obj;
1139 struct radeon_bo *rbo;
1140 uint64_t fb_location;
1141 uint32_t fb_format, fb_pitch_pixels, tiling_flags;
1142 unsigned bankw, bankh, mtaspect, tile_split;
1143 u32 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_NONE);
1144 u32 tmp, viewport_w, viewport_h;
1145 int r;
1146 bool bypass_lut = false;
1147
1148 /* no fb bound */
1149 if (!atomic && !crtc->primary->fb) {
1150 DRM_DEBUG_KMS("No FB bound\n");
1151 return 0;
1152 }
1153
1154 if (atomic) {
1155 radeon_fb = to_radeon_framebuffer(fb);
1156 target_fb = fb;
1157 }
1158 else {
1159 radeon_fb = to_radeon_framebuffer(crtc->primary->fb);
1160 target_fb = crtc->primary->fb;
1161 }
1162
1163 /* If atomic, assume fb object is pinned & idle & fenced and
1164 * just update base pointers
1165 */
1166 obj = radeon_fb->obj;
1167 rbo = gem_to_radeon_bo(obj);
1168 r = radeon_bo_reserve(rbo, false);
1169 if (unlikely(r != 0))
1170 return r;
1171
1172 if (atomic)
1173 fb_location = radeon_bo_gpu_offset(rbo);
1174 else {
1175 r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location);
1176 if (unlikely(r != 0)) {
1177 radeon_bo_unreserve(rbo);
1178 return -EINVAL;
1179 }
1180 }
1181
1182 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
1183 radeon_bo_unreserve(rbo);
1184
1185 switch (target_fb->pixel_format) {
1186 case DRM_FORMAT_C8:
1187 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_8BPP) |
1188 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_INDEXED));
1189 break;
1190 case DRM_FORMAT_XRGB4444:
1191 case DRM_FORMAT_ARGB4444:
1192 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
1193 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB4444));
1194 #ifdef __BIG_ENDIAN
1195 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16);
1196 #endif
1197 break;
1198 case DRM_FORMAT_XRGB1555:
1199 case DRM_FORMAT_ARGB1555:
1200 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
1201 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB1555));
1202 #ifdef __BIG_ENDIAN
1203 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16);
1204 #endif
1205 break;
1206 case DRM_FORMAT_BGRX5551:
1207 case DRM_FORMAT_BGRA5551:
1208 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
1209 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_BGRA5551));
1210 #ifdef __BIG_ENDIAN
1211 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16);
1212 #endif
1213 break;
1214 case DRM_FORMAT_RGB565:
1215 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
1216 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB565));
1217 #ifdef __BIG_ENDIAN
1218 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16);
1219 #endif
1220 break;
1221 case DRM_FORMAT_XRGB8888:
1222 case DRM_FORMAT_ARGB8888:
1223 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) |
1224 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB8888));
1225 #ifdef __BIG_ENDIAN
1226 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32);
1227 #endif
1228 break;
1229 case DRM_FORMAT_XRGB2101010:
1230 case DRM_FORMAT_ARGB2101010:
1231 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) |
1232 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB2101010));
1233 #ifdef __BIG_ENDIAN
1234 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32);
1235 #endif
1236 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
1237 bypass_lut = true;
1238 break;
1239 case DRM_FORMAT_BGRX1010102:
1240 case DRM_FORMAT_BGRA1010102:
1241 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) |
1242 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_BGRA1010102));
1243 #ifdef __BIG_ENDIAN
1244 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32);
1245 #endif
1246 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
1247 bypass_lut = true;
1248 break;
1249 default:
1250 DRM_ERROR("Unsupported screen format %s\n",
1251 drm_get_format_name(target_fb->pixel_format));
1252 return -EINVAL;
1253 }
1254
1255 if (tiling_flags & RADEON_TILING_MACRO) {
1256 evergreen_tiling_fields(tiling_flags, &bankw, &bankh, &mtaspect, &tile_split);
1257
1258 /* Set NUM_BANKS. */
1259 if (rdev->family >= CHIP_TAHITI) {
1260 unsigned index, num_banks;
1261
1262 if (rdev->family >= CHIP_BONAIRE) {
1263 unsigned tileb, tile_split_bytes;
1264
1265 /* Calculate the macrotile mode index. */
1266 tile_split_bytes = 64 << tile_split;
1267 tileb = 8 * 8 * target_fb->bits_per_pixel / 8;
1268 tileb = min(tile_split_bytes, tileb);
1269
1270 for (index = 0; tileb > 64; index++)
1271 tileb >>= 1;
1272
1273 if (index >= 16) {
1274 DRM_ERROR("Wrong screen bpp (%u) or tile split (%u)\n",
1275 target_fb->bits_per_pixel, tile_split);
1276 return -EINVAL;
1277 }
1278
1279 num_banks = (rdev->config.cik.macrotile_mode_array[index] >> 6) & 0x3;
1280 } else {
1281 switch (target_fb->bits_per_pixel) {
1282 case 8:
1283 index = 10;
1284 break;
1285 case 16:
1286 index = SI_TILE_MODE_COLOR_2D_SCANOUT_16BPP;
1287 break;
1288 default:
1289 case 32:
1290 index = SI_TILE_MODE_COLOR_2D_SCANOUT_32BPP;
1291 break;
1292 }
1293
1294 num_banks = (rdev->config.si.tile_mode_array[index] >> 20) & 0x3;
1295 }
1296
1297 fb_format |= EVERGREEN_GRPH_NUM_BANKS(num_banks);
1298 } else {
1299 /* NI and older. */
1300 if (rdev->family >= CHIP_CAYMAN)
1301 tmp = rdev->config.cayman.tile_config;
1302 else
1303 tmp = rdev->config.evergreen.tile_config;
1304
1305 switch ((tmp & 0xf0) >> 4) {
1306 case 0: /* 4 banks */
1307 fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_4_BANK);
1308 break;
1309 case 1: /* 8 banks */
1310 default:
1311 fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_8_BANK);
1312 break;
1313 case 2: /* 16 banks */
1314 fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_16_BANK);
1315 break;
1316 }
1317 }
1318
1319 fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_2D_TILED_THIN1);
1320 fb_format |= EVERGREEN_GRPH_TILE_SPLIT(tile_split);
1321 fb_format |= EVERGREEN_GRPH_BANK_WIDTH(bankw);
1322 fb_format |= EVERGREEN_GRPH_BANK_HEIGHT(bankh);
1323 fb_format |= EVERGREEN_GRPH_MACRO_TILE_ASPECT(mtaspect);
1324 if (rdev->family >= CHIP_BONAIRE) {
1325 /* XXX need to know more about the surface tiling mode */
1326 fb_format |= CIK_GRPH_MICRO_TILE_MODE(CIK_DISPLAY_MICRO_TILING);
1327 }
1328 } else if (tiling_flags & RADEON_TILING_MICRO)
1329 fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_1D_TILED_THIN1);
1330
1331 if (rdev->family >= CHIP_BONAIRE) {
1332 /* Read the pipe config from the 2D TILED SCANOUT mode.
1333 * It should be the same for the other modes too, but not all
1334 * modes set the pipe config field. */
1335 u32 pipe_config = (rdev->config.cik.tile_mode_array[10] >> 6) & 0x1f;
1336
1337 fb_format |= CIK_GRPH_PIPE_CONFIG(pipe_config);
1338 } else if ((rdev->family == CHIP_TAHITI) ||
1339 (rdev->family == CHIP_PITCAIRN))
1340 fb_format |= SI_GRPH_PIPE_CONFIG(SI_ADDR_SURF_P8_32x32_8x16);
1341 else if ((rdev->family == CHIP_VERDE) ||
1342 (rdev->family == CHIP_OLAND) ||
1343 (rdev->family == CHIP_HAINAN)) /* for completeness. HAINAN has no display hw */
1344 fb_format |= SI_GRPH_PIPE_CONFIG(SI_ADDR_SURF_P4_8x16);
1345
1346 switch (radeon_crtc->crtc_id) {
1347 case 0:
1348 WREG32(AVIVO_D1VGA_CONTROL, 0);
1349 break;
1350 case 1:
1351 WREG32(AVIVO_D2VGA_CONTROL, 0);
1352 break;
1353 case 2:
1354 WREG32(EVERGREEN_D3VGA_CONTROL, 0);
1355 break;
1356 case 3:
1357 WREG32(EVERGREEN_D4VGA_CONTROL, 0);
1358 break;
1359 case 4:
1360 WREG32(EVERGREEN_D5VGA_CONTROL, 0);
1361 break;
1362 case 5:
1363 WREG32(EVERGREEN_D6VGA_CONTROL, 0);
1364 break;
1365 default:
1366 break;
1367 }
1368
1369 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
1370 upper_32_bits(fb_location));
1371 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
1372 upper_32_bits(fb_location));
1373 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
1374 (u32)fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK);
1375 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
1376 (u32) fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK);
1377 WREG32(EVERGREEN_GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);
1378 WREG32(EVERGREEN_GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap);
1379
1380 /*
1381 * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT
1382 * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to
1383 * retain the full precision throughout the pipeline.
1384 */
1385 WREG32_P(EVERGREEN_GRPH_LUT_10BIT_BYPASS_CONTROL + radeon_crtc->crtc_offset,
1386 (bypass_lut ? EVERGREEN_LUT_10BIT_BYPASS_EN : 0),
1387 ~EVERGREEN_LUT_10BIT_BYPASS_EN);
1388
1389 if (bypass_lut)
1390 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n");
1391
1392 WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
1393 WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
1394 WREG32(EVERGREEN_GRPH_X_START + radeon_crtc->crtc_offset, 0);
1395 WREG32(EVERGREEN_GRPH_Y_START + radeon_crtc->crtc_offset, 0);
1396 WREG32(EVERGREEN_GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width);
1397 WREG32(EVERGREEN_GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height);
1398
1399 fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8);
1400 WREG32(EVERGREEN_GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);
1401 WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
1402
1403 if (rdev->family >= CHIP_BONAIRE)
1404 WREG32(CIK_LB_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
1405 target_fb->height);
1406 else
1407 WREG32(EVERGREEN_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
1408 target_fb->height);
1409 x &= ~3;
1410 y &= ~1;
1411 WREG32(EVERGREEN_VIEWPORT_START + radeon_crtc->crtc_offset,
1412 (x << 16) | y);
1413 viewport_w = crtc->mode.hdisplay;
1414 viewport_h = (crtc->mode.vdisplay + 1) & ~1;
1415 if ((rdev->family >= CHIP_BONAIRE) &&
1416 (crtc->mode.flags & DRM_MODE_FLAG_INTERLACE))
1417 viewport_h *= 2;
1418 WREG32(EVERGREEN_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
1419 (viewport_w << 16) | viewport_h);
1420
1421 /* pageflip setup */
1422 /* make sure flip is at vb rather than hb */
1423 tmp = RREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset);
1424 tmp &= ~EVERGREEN_GRPH_SURFACE_UPDATE_H_RETRACE_EN;
1425 WREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, tmp);
1426
1427 /* set pageflip to happen only at start of vblank interval (front porch) */
1428 WREG32(EVERGREEN_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 3);
1429
1430 if (!atomic && fb && fb != crtc->primary->fb) {
1431 radeon_fb = to_radeon_framebuffer(fb);
1432 rbo = gem_to_radeon_bo(radeon_fb->obj);
1433 r = radeon_bo_reserve(rbo, false);
1434 if (unlikely(r != 0))
1435 return r;
1436 radeon_bo_unpin(rbo);
1437 radeon_bo_unreserve(rbo);
1438 }
1439
1440 /* Bytes per pixel may have changed */
1441 radeon_bandwidth_update(rdev);
1442
1443 return 0;
1444 }
1445
avivo_crtc_do_set_base(struct drm_crtc * crtc,struct drm_framebuffer * fb,int x,int y,int atomic)1446 static int avivo_crtc_do_set_base(struct drm_crtc *crtc,
1447 struct drm_framebuffer *fb,
1448 int x, int y, int atomic)
1449 {
1450 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1451 struct drm_device *dev = crtc->dev;
1452 struct radeon_device *rdev = dev->dev_private;
1453 struct radeon_framebuffer *radeon_fb;
1454 struct drm_gem_object *obj;
1455 struct radeon_bo *rbo;
1456 struct drm_framebuffer *target_fb;
1457 uint64_t fb_location;
1458 uint32_t fb_format, fb_pitch_pixels, tiling_flags;
1459 u32 fb_swap = R600_D1GRPH_SWAP_ENDIAN_NONE;
1460 u32 tmp, viewport_w, viewport_h;
1461 int r;
1462 bool bypass_lut = false;
1463
1464 /* no fb bound */
1465 if (!atomic && !crtc->primary->fb) {
1466 DRM_DEBUG_KMS("No FB bound\n");
1467 return 0;
1468 }
1469
1470 if (atomic) {
1471 radeon_fb = to_radeon_framebuffer(fb);
1472 target_fb = fb;
1473 }
1474 else {
1475 radeon_fb = to_radeon_framebuffer(crtc->primary->fb);
1476 target_fb = crtc->primary->fb;
1477 }
1478
1479 obj = radeon_fb->obj;
1480 rbo = gem_to_radeon_bo(obj);
1481 r = radeon_bo_reserve(rbo, false);
1482 if (unlikely(r != 0))
1483 return r;
1484
1485 /* If atomic, assume fb object is pinned & idle & fenced and
1486 * just update base pointers
1487 */
1488 if (atomic)
1489 fb_location = radeon_bo_gpu_offset(rbo);
1490 else {
1491 r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location);
1492 if (unlikely(r != 0)) {
1493 radeon_bo_unreserve(rbo);
1494 return -EINVAL;
1495 }
1496 }
1497 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
1498 radeon_bo_unreserve(rbo);
1499
1500 switch (target_fb->pixel_format) {
1501 case DRM_FORMAT_C8:
1502 fb_format =
1503 AVIVO_D1GRPH_CONTROL_DEPTH_8BPP |
1504 AVIVO_D1GRPH_CONTROL_8BPP_INDEXED;
1505 break;
1506 case DRM_FORMAT_XRGB4444:
1507 case DRM_FORMAT_ARGB4444:
1508 fb_format =
1509 AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
1510 AVIVO_D1GRPH_CONTROL_16BPP_ARGB4444;
1511 #ifdef __BIG_ENDIAN
1512 fb_swap = R600_D1GRPH_SWAP_ENDIAN_16BIT;
1513 #endif
1514 break;
1515 case DRM_FORMAT_XRGB1555:
1516 fb_format =
1517 AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
1518 AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555;
1519 #ifdef __BIG_ENDIAN
1520 fb_swap = R600_D1GRPH_SWAP_ENDIAN_16BIT;
1521 #endif
1522 break;
1523 case DRM_FORMAT_RGB565:
1524 fb_format =
1525 AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
1526 AVIVO_D1GRPH_CONTROL_16BPP_RGB565;
1527 #ifdef __BIG_ENDIAN
1528 fb_swap = R600_D1GRPH_SWAP_ENDIAN_16BIT;
1529 #endif
1530 break;
1531 case DRM_FORMAT_XRGB8888:
1532 case DRM_FORMAT_ARGB8888:
1533 fb_format =
1534 AVIVO_D1GRPH_CONTROL_DEPTH_32BPP |
1535 AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888;
1536 #ifdef __BIG_ENDIAN
1537 fb_swap = R600_D1GRPH_SWAP_ENDIAN_32BIT;
1538 #endif
1539 break;
1540 case DRM_FORMAT_XRGB2101010:
1541 case DRM_FORMAT_ARGB2101010:
1542 fb_format =
1543 AVIVO_D1GRPH_CONTROL_DEPTH_32BPP |
1544 AVIVO_D1GRPH_CONTROL_32BPP_ARGB2101010;
1545 #ifdef __BIG_ENDIAN
1546 fb_swap = R600_D1GRPH_SWAP_ENDIAN_32BIT;
1547 #endif
1548 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
1549 bypass_lut = true;
1550 break;
1551 default:
1552 DRM_ERROR("Unsupported screen format %s\n",
1553 drm_get_format_name(target_fb->pixel_format));
1554 return -EINVAL;
1555 }
1556
1557 if (rdev->family >= CHIP_R600) {
1558 if (tiling_flags & RADEON_TILING_MACRO)
1559 fb_format |= R600_D1GRPH_ARRAY_MODE_2D_TILED_THIN1;
1560 else if (tiling_flags & RADEON_TILING_MICRO)
1561 fb_format |= R600_D1GRPH_ARRAY_MODE_1D_TILED_THIN1;
1562 } else {
1563 if (tiling_flags & RADEON_TILING_MACRO)
1564 fb_format |= AVIVO_D1GRPH_MACRO_ADDRESS_MODE;
1565
1566 if (tiling_flags & RADEON_TILING_MICRO)
1567 fb_format |= AVIVO_D1GRPH_TILED;
1568 }
1569
1570 if (radeon_crtc->crtc_id == 0)
1571 WREG32(AVIVO_D1VGA_CONTROL, 0);
1572 else
1573 WREG32(AVIVO_D2VGA_CONTROL, 0);
1574
1575 if (rdev->family >= CHIP_RV770) {
1576 if (radeon_crtc->crtc_id) {
1577 WREG32(R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1578 WREG32(R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1579 } else {
1580 WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1581 WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1582 }
1583 }
1584 WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
1585 (u32) fb_location);
1586 WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS +
1587 radeon_crtc->crtc_offset, (u32) fb_location);
1588 WREG32(AVIVO_D1GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);
1589 if (rdev->family >= CHIP_R600)
1590 WREG32(R600_D1GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap);
1591
1592 /* LUT only has 256 slots for 8 bpc fb. Bypass for > 8 bpc scanout for precision */
1593 WREG32_P(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset,
1594 (bypass_lut ? AVIVO_LUT_10BIT_BYPASS_EN : 0), ~AVIVO_LUT_10BIT_BYPASS_EN);
1595
1596 if (bypass_lut)
1597 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n");
1598
1599 WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
1600 WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
1601 WREG32(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, 0);
1602 WREG32(AVIVO_D1GRPH_Y_START + radeon_crtc->crtc_offset, 0);
1603 WREG32(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width);
1604 WREG32(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height);
1605
1606 fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8);
1607 WREG32(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);
1608 WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
1609
1610 WREG32(AVIVO_D1MODE_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
1611 target_fb->height);
1612 x &= ~3;
1613 y &= ~1;
1614 WREG32(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset,
1615 (x << 16) | y);
1616 viewport_w = crtc->mode.hdisplay;
1617 viewport_h = (crtc->mode.vdisplay + 1) & ~1;
1618 WREG32(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
1619 (viewport_w << 16) | viewport_h);
1620
1621 /* pageflip setup */
1622 /* make sure flip is at vb rather than hb */
1623 tmp = RREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset);
1624 tmp &= ~AVIVO_D1GRPH_SURFACE_UPDATE_H_RETRACE_EN;
1625 WREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, tmp);
1626
1627 /* set pageflip to happen only at start of vblank interval (front porch) */
1628 WREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 3);
1629
1630 if (!atomic && fb && fb != crtc->primary->fb) {
1631 radeon_fb = to_radeon_framebuffer(fb);
1632 rbo = gem_to_radeon_bo(radeon_fb->obj);
1633 r = radeon_bo_reserve(rbo, false);
1634 if (unlikely(r != 0))
1635 return r;
1636 radeon_bo_unpin(rbo);
1637 radeon_bo_unreserve(rbo);
1638 }
1639
1640 /* Bytes per pixel may have changed */
1641 radeon_bandwidth_update(rdev);
1642
1643 return 0;
1644 }
1645
atombios_crtc_set_base(struct drm_crtc * crtc,int x,int y,struct drm_framebuffer * old_fb)1646 int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
1647 struct drm_framebuffer *old_fb)
1648 {
1649 struct drm_device *dev = crtc->dev;
1650 struct radeon_device *rdev = dev->dev_private;
1651
1652 if (ASIC_IS_DCE4(rdev))
1653 return dce4_crtc_do_set_base(crtc, old_fb, x, y, 0);
1654 else if (ASIC_IS_AVIVO(rdev))
1655 return avivo_crtc_do_set_base(crtc, old_fb, x, y, 0);
1656 else
1657 return radeon_crtc_do_set_base(crtc, old_fb, x, y, 0);
1658 }
1659
atombios_crtc_set_base_atomic(struct drm_crtc * crtc,struct drm_framebuffer * fb,int x,int y,enum mode_set_atomic state)1660 int atombios_crtc_set_base_atomic(struct drm_crtc *crtc,
1661 struct drm_framebuffer *fb,
1662 int x, int y, enum mode_set_atomic state)
1663 {
1664 struct drm_device *dev = crtc->dev;
1665 struct radeon_device *rdev = dev->dev_private;
1666
1667 if (ASIC_IS_DCE4(rdev))
1668 return dce4_crtc_do_set_base(crtc, fb, x, y, 1);
1669 else if (ASIC_IS_AVIVO(rdev))
1670 return avivo_crtc_do_set_base(crtc, fb, x, y, 1);
1671 else
1672 return radeon_crtc_do_set_base(crtc, fb, x, y, 1);
1673 }
1674
1675 /* properly set additional regs when using atombios */
radeon_legacy_atom_fixup(struct drm_crtc * crtc)1676 static void radeon_legacy_atom_fixup(struct drm_crtc *crtc)
1677 {
1678 struct drm_device *dev = crtc->dev;
1679 struct radeon_device *rdev = dev->dev_private;
1680 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1681 u32 disp_merge_cntl;
1682
1683 switch (radeon_crtc->crtc_id) {
1684 case 0:
1685 disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL);
1686 disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN;
1687 WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl);
1688 break;
1689 case 1:
1690 disp_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL);
1691 disp_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN;
1692 WREG32(RADEON_DISP2_MERGE_CNTL, disp_merge_cntl);
1693 WREG32(RADEON_FP_H2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_H_SYNC_STRT_WID));
1694 WREG32(RADEON_FP_V2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_V_SYNC_STRT_WID));
1695 break;
1696 }
1697 }
1698
1699 /**
1700 * radeon_get_pll_use_mask - look up a mask of which pplls are in use
1701 *
1702 * @crtc: drm crtc
1703 *
1704 * Returns the mask of which PPLLs (Pixel PLLs) are in use.
1705 */
radeon_get_pll_use_mask(struct drm_crtc * crtc)1706 static u32 radeon_get_pll_use_mask(struct drm_crtc *crtc)
1707 {
1708 struct drm_device *dev = crtc->dev;
1709 struct drm_crtc *test_crtc;
1710 struct radeon_crtc *test_radeon_crtc;
1711 u32 pll_in_use = 0;
1712
1713 list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) {
1714 if (crtc == test_crtc)
1715 continue;
1716
1717 test_radeon_crtc = to_radeon_crtc(test_crtc);
1718 if (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID)
1719 pll_in_use |= (1 << test_radeon_crtc->pll_id);
1720 }
1721 return pll_in_use;
1722 }
1723
1724 /**
1725 * radeon_get_shared_dp_ppll - return the PPLL used by another crtc for DP
1726 *
1727 * @crtc: drm crtc
1728 *
1729 * Returns the PPLL (Pixel PLL) used by another crtc/encoder which is
1730 * also in DP mode. For DP, a single PPLL can be used for all DP
1731 * crtcs/encoders.
1732 */
radeon_get_shared_dp_ppll(struct drm_crtc * crtc)1733 static int radeon_get_shared_dp_ppll(struct drm_crtc *crtc)
1734 {
1735 struct drm_device *dev = crtc->dev;
1736 struct radeon_device *rdev = dev->dev_private;
1737 struct drm_crtc *test_crtc;
1738 struct radeon_crtc *test_radeon_crtc;
1739
1740 list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) {
1741 if (crtc == test_crtc)
1742 continue;
1743 test_radeon_crtc = to_radeon_crtc(test_crtc);
1744 if (test_radeon_crtc->encoder &&
1745 ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_radeon_crtc->encoder))) {
1746 /* PPLL2 is exclusive to UNIPHYA on DCE61 */
1747 if (ASIC_IS_DCE61(rdev) && !ASIC_IS_DCE8(rdev) &&
1748 test_radeon_crtc->pll_id == ATOM_PPLL2)
1749 continue;
1750 /* for DP use the same PLL for all */
1751 if (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID)
1752 return test_radeon_crtc->pll_id;
1753 }
1754 }
1755 return ATOM_PPLL_INVALID;
1756 }
1757
1758 /**
1759 * radeon_get_shared_nondp_ppll - return the PPLL used by another non-DP crtc
1760 *
1761 * @crtc: drm crtc
1762 * @encoder: drm encoder
1763 *
1764 * Returns the PPLL (Pixel PLL) used by another non-DP crtc/encoder which can
1765 * be shared (i.e., same clock).
1766 */
radeon_get_shared_nondp_ppll(struct drm_crtc * crtc)1767 static int radeon_get_shared_nondp_ppll(struct drm_crtc *crtc)
1768 {
1769 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1770 struct drm_device *dev = crtc->dev;
1771 struct radeon_device *rdev = dev->dev_private;
1772 struct drm_crtc *test_crtc;
1773 struct radeon_crtc *test_radeon_crtc;
1774 u32 adjusted_clock, test_adjusted_clock;
1775
1776 adjusted_clock = radeon_crtc->adjusted_clock;
1777
1778 if (adjusted_clock == 0)
1779 return ATOM_PPLL_INVALID;
1780
1781 list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) {
1782 if (crtc == test_crtc)
1783 continue;
1784 test_radeon_crtc = to_radeon_crtc(test_crtc);
1785 if (test_radeon_crtc->encoder &&
1786 !ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_radeon_crtc->encoder))) {
1787 /* PPLL2 is exclusive to UNIPHYA on DCE61 */
1788 if (ASIC_IS_DCE61(rdev) && !ASIC_IS_DCE8(rdev) &&
1789 test_radeon_crtc->pll_id == ATOM_PPLL2)
1790 continue;
1791 /* check if we are already driving this connector with another crtc */
1792 if (test_radeon_crtc->connector == radeon_crtc->connector) {
1793 /* if we are, return that pll */
1794 if (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID)
1795 return test_radeon_crtc->pll_id;
1796 }
1797 /* for non-DP check the clock */
1798 test_adjusted_clock = test_radeon_crtc->adjusted_clock;
1799 if ((crtc->mode.clock == test_crtc->mode.clock) &&
1800 (adjusted_clock == test_adjusted_clock) &&
1801 (radeon_crtc->ss_enabled == test_radeon_crtc->ss_enabled) &&
1802 (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID))
1803 return test_radeon_crtc->pll_id;
1804 }
1805 }
1806 return ATOM_PPLL_INVALID;
1807 }
1808
1809 /**
1810 * radeon_atom_pick_pll - Allocate a PPLL for use by the crtc.
1811 *
1812 * @crtc: drm crtc
1813 *
1814 * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors
1815 * a single PPLL can be used for all DP crtcs/encoders. For non-DP
1816 * monitors a dedicated PPLL must be used. If a particular board has
1817 * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming
1818 * as there is no need to program the PLL itself. If we are not able to
1819 * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to
1820 * avoid messing up an existing monitor.
1821 *
1822 * Asic specific PLL information
1823 *
1824 * DCE 8.x
1825 * KB/KV
1826 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP)
1827 * CI
1828 * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
1829 *
1830 * DCE 6.1
1831 * - PPLL2 is only available to UNIPHYA (both DP and non-DP)
1832 * - PPLL0, PPLL1 are available for UNIPHYB/C/D/E/F (both DP and non-DP)
1833 *
1834 * DCE 6.0
1835 * - PPLL0 is available to all UNIPHY (DP only)
1836 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
1837 *
1838 * DCE 5.0
1839 * - DCPLL is available to all UNIPHY (DP only)
1840 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
1841 *
1842 * DCE 3.0/4.0/4.1
1843 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
1844 *
1845 */
radeon_atom_pick_pll(struct drm_crtc * crtc)1846 static int radeon_atom_pick_pll(struct drm_crtc *crtc)
1847 {
1848 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1849 struct drm_device *dev = crtc->dev;
1850 struct radeon_device *rdev = dev->dev_private;
1851 struct radeon_encoder *radeon_encoder =
1852 to_radeon_encoder(radeon_crtc->encoder);
1853 u32 pll_in_use;
1854 int pll;
1855
1856 if (ASIC_IS_DCE8(rdev)) {
1857 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) {
1858 if (rdev->clock.dp_extclk)
1859 /* skip PPLL programming if using ext clock */
1860 return ATOM_PPLL_INVALID;
1861 else {
1862 /* use the same PPLL for all DP monitors */
1863 pll = radeon_get_shared_dp_ppll(crtc);
1864 if (pll != ATOM_PPLL_INVALID)
1865 return pll;
1866 }
1867 } else {
1868 /* use the same PPLL for all monitors with the same clock */
1869 pll = radeon_get_shared_nondp_ppll(crtc);
1870 if (pll != ATOM_PPLL_INVALID)
1871 return pll;
1872 }
1873 /* otherwise, pick one of the plls */
1874 if ((rdev->family == CHIP_KABINI) ||
1875 (rdev->family == CHIP_MULLINS)) {
1876 /* KB/ML has PPLL1 and PPLL2 */
1877 pll_in_use = radeon_get_pll_use_mask(crtc);
1878 if (!(pll_in_use & (1 << ATOM_PPLL2)))
1879 return ATOM_PPLL2;
1880 if (!(pll_in_use & (1 << ATOM_PPLL1)))
1881 return ATOM_PPLL1;
1882 DRM_ERROR("unable to allocate a PPLL\n");
1883 return ATOM_PPLL_INVALID;
1884 } else {
1885 /* CI/KV has PPLL0, PPLL1, and PPLL2 */
1886 pll_in_use = radeon_get_pll_use_mask(crtc);
1887 if (!(pll_in_use & (1 << ATOM_PPLL2)))
1888 return ATOM_PPLL2;
1889 if (!(pll_in_use & (1 << ATOM_PPLL1)))
1890 return ATOM_PPLL1;
1891 if (!(pll_in_use & (1 << ATOM_PPLL0)))
1892 return ATOM_PPLL0;
1893 DRM_ERROR("unable to allocate a PPLL\n");
1894 return ATOM_PPLL_INVALID;
1895 }
1896 } else if (ASIC_IS_DCE61(rdev)) {
1897 struct radeon_encoder_atom_dig *dig =
1898 radeon_encoder->enc_priv;
1899
1900 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY) &&
1901 (dig->linkb == false))
1902 /* UNIPHY A uses PPLL2 */
1903 return ATOM_PPLL2;
1904 else if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) {
1905 /* UNIPHY B/C/D/E/F */
1906 if (rdev->clock.dp_extclk)
1907 /* skip PPLL programming if using ext clock */
1908 return ATOM_PPLL_INVALID;
1909 else {
1910 /* use the same PPLL for all DP monitors */
1911 pll = radeon_get_shared_dp_ppll(crtc);
1912 if (pll != ATOM_PPLL_INVALID)
1913 return pll;
1914 }
1915 } else {
1916 /* use the same PPLL for all monitors with the same clock */
1917 pll = radeon_get_shared_nondp_ppll(crtc);
1918 if (pll != ATOM_PPLL_INVALID)
1919 return pll;
1920 }
1921 /* UNIPHY B/C/D/E/F */
1922 pll_in_use = radeon_get_pll_use_mask(crtc);
1923 if (!(pll_in_use & (1 << ATOM_PPLL0)))
1924 return ATOM_PPLL0;
1925 if (!(pll_in_use & (1 << ATOM_PPLL1)))
1926 return ATOM_PPLL1;
1927 DRM_ERROR("unable to allocate a PPLL\n");
1928 return ATOM_PPLL_INVALID;
1929 } else if (ASIC_IS_DCE41(rdev)) {
1930 /* Don't share PLLs on DCE4.1 chips */
1931 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) {
1932 if (rdev->clock.dp_extclk)
1933 /* skip PPLL programming if using ext clock */
1934 return ATOM_PPLL_INVALID;
1935 }
1936 pll_in_use = radeon_get_pll_use_mask(crtc);
1937 if (!(pll_in_use & (1 << ATOM_PPLL1)))
1938 return ATOM_PPLL1;
1939 if (!(pll_in_use & (1 << ATOM_PPLL2)))
1940 return ATOM_PPLL2;
1941 DRM_ERROR("unable to allocate a PPLL\n");
1942 return ATOM_PPLL_INVALID;
1943 } else if (ASIC_IS_DCE4(rdev)) {
1944 /* in DP mode, the DP ref clock can come from PPLL, DCPLL, or ext clock,
1945 * depending on the asic:
1946 * DCE4: PPLL or ext clock
1947 * DCE5: PPLL, DCPLL, or ext clock
1948 * DCE6: PPLL, PPLL0, or ext clock
1949 *
1950 * Setting ATOM_PPLL_INVALID will cause SetPixelClock to skip
1951 * PPLL/DCPLL programming and only program the DP DTO for the
1952 * crtc virtual pixel clock.
1953 */
1954 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) {
1955 if (rdev->clock.dp_extclk)
1956 /* skip PPLL programming if using ext clock */
1957 return ATOM_PPLL_INVALID;
1958 else if (ASIC_IS_DCE6(rdev))
1959 /* use PPLL0 for all DP */
1960 return ATOM_PPLL0;
1961 else if (ASIC_IS_DCE5(rdev))
1962 /* use DCPLL for all DP */
1963 return ATOM_DCPLL;
1964 else {
1965 /* use the same PPLL for all DP monitors */
1966 pll = radeon_get_shared_dp_ppll(crtc);
1967 if (pll != ATOM_PPLL_INVALID)
1968 return pll;
1969 }
1970 } else {
1971 /* use the same PPLL for all monitors with the same clock */
1972 pll = radeon_get_shared_nondp_ppll(crtc);
1973 if (pll != ATOM_PPLL_INVALID)
1974 return pll;
1975 }
1976 /* all other cases */
1977 pll_in_use = radeon_get_pll_use_mask(crtc);
1978 if (!(pll_in_use & (1 << ATOM_PPLL1)))
1979 return ATOM_PPLL1;
1980 if (!(pll_in_use & (1 << ATOM_PPLL2)))
1981 return ATOM_PPLL2;
1982 DRM_ERROR("unable to allocate a PPLL\n");
1983 return ATOM_PPLL_INVALID;
1984 } else {
1985 /* on pre-R5xx asics, the crtc to pll mapping is hardcoded */
1986 /* some atombios (observed in some DCE2/DCE3) code have a bug,
1987 * the matching btw pll and crtc is done through
1988 * PCLK_CRTC[1|2]_CNTL (0x480/0x484) but atombios code use the
1989 * pll (1 or 2) to select which register to write. ie if using
1990 * pll1 it will use PCLK_CRTC1_CNTL (0x480) and if using pll2
1991 * it will use PCLK_CRTC2_CNTL (0x484), it then use crtc id to
1992 * choose which value to write. Which is reverse order from
1993 * register logic. So only case that works is when pllid is
1994 * same as crtcid or when both pll and crtc are enabled and
1995 * both use same clock.
1996 *
1997 * So just return crtc id as if crtc and pll were hard linked
1998 * together even if they aren't
1999 */
2000 return radeon_crtc->crtc_id;
2001 }
2002 }
2003
radeon_atom_disp_eng_pll_init(struct radeon_device * rdev)2004 void radeon_atom_disp_eng_pll_init(struct radeon_device *rdev)
2005 {
2006 /* always set DCPLL */
2007 if (ASIC_IS_DCE6(rdev))
2008 atombios_crtc_set_disp_eng_pll(rdev, rdev->clock.default_dispclk);
2009 else if (ASIC_IS_DCE4(rdev)) {
2010 struct radeon_atom_ss ss;
2011 bool ss_enabled = radeon_atombios_get_asic_ss_info(rdev, &ss,
2012 ASIC_INTERNAL_SS_ON_DCPLL,
2013 rdev->clock.default_dispclk);
2014 if (ss_enabled)
2015 atombios_crtc_program_ss(rdev, ATOM_DISABLE, ATOM_DCPLL, -1, &ss);
2016 /* XXX: DCE5, make sure voltage, dispclk is high enough */
2017 atombios_crtc_set_disp_eng_pll(rdev, rdev->clock.default_dispclk);
2018 if (ss_enabled)
2019 atombios_crtc_program_ss(rdev, ATOM_ENABLE, ATOM_DCPLL, -1, &ss);
2020 }
2021
2022 }
2023
atombios_crtc_mode_set(struct drm_crtc * crtc,struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode,int x,int y,struct drm_framebuffer * old_fb)2024 int atombios_crtc_mode_set(struct drm_crtc *crtc,
2025 struct drm_display_mode *mode,
2026 struct drm_display_mode *adjusted_mode,
2027 int x, int y, struct drm_framebuffer *old_fb)
2028 {
2029 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
2030 struct drm_device *dev = crtc->dev;
2031 struct radeon_device *rdev = dev->dev_private;
2032 struct radeon_encoder *radeon_encoder =
2033 to_radeon_encoder(radeon_crtc->encoder);
2034 bool is_tvcv = false;
2035
2036 if (radeon_encoder->active_device &
2037 (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
2038 is_tvcv = true;
2039
2040 if (!radeon_crtc->adjusted_clock)
2041 return -EINVAL;
2042
2043 atombios_crtc_set_pll(crtc, adjusted_mode);
2044
2045 if (ASIC_IS_DCE4(rdev))
2046 atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
2047 else if (ASIC_IS_AVIVO(rdev)) {
2048 if (is_tvcv)
2049 atombios_crtc_set_timing(crtc, adjusted_mode);
2050 else
2051 atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
2052 } else {
2053 atombios_crtc_set_timing(crtc, adjusted_mode);
2054 if (radeon_crtc->crtc_id == 0)
2055 atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
2056 radeon_legacy_atom_fixup(crtc);
2057 }
2058 atombios_crtc_set_base(crtc, x, y, old_fb);
2059 atombios_overscan_setup(crtc, mode, adjusted_mode);
2060 atombios_scaler_setup(crtc);
2061 /* update the hw version fpr dpm */
2062 radeon_crtc->hw_mode = *adjusted_mode;
2063
2064 return 0;
2065 }
2066
atombios_crtc_mode_fixup(struct drm_crtc * crtc,const struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode)2067 static bool atombios_crtc_mode_fixup(struct drm_crtc *crtc,
2068 const struct drm_display_mode *mode,
2069 struct drm_display_mode *adjusted_mode)
2070 {
2071 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
2072 struct drm_device *dev = crtc->dev;
2073 struct drm_encoder *encoder;
2074
2075 /* assign the encoder to the radeon crtc to avoid repeated lookups later */
2076 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2077 if (encoder->crtc == crtc) {
2078 radeon_crtc->encoder = encoder;
2079 radeon_crtc->connector = radeon_get_connector_for_encoder(encoder);
2080 break;
2081 }
2082 }
2083 if ((radeon_crtc->encoder == NULL) || (radeon_crtc->connector == NULL)) {
2084 radeon_crtc->encoder = NULL;
2085 radeon_crtc->connector = NULL;
2086 return false;
2087 }
2088 if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
2089 return false;
2090 if (!atombios_crtc_prepare_pll(crtc, adjusted_mode))
2091 return false;
2092 /* pick pll */
2093 radeon_crtc->pll_id = radeon_atom_pick_pll(crtc);
2094 /* if we can't get a PPLL for a non-DP encoder, fail */
2095 if ((radeon_crtc->pll_id == ATOM_PPLL_INVALID) &&
2096 !ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder)))
2097 return false;
2098
2099 return true;
2100 }
2101
atombios_crtc_prepare(struct drm_crtc * crtc)2102 static void atombios_crtc_prepare(struct drm_crtc *crtc)
2103 {
2104 struct drm_device *dev = crtc->dev;
2105 struct radeon_device *rdev = dev->dev_private;
2106
2107 /* disable crtc pair power gating before programming */
2108 if (ASIC_IS_DCE6(rdev))
2109 atombios_powergate_crtc(crtc, ATOM_DISABLE);
2110
2111 atombios_lock_crtc(crtc, ATOM_ENABLE);
2112 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2113 }
2114
atombios_crtc_commit(struct drm_crtc * crtc)2115 static void atombios_crtc_commit(struct drm_crtc *crtc)
2116 {
2117 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
2118 atombios_lock_crtc(crtc, ATOM_DISABLE);
2119 }
2120
atombios_crtc_disable(struct drm_crtc * crtc)2121 static void atombios_crtc_disable(struct drm_crtc *crtc)
2122 {
2123 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
2124 struct drm_device *dev = crtc->dev;
2125 struct radeon_device *rdev = dev->dev_private;
2126 struct radeon_atom_ss ss;
2127 int i;
2128
2129 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2130 if (crtc->primary->fb) {
2131 int r;
2132 struct radeon_framebuffer *radeon_fb;
2133 struct radeon_bo *rbo;
2134
2135 radeon_fb = to_radeon_framebuffer(crtc->primary->fb);
2136 rbo = gem_to_radeon_bo(radeon_fb->obj);
2137 r = radeon_bo_reserve(rbo, false);
2138 if (unlikely(r))
2139 DRM_ERROR("failed to reserve rbo before unpin\n");
2140 else {
2141 radeon_bo_unpin(rbo);
2142 radeon_bo_unreserve(rbo);
2143 }
2144 }
2145 /* disable the GRPH */
2146 if (ASIC_IS_DCE4(rdev))
2147 WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 0);
2148 else if (ASIC_IS_AVIVO(rdev))
2149 WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 0);
2150
2151 if (ASIC_IS_DCE6(rdev))
2152 atombios_powergate_crtc(crtc, ATOM_ENABLE);
2153
2154 for (i = 0; i < rdev->num_crtc; i++) {
2155 if (rdev->mode_info.crtcs[i] &&
2156 rdev->mode_info.crtcs[i]->enabled &&
2157 i != radeon_crtc->crtc_id &&
2158 radeon_crtc->pll_id == rdev->mode_info.crtcs[i]->pll_id) {
2159 /* one other crtc is using this pll don't turn
2160 * off the pll
2161 */
2162 goto done;
2163 }
2164 }
2165
2166 switch (radeon_crtc->pll_id) {
2167 case ATOM_PPLL1:
2168 case ATOM_PPLL2:
2169 /* disable the ppll */
2170 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
2171 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
2172 break;
2173 case ATOM_PPLL0:
2174 /* disable the ppll */
2175 if ((rdev->family == CHIP_ARUBA) ||
2176 (rdev->family == CHIP_KAVERI) ||
2177 (rdev->family == CHIP_BONAIRE) ||
2178 (rdev->family == CHIP_HAWAII))
2179 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
2180 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
2181 break;
2182 default:
2183 break;
2184 }
2185 done:
2186 radeon_crtc->pll_id = ATOM_PPLL_INVALID;
2187 radeon_crtc->adjusted_clock = 0;
2188 radeon_crtc->encoder = NULL;
2189 radeon_crtc->connector = NULL;
2190 }
2191
2192 static const struct drm_crtc_helper_funcs atombios_helper_funcs = {
2193 .dpms = atombios_crtc_dpms,
2194 .mode_fixup = atombios_crtc_mode_fixup,
2195 .mode_set = atombios_crtc_mode_set,
2196 .mode_set_base = atombios_crtc_set_base,
2197 .mode_set_base_atomic = atombios_crtc_set_base_atomic,
2198 .prepare = atombios_crtc_prepare,
2199 .commit = atombios_crtc_commit,
2200 .load_lut = radeon_crtc_load_lut,
2201 .disable = atombios_crtc_disable,
2202 };
2203
radeon_atombios_init_crtc(struct drm_device * dev,struct radeon_crtc * radeon_crtc)2204 void radeon_atombios_init_crtc(struct drm_device *dev,
2205 struct radeon_crtc *radeon_crtc)
2206 {
2207 struct radeon_device *rdev = dev->dev_private;
2208
2209 if (ASIC_IS_DCE4(rdev)) {
2210 switch (radeon_crtc->crtc_id) {
2211 case 0:
2212 default:
2213 radeon_crtc->crtc_offset = EVERGREEN_CRTC0_REGISTER_OFFSET;
2214 break;
2215 case 1:
2216 radeon_crtc->crtc_offset = EVERGREEN_CRTC1_REGISTER_OFFSET;
2217 break;
2218 case 2:
2219 radeon_crtc->crtc_offset = EVERGREEN_CRTC2_REGISTER_OFFSET;
2220 break;
2221 case 3:
2222 radeon_crtc->crtc_offset = EVERGREEN_CRTC3_REGISTER_OFFSET;
2223 break;
2224 case 4:
2225 radeon_crtc->crtc_offset = EVERGREEN_CRTC4_REGISTER_OFFSET;
2226 break;
2227 case 5:
2228 radeon_crtc->crtc_offset = EVERGREEN_CRTC5_REGISTER_OFFSET;
2229 break;
2230 }
2231 } else {
2232 if (radeon_crtc->crtc_id == 1)
2233 radeon_crtc->crtc_offset =
2234 AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL;
2235 else
2236 radeon_crtc->crtc_offset = 0;
2237 }
2238 radeon_crtc->pll_id = ATOM_PPLL_INVALID;
2239 radeon_crtc->adjusted_clock = 0;
2240 radeon_crtc->encoder = NULL;
2241 radeon_crtc->connector = NULL;
2242 drm_crtc_helper_add(&radeon_crtc->base, &atombios_helper_funcs);
2243 }
2244