1 /*
2 * TI DAVINCI I2C adapter driver.
3 *
4 * Copyright (C) 2006 Texas Instruments.
5 * Copyright (C) 2007 MontaVista Software Inc.
6 *
7 * Updated by Vinod & Sudhakar Feb 2005
8 *
9 * ----------------------------------------------------------------------------
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 * ----------------------------------------------------------------------------
21 *
22 */
23 #include <linux/kernel.h>
24 #include <linux/module.h>
25 #include <linux/delay.h>
26 #include <linux/i2c.h>
27 #include <linux/clk.h>
28 #include <linux/errno.h>
29 #include <linux/sched.h>
30 #include <linux/err.h>
31 #include <linux/interrupt.h>
32 #include <linux/platform_device.h>
33 #include <linux/io.h>
34 #include <linux/slab.h>
35 #include <linux/cpufreq.h>
36 #include <linux/gpio.h>
37 #include <linux/of_device.h>
38 #include <linux/platform_data/i2c-davinci.h>
39
40 /* ----- global defines ----------------------------------------------- */
41
42 #define DAVINCI_I2C_TIMEOUT (1*HZ)
43 #define DAVINCI_I2C_MAX_TRIES 2
44 #define I2C_DAVINCI_INTR_ALL (DAVINCI_I2C_IMR_AAS | \
45 DAVINCI_I2C_IMR_SCD | \
46 DAVINCI_I2C_IMR_ARDY | \
47 DAVINCI_I2C_IMR_NACK | \
48 DAVINCI_I2C_IMR_AL)
49
50 #define DAVINCI_I2C_OAR_REG 0x00
51 #define DAVINCI_I2C_IMR_REG 0x04
52 #define DAVINCI_I2C_STR_REG 0x08
53 #define DAVINCI_I2C_CLKL_REG 0x0c
54 #define DAVINCI_I2C_CLKH_REG 0x10
55 #define DAVINCI_I2C_CNT_REG 0x14
56 #define DAVINCI_I2C_DRR_REG 0x18
57 #define DAVINCI_I2C_SAR_REG 0x1c
58 #define DAVINCI_I2C_DXR_REG 0x20
59 #define DAVINCI_I2C_MDR_REG 0x24
60 #define DAVINCI_I2C_IVR_REG 0x28
61 #define DAVINCI_I2C_EMDR_REG 0x2c
62 #define DAVINCI_I2C_PSC_REG 0x30
63
64 #define DAVINCI_I2C_IVR_AAS 0x07
65 #define DAVINCI_I2C_IVR_SCD 0x06
66 #define DAVINCI_I2C_IVR_XRDY 0x05
67 #define DAVINCI_I2C_IVR_RDR 0x04
68 #define DAVINCI_I2C_IVR_ARDY 0x03
69 #define DAVINCI_I2C_IVR_NACK 0x02
70 #define DAVINCI_I2C_IVR_AL 0x01
71
72 #define DAVINCI_I2C_STR_BB BIT(12)
73 #define DAVINCI_I2C_STR_RSFULL BIT(11)
74 #define DAVINCI_I2C_STR_SCD BIT(5)
75 #define DAVINCI_I2C_STR_ARDY BIT(2)
76 #define DAVINCI_I2C_STR_NACK BIT(1)
77 #define DAVINCI_I2C_STR_AL BIT(0)
78
79 #define DAVINCI_I2C_MDR_NACK BIT(15)
80 #define DAVINCI_I2C_MDR_STT BIT(13)
81 #define DAVINCI_I2C_MDR_STP BIT(11)
82 #define DAVINCI_I2C_MDR_MST BIT(10)
83 #define DAVINCI_I2C_MDR_TRX BIT(9)
84 #define DAVINCI_I2C_MDR_XA BIT(8)
85 #define DAVINCI_I2C_MDR_RM BIT(7)
86 #define DAVINCI_I2C_MDR_IRS BIT(5)
87
88 #define DAVINCI_I2C_IMR_AAS BIT(6)
89 #define DAVINCI_I2C_IMR_SCD BIT(5)
90 #define DAVINCI_I2C_IMR_XRDY BIT(4)
91 #define DAVINCI_I2C_IMR_RRDY BIT(3)
92 #define DAVINCI_I2C_IMR_ARDY BIT(2)
93 #define DAVINCI_I2C_IMR_NACK BIT(1)
94 #define DAVINCI_I2C_IMR_AL BIT(0)
95
96 struct davinci_i2c_dev {
97 struct device *dev;
98 void __iomem *base;
99 struct completion cmd_complete;
100 struct clk *clk;
101 int cmd_err;
102 u8 *buf;
103 size_t buf_len;
104 int irq;
105 int stop;
106 u8 terminate;
107 struct i2c_adapter adapter;
108 #ifdef CONFIG_CPU_FREQ
109 struct completion xfr_complete;
110 struct notifier_block freq_transition;
111 #endif
112 struct davinci_i2c_platform_data *pdata;
113 };
114
115 /* default platform data to use if not supplied in the platform_device */
116 static struct davinci_i2c_platform_data davinci_i2c_platform_data_default = {
117 .bus_freq = 100,
118 .bus_delay = 0,
119 };
120
davinci_i2c_write_reg(struct davinci_i2c_dev * i2c_dev,int reg,u16 val)121 static inline void davinci_i2c_write_reg(struct davinci_i2c_dev *i2c_dev,
122 int reg, u16 val)
123 {
124 writew_relaxed(val, i2c_dev->base + reg);
125 }
126
davinci_i2c_read_reg(struct davinci_i2c_dev * i2c_dev,int reg)127 static inline u16 davinci_i2c_read_reg(struct davinci_i2c_dev *i2c_dev, int reg)
128 {
129 return readw_relaxed(i2c_dev->base + reg);
130 }
131
132 /* Generate a pulse on the i2c clock pin. */
davinci_i2c_clock_pulse(unsigned int scl_pin)133 static void davinci_i2c_clock_pulse(unsigned int scl_pin)
134 {
135 u16 i;
136
137 if (scl_pin) {
138 /* Send high and low on the SCL line */
139 for (i = 0; i < 9; i++) {
140 gpio_set_value(scl_pin, 0);
141 udelay(20);
142 gpio_set_value(scl_pin, 1);
143 udelay(20);
144 }
145 }
146 }
147
148 /* This routine does i2c bus recovery as specified in the
149 * i2c protocol Rev. 03 section 3.16 titled "Bus clear"
150 */
davinci_i2c_recover_bus(struct davinci_i2c_dev * dev)151 static void davinci_i2c_recover_bus(struct davinci_i2c_dev *dev)
152 {
153 u32 flag = 0;
154 struct davinci_i2c_platform_data *pdata = dev->pdata;
155
156 dev_err(dev->dev, "initiating i2c bus recovery\n");
157 /* Send NACK to the slave */
158 flag = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG);
159 flag |= DAVINCI_I2C_MDR_NACK;
160 /* write the data into mode register */
161 davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, flag);
162 davinci_i2c_clock_pulse(pdata->scl_pin);
163 /* Send STOP */
164 flag = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG);
165 flag |= DAVINCI_I2C_MDR_STP;
166 davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, flag);
167 }
168
davinci_i2c_reset_ctrl(struct davinci_i2c_dev * i2c_dev,int val)169 static inline void davinci_i2c_reset_ctrl(struct davinci_i2c_dev *i2c_dev,
170 int val)
171 {
172 u16 w;
173
174 w = davinci_i2c_read_reg(i2c_dev, DAVINCI_I2C_MDR_REG);
175 if (!val) /* put I2C into reset */
176 w &= ~DAVINCI_I2C_MDR_IRS;
177 else /* take I2C out of reset */
178 w |= DAVINCI_I2C_MDR_IRS;
179
180 davinci_i2c_write_reg(i2c_dev, DAVINCI_I2C_MDR_REG, w);
181 }
182
i2c_davinci_calc_clk_dividers(struct davinci_i2c_dev * dev)183 static void i2c_davinci_calc_clk_dividers(struct davinci_i2c_dev *dev)
184 {
185 struct davinci_i2c_platform_data *pdata = dev->pdata;
186 u16 psc;
187 u32 clk;
188 u32 d;
189 u32 clkh;
190 u32 clkl;
191 u32 input_clock = clk_get_rate(dev->clk);
192
193 /* NOTE: I2C Clock divider programming info
194 * As per I2C specs the following formulas provide prescaler
195 * and low/high divider values
196 * input clk --> PSC Div -----------> ICCL/H Div --> output clock
197 * module clk
198 *
199 * output clk = module clk / (PSC + 1) [ (ICCL + d) + (ICCH + d) ]
200 *
201 * Thus,
202 * (ICCL + ICCH) = clk = (input clk / ((psc +1) * output clk)) - 2d;
203 *
204 * where if PSC == 0, d = 7,
205 * if PSC == 1, d = 6
206 * if PSC > 1 , d = 5
207 */
208
209 /* get minimum of 7 MHz clock, but max of 12 MHz */
210 psc = (input_clock / 7000000) - 1;
211 if ((input_clock / (psc + 1)) > 12000000)
212 psc++; /* better to run under spec than over */
213 d = (psc >= 2) ? 5 : 7 - psc;
214
215 clk = ((input_clock / (psc + 1)) / (pdata->bus_freq * 1000)) - (d << 1);
216 clkh = clk >> 1;
217 clkl = clk - clkh;
218
219 davinci_i2c_write_reg(dev, DAVINCI_I2C_PSC_REG, psc);
220 davinci_i2c_write_reg(dev, DAVINCI_I2C_CLKH_REG, clkh);
221 davinci_i2c_write_reg(dev, DAVINCI_I2C_CLKL_REG, clkl);
222
223 dev_dbg(dev->dev, "input_clock = %d, CLK = %d\n", input_clock, clk);
224 }
225
226 /*
227 * This function configures I2C and brings I2C out of reset.
228 * This function is called during I2C init function. This function
229 * also gets called if I2C encounters any errors.
230 */
i2c_davinci_init(struct davinci_i2c_dev * dev)231 static int i2c_davinci_init(struct davinci_i2c_dev *dev)
232 {
233 struct davinci_i2c_platform_data *pdata = dev->pdata;
234
235 /* put I2C into reset */
236 davinci_i2c_reset_ctrl(dev, 0);
237
238 /* compute clock dividers */
239 i2c_davinci_calc_clk_dividers(dev);
240
241 /* Respond at reserved "SMBus Host" slave address" (and zero);
242 * we seem to have no option to not respond...
243 */
244 davinci_i2c_write_reg(dev, DAVINCI_I2C_OAR_REG, 0x08);
245
246 dev_dbg(dev->dev, "PSC = %d\n",
247 davinci_i2c_read_reg(dev, DAVINCI_I2C_PSC_REG));
248 dev_dbg(dev->dev, "CLKL = %d\n",
249 davinci_i2c_read_reg(dev, DAVINCI_I2C_CLKL_REG));
250 dev_dbg(dev->dev, "CLKH = %d\n",
251 davinci_i2c_read_reg(dev, DAVINCI_I2C_CLKH_REG));
252 dev_dbg(dev->dev, "bus_freq = %dkHz, bus_delay = %d\n",
253 pdata->bus_freq, pdata->bus_delay);
254
255
256 /* Take the I2C module out of reset: */
257 davinci_i2c_reset_ctrl(dev, 1);
258
259 /* Enable interrupts */
260 davinci_i2c_write_reg(dev, DAVINCI_I2C_IMR_REG, I2C_DAVINCI_INTR_ALL);
261
262 return 0;
263 }
264
265 /*
266 * Waiting for bus not busy
267 */
i2c_davinci_wait_bus_not_busy(struct davinci_i2c_dev * dev,char allow_sleep)268 static int i2c_davinci_wait_bus_not_busy(struct davinci_i2c_dev *dev,
269 char allow_sleep)
270 {
271 unsigned long timeout;
272 static u16 to_cnt;
273
274 timeout = jiffies + dev->adapter.timeout;
275 while (davinci_i2c_read_reg(dev, DAVINCI_I2C_STR_REG)
276 & DAVINCI_I2C_STR_BB) {
277 if (to_cnt <= DAVINCI_I2C_MAX_TRIES) {
278 if (time_after(jiffies, timeout)) {
279 dev_warn(dev->dev,
280 "timeout waiting for bus ready\n");
281 to_cnt++;
282 return -ETIMEDOUT;
283 } else {
284 to_cnt = 0;
285 davinci_i2c_recover_bus(dev);
286 i2c_davinci_init(dev);
287 }
288 }
289 if (allow_sleep)
290 schedule_timeout(1);
291 }
292
293 return 0;
294 }
295
296 /*
297 * Low level master read/write transaction. This function is called
298 * from i2c_davinci_xfer.
299 */
300 static int
i2c_davinci_xfer_msg(struct i2c_adapter * adap,struct i2c_msg * msg,int stop)301 i2c_davinci_xfer_msg(struct i2c_adapter *adap, struct i2c_msg *msg, int stop)
302 {
303 struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
304 struct davinci_i2c_platform_data *pdata = dev->pdata;
305 u32 flag;
306 u16 w;
307 int r;
308
309 /* Introduce a delay, required for some boards (e.g Davinci EVM) */
310 if (pdata->bus_delay)
311 udelay(pdata->bus_delay);
312
313 /* set the slave address */
314 davinci_i2c_write_reg(dev, DAVINCI_I2C_SAR_REG, msg->addr);
315
316 dev->buf = msg->buf;
317 dev->buf_len = msg->len;
318 dev->stop = stop;
319
320 davinci_i2c_write_reg(dev, DAVINCI_I2C_CNT_REG, dev->buf_len);
321
322 reinit_completion(&dev->cmd_complete);
323 dev->cmd_err = 0;
324
325 /* Take I2C out of reset and configure it as master */
326 flag = DAVINCI_I2C_MDR_IRS | DAVINCI_I2C_MDR_MST;
327
328 /* if the slave address is ten bit address, enable XA bit */
329 if (msg->flags & I2C_M_TEN)
330 flag |= DAVINCI_I2C_MDR_XA;
331 if (!(msg->flags & I2C_M_RD))
332 flag |= DAVINCI_I2C_MDR_TRX;
333 if (msg->len == 0)
334 flag |= DAVINCI_I2C_MDR_RM;
335
336 /* Enable receive or transmit interrupts */
337 w = davinci_i2c_read_reg(dev, DAVINCI_I2C_IMR_REG);
338 if (msg->flags & I2C_M_RD)
339 w |= DAVINCI_I2C_IMR_RRDY;
340 else
341 w |= DAVINCI_I2C_IMR_XRDY;
342 davinci_i2c_write_reg(dev, DAVINCI_I2C_IMR_REG, w);
343
344 dev->terminate = 0;
345
346 /*
347 * Write mode register first as needed for correct behaviour
348 * on OMAP-L138, but don't set STT yet to avoid a race with XRDY
349 * occurring before we have loaded DXR
350 */
351 davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, flag);
352
353 /*
354 * First byte should be set here, not after interrupt,
355 * because transmit-data-ready interrupt can come before
356 * NACK-interrupt during sending of previous message and
357 * ICDXR may have wrong data
358 * It also saves us one interrupt, slightly faster
359 */
360 if ((!(msg->flags & I2C_M_RD)) && dev->buf_len) {
361 davinci_i2c_write_reg(dev, DAVINCI_I2C_DXR_REG, *dev->buf++);
362 dev->buf_len--;
363 }
364
365 /* Set STT to begin transmit now DXR is loaded */
366 flag |= DAVINCI_I2C_MDR_STT;
367 if (stop && msg->len != 0)
368 flag |= DAVINCI_I2C_MDR_STP;
369 davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, flag);
370
371 r = wait_for_completion_interruptible_timeout(&dev->cmd_complete,
372 dev->adapter.timeout);
373 if (r == 0) {
374 dev_err(dev->dev, "controller timed out\n");
375 davinci_i2c_recover_bus(dev);
376 i2c_davinci_init(dev);
377 dev->buf_len = 0;
378 return -ETIMEDOUT;
379 }
380 if (dev->buf_len) {
381 /* This should be 0 if all bytes were transferred
382 * or dev->cmd_err denotes an error.
383 * A signal may have aborted the transfer.
384 */
385 if (r >= 0) {
386 dev_err(dev->dev, "abnormal termination buf_len=%i\n",
387 dev->buf_len);
388 r = -EREMOTEIO;
389 }
390 dev->terminate = 1;
391 wmb();
392 dev->buf_len = 0;
393 }
394 if (r < 0)
395 return r;
396
397 /* no error */
398 if (likely(!dev->cmd_err))
399 return msg->len;
400
401 /* We have an error */
402 if (dev->cmd_err & DAVINCI_I2C_STR_AL) {
403 i2c_davinci_init(dev);
404 return -EIO;
405 }
406
407 if (dev->cmd_err & DAVINCI_I2C_STR_NACK) {
408 if (msg->flags & I2C_M_IGNORE_NAK)
409 return msg->len;
410 w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG);
411 w |= DAVINCI_I2C_MDR_STP;
412 davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w);
413 return -EREMOTEIO;
414 }
415 return -EIO;
416 }
417
418 /*
419 * Prepare controller for a transaction and call i2c_davinci_xfer_msg
420 */
421 static int
i2c_davinci_xfer(struct i2c_adapter * adap,struct i2c_msg msgs[],int num)422 i2c_davinci_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
423 {
424 struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
425 int i;
426 int ret;
427
428 dev_dbg(dev->dev, "%s: msgs: %d\n", __func__, num);
429
430 ret = i2c_davinci_wait_bus_not_busy(dev, 1);
431 if (ret < 0) {
432 dev_warn(dev->dev, "timeout waiting for bus ready\n");
433 return ret;
434 }
435
436 for (i = 0; i < num; i++) {
437 ret = i2c_davinci_xfer_msg(adap, &msgs[i], (i == (num - 1)));
438 dev_dbg(dev->dev, "%s [%d/%d] ret: %d\n", __func__, i + 1, num,
439 ret);
440 if (ret < 0)
441 return ret;
442 }
443
444 #ifdef CONFIG_CPU_FREQ
445 complete(&dev->xfr_complete);
446 #endif
447
448 return num;
449 }
450
i2c_davinci_func(struct i2c_adapter * adap)451 static u32 i2c_davinci_func(struct i2c_adapter *adap)
452 {
453 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
454 }
455
terminate_read(struct davinci_i2c_dev * dev)456 static void terminate_read(struct davinci_i2c_dev *dev)
457 {
458 u16 w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG);
459 w |= DAVINCI_I2C_MDR_NACK;
460 davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w);
461
462 /* Throw away data */
463 davinci_i2c_read_reg(dev, DAVINCI_I2C_DRR_REG);
464 if (!dev->terminate)
465 dev_err(dev->dev, "RDR IRQ while no data requested\n");
466 }
terminate_write(struct davinci_i2c_dev * dev)467 static void terminate_write(struct davinci_i2c_dev *dev)
468 {
469 u16 w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG);
470 w |= DAVINCI_I2C_MDR_RM | DAVINCI_I2C_MDR_STP;
471 davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w);
472
473 if (!dev->terminate)
474 dev_dbg(dev->dev, "TDR IRQ while no data to send\n");
475 }
476
477 /*
478 * Interrupt service routine. This gets called whenever an I2C interrupt
479 * occurs.
480 */
i2c_davinci_isr(int this_irq,void * dev_id)481 static irqreturn_t i2c_davinci_isr(int this_irq, void *dev_id)
482 {
483 struct davinci_i2c_dev *dev = dev_id;
484 u32 stat;
485 int count = 0;
486 u16 w;
487
488 while ((stat = davinci_i2c_read_reg(dev, DAVINCI_I2C_IVR_REG))) {
489 dev_dbg(dev->dev, "%s: stat=0x%x\n", __func__, stat);
490 if (count++ == 100) {
491 dev_warn(dev->dev, "Too much work in one IRQ\n");
492 break;
493 }
494
495 switch (stat) {
496 case DAVINCI_I2C_IVR_AL:
497 /* Arbitration lost, must retry */
498 dev->cmd_err |= DAVINCI_I2C_STR_AL;
499 dev->buf_len = 0;
500 complete(&dev->cmd_complete);
501 break;
502
503 case DAVINCI_I2C_IVR_NACK:
504 dev->cmd_err |= DAVINCI_I2C_STR_NACK;
505 dev->buf_len = 0;
506 complete(&dev->cmd_complete);
507 break;
508
509 case DAVINCI_I2C_IVR_ARDY:
510 davinci_i2c_write_reg(dev,
511 DAVINCI_I2C_STR_REG, DAVINCI_I2C_STR_ARDY);
512 if (((dev->buf_len == 0) && (dev->stop != 0)) ||
513 (dev->cmd_err & DAVINCI_I2C_STR_NACK)) {
514 w = davinci_i2c_read_reg(dev,
515 DAVINCI_I2C_MDR_REG);
516 w |= DAVINCI_I2C_MDR_STP;
517 davinci_i2c_write_reg(dev,
518 DAVINCI_I2C_MDR_REG, w);
519 }
520 complete(&dev->cmd_complete);
521 break;
522
523 case DAVINCI_I2C_IVR_RDR:
524 if (dev->buf_len) {
525 *dev->buf++ =
526 davinci_i2c_read_reg(dev,
527 DAVINCI_I2C_DRR_REG);
528 dev->buf_len--;
529 if (dev->buf_len)
530 continue;
531
532 davinci_i2c_write_reg(dev,
533 DAVINCI_I2C_STR_REG,
534 DAVINCI_I2C_IMR_RRDY);
535 } else {
536 /* signal can terminate transfer */
537 terminate_read(dev);
538 }
539 break;
540
541 case DAVINCI_I2C_IVR_XRDY:
542 if (dev->buf_len) {
543 davinci_i2c_write_reg(dev, DAVINCI_I2C_DXR_REG,
544 *dev->buf++);
545 dev->buf_len--;
546 if (dev->buf_len)
547 continue;
548
549 w = davinci_i2c_read_reg(dev,
550 DAVINCI_I2C_IMR_REG);
551 w &= ~DAVINCI_I2C_IMR_XRDY;
552 davinci_i2c_write_reg(dev,
553 DAVINCI_I2C_IMR_REG,
554 w);
555 } else {
556 /* signal can terminate transfer */
557 terminate_write(dev);
558 }
559 break;
560
561 case DAVINCI_I2C_IVR_SCD:
562 davinci_i2c_write_reg(dev,
563 DAVINCI_I2C_STR_REG, DAVINCI_I2C_STR_SCD);
564 complete(&dev->cmd_complete);
565 break;
566
567 case DAVINCI_I2C_IVR_AAS:
568 dev_dbg(dev->dev, "Address as slave interrupt\n");
569 break;
570
571 default:
572 dev_warn(dev->dev, "Unrecognized irq stat %d\n", stat);
573 break;
574 }
575 }
576
577 return count ? IRQ_HANDLED : IRQ_NONE;
578 }
579
580 #ifdef CONFIG_CPU_FREQ
i2c_davinci_cpufreq_transition(struct notifier_block * nb,unsigned long val,void * data)581 static int i2c_davinci_cpufreq_transition(struct notifier_block *nb,
582 unsigned long val, void *data)
583 {
584 struct davinci_i2c_dev *dev;
585
586 dev = container_of(nb, struct davinci_i2c_dev, freq_transition);
587 if (val == CPUFREQ_PRECHANGE) {
588 wait_for_completion(&dev->xfr_complete);
589 davinci_i2c_reset_ctrl(dev, 0);
590 } else if (val == CPUFREQ_POSTCHANGE) {
591 i2c_davinci_calc_clk_dividers(dev);
592 davinci_i2c_reset_ctrl(dev, 1);
593 }
594
595 return 0;
596 }
597
i2c_davinci_cpufreq_register(struct davinci_i2c_dev * dev)598 static inline int i2c_davinci_cpufreq_register(struct davinci_i2c_dev *dev)
599 {
600 dev->freq_transition.notifier_call = i2c_davinci_cpufreq_transition;
601
602 return cpufreq_register_notifier(&dev->freq_transition,
603 CPUFREQ_TRANSITION_NOTIFIER);
604 }
605
i2c_davinci_cpufreq_deregister(struct davinci_i2c_dev * dev)606 static inline void i2c_davinci_cpufreq_deregister(struct davinci_i2c_dev *dev)
607 {
608 cpufreq_unregister_notifier(&dev->freq_transition,
609 CPUFREQ_TRANSITION_NOTIFIER);
610 }
611 #else
i2c_davinci_cpufreq_register(struct davinci_i2c_dev * dev)612 static inline int i2c_davinci_cpufreq_register(struct davinci_i2c_dev *dev)
613 {
614 return 0;
615 }
616
i2c_davinci_cpufreq_deregister(struct davinci_i2c_dev * dev)617 static inline void i2c_davinci_cpufreq_deregister(struct davinci_i2c_dev *dev)
618 {
619 }
620 #endif
621
622 static struct i2c_algorithm i2c_davinci_algo = {
623 .master_xfer = i2c_davinci_xfer,
624 .functionality = i2c_davinci_func,
625 };
626
627 static const struct of_device_id davinci_i2c_of_match[] = {
628 {.compatible = "ti,davinci-i2c", },
629 {},
630 };
631 MODULE_DEVICE_TABLE(of, davinci_i2c_of_match);
632
davinci_i2c_probe(struct platform_device * pdev)633 static int davinci_i2c_probe(struct platform_device *pdev)
634 {
635 struct davinci_i2c_dev *dev;
636 struct i2c_adapter *adap;
637 struct resource *mem, *irq;
638 int r;
639
640 irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
641 if (!irq) {
642 dev_err(&pdev->dev, "no irq resource?\n");
643 return -ENODEV;
644 }
645
646 dev = devm_kzalloc(&pdev->dev, sizeof(struct davinci_i2c_dev),
647 GFP_KERNEL);
648 if (!dev) {
649 dev_err(&pdev->dev, "Memory allocation failed\n");
650 return -ENOMEM;
651 }
652
653 init_completion(&dev->cmd_complete);
654 #ifdef CONFIG_CPU_FREQ
655 init_completion(&dev->xfr_complete);
656 #endif
657 dev->dev = &pdev->dev;
658 dev->irq = irq->start;
659 dev->pdata = dev_get_platdata(&pdev->dev);
660 platform_set_drvdata(pdev, dev);
661
662 if (!dev->pdata && pdev->dev.of_node) {
663 u32 prop;
664
665 dev->pdata = devm_kzalloc(&pdev->dev,
666 sizeof(struct davinci_i2c_platform_data), GFP_KERNEL);
667 if (!dev->pdata)
668 return -ENOMEM;
669
670 memcpy(dev->pdata, &davinci_i2c_platform_data_default,
671 sizeof(struct davinci_i2c_platform_data));
672 if (!of_property_read_u32(pdev->dev.of_node, "clock-frequency",
673 &prop))
674 dev->pdata->bus_freq = prop / 1000;
675 } else if (!dev->pdata) {
676 dev->pdata = &davinci_i2c_platform_data_default;
677 }
678
679 dev->clk = devm_clk_get(&pdev->dev, NULL);
680 if (IS_ERR(dev->clk))
681 return -ENODEV;
682 clk_prepare_enable(dev->clk);
683
684 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
685 dev->base = devm_ioremap_resource(&pdev->dev, mem);
686 if (IS_ERR(dev->base)) {
687 r = PTR_ERR(dev->base);
688 goto err_unuse_clocks;
689 }
690
691 i2c_davinci_init(dev);
692
693 r = devm_request_irq(&pdev->dev, dev->irq, i2c_davinci_isr, 0,
694 pdev->name, dev);
695 if (r) {
696 dev_err(&pdev->dev, "failure requesting irq %i\n", dev->irq);
697 goto err_unuse_clocks;
698 }
699
700 r = i2c_davinci_cpufreq_register(dev);
701 if (r) {
702 dev_err(&pdev->dev, "failed to register cpufreq\n");
703 goto err_unuse_clocks;
704 }
705
706 adap = &dev->adapter;
707 i2c_set_adapdata(adap, dev);
708 adap->owner = THIS_MODULE;
709 adap->class = I2C_CLASS_DEPRECATED;
710 strlcpy(adap->name, "DaVinci I2C adapter", sizeof(adap->name));
711 adap->algo = &i2c_davinci_algo;
712 adap->dev.parent = &pdev->dev;
713 adap->timeout = DAVINCI_I2C_TIMEOUT;
714 adap->dev.of_node = pdev->dev.of_node;
715
716 adap->nr = pdev->id;
717 r = i2c_add_numbered_adapter(adap);
718 if (r) {
719 dev_err(&pdev->dev, "failure adding adapter\n");
720 goto err_unuse_clocks;
721 }
722
723 return 0;
724
725 err_unuse_clocks:
726 clk_disable_unprepare(dev->clk);
727 dev->clk = NULL;
728 return r;
729 }
730
davinci_i2c_remove(struct platform_device * pdev)731 static int davinci_i2c_remove(struct platform_device *pdev)
732 {
733 struct davinci_i2c_dev *dev = platform_get_drvdata(pdev);
734
735 i2c_davinci_cpufreq_deregister(dev);
736
737 i2c_del_adapter(&dev->adapter);
738
739 clk_disable_unprepare(dev->clk);
740 dev->clk = NULL;
741
742 davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, 0);
743
744 return 0;
745 }
746
747 #ifdef CONFIG_PM
davinci_i2c_suspend(struct device * dev)748 static int davinci_i2c_suspend(struct device *dev)
749 {
750 struct platform_device *pdev = to_platform_device(dev);
751 struct davinci_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
752
753 /* put I2C into reset */
754 davinci_i2c_reset_ctrl(i2c_dev, 0);
755 clk_disable_unprepare(i2c_dev->clk);
756
757 return 0;
758 }
759
davinci_i2c_resume(struct device * dev)760 static int davinci_i2c_resume(struct device *dev)
761 {
762 struct platform_device *pdev = to_platform_device(dev);
763 struct davinci_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
764
765 clk_prepare_enable(i2c_dev->clk);
766 /* take I2C out of reset */
767 davinci_i2c_reset_ctrl(i2c_dev, 1);
768
769 return 0;
770 }
771
772 static const struct dev_pm_ops davinci_i2c_pm = {
773 .suspend = davinci_i2c_suspend,
774 .resume = davinci_i2c_resume,
775 };
776
777 #define davinci_i2c_pm_ops (&davinci_i2c_pm)
778 #else
779 #define davinci_i2c_pm_ops NULL
780 #endif
781
782 /* work with hotplug and coldplug */
783 MODULE_ALIAS("platform:i2c_davinci");
784
785 static struct platform_driver davinci_i2c_driver = {
786 .probe = davinci_i2c_probe,
787 .remove = davinci_i2c_remove,
788 .driver = {
789 .name = "i2c_davinci",
790 .owner = THIS_MODULE,
791 .pm = davinci_i2c_pm_ops,
792 .of_match_table = davinci_i2c_of_match,
793 },
794 };
795
796 /* I2C may be needed to bring up other drivers */
davinci_i2c_init_driver(void)797 static int __init davinci_i2c_init_driver(void)
798 {
799 return platform_driver_register(&davinci_i2c_driver);
800 }
801 subsys_initcall(davinci_i2c_init_driver);
802
davinci_i2c_exit_driver(void)803 static void __exit davinci_i2c_exit_driver(void)
804 {
805 platform_driver_unregister(&davinci_i2c_driver);
806 }
807 module_exit(davinci_i2c_exit_driver);
808
809 MODULE_AUTHOR("Texas Instruments India");
810 MODULE_DESCRIPTION("TI DaVinci I2C bus adapter");
811 MODULE_LICENSE("GPL");
812