1 /*
2 * This file is provided under a dual BSD/GPLv2 license. When using or
3 * redistributing this file, you may do so under either license.
4 *
5 * Copyright(c) 2012 Intel Corporation. All rights reserved.
6 *
7 * GPL LICENSE SUMMARY
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of version 2 of the GNU General Public License as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 * The full GNU General Public License is included in this distribution
18 * in the file called LICENSE.GPL.
19 *
20 * BSD LICENSE
21 *
22 * Redistribution and use in source and binary forms, with or without
23 * modification, are permitted provided that the following conditions
24 * are met:
25 *
26 * * Redistributions of source code must retain the above copyright
27 * notice, this list of conditions and the following disclaimer.
28 * * Redistributions in binary form must reproduce the above copyright
29 * notice, this list of conditions and the following disclaimer in
30 * the documentation and/or other materials provided with the
31 * distribution.
32 * * Neither the name of Intel Corporation nor the names of its
33 * contributors may be used to endorse or promote products derived
34 * from this software without specific prior written permission.
35 *
36 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
37 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
38 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
39 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
40 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
41 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
42 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
43 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
44 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
45 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
46 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
47 */
48
49 /*
50 * Supports the SMBus Message Transport (SMT) in the Intel Atom Processor
51 * S12xx Product Family.
52 *
53 * Features supported by this driver:
54 * Hardware PEC yes
55 * Block buffer yes
56 * Block process call transaction no
57 * Slave mode no
58 */
59
60 #include <linux/module.h>
61 #include <linux/pci.h>
62 #include <linux/kernel.h>
63 #include <linux/stddef.h>
64 #include <linux/completion.h>
65 #include <linux/dma-mapping.h>
66 #include <linux/i2c.h>
67 #include <linux/acpi.h>
68 #include <linux/interrupt.h>
69
70 #include <asm-generic/io-64-nonatomic-lo-hi.h>
71
72 /* PCI Address Constants */
73 #define SMBBAR 0
74
75 /* PCI DIDs for the Intel SMBus Message Transport (SMT) Devices */
76 #define PCI_DEVICE_ID_INTEL_S1200_SMT0 0x0c59
77 #define PCI_DEVICE_ID_INTEL_S1200_SMT1 0x0c5a
78 #define PCI_DEVICE_ID_INTEL_AVOTON_SMT 0x1f15
79
80 #define ISMT_DESC_ENTRIES 2 /* number of descriptor entries */
81 #define ISMT_MAX_RETRIES 3 /* number of SMBus retries to attempt */
82
83 /* Hardware Descriptor Constants - Control Field */
84 #define ISMT_DESC_CWRL 0x01 /* Command/Write Length */
85 #define ISMT_DESC_BLK 0X04 /* Perform Block Transaction */
86 #define ISMT_DESC_FAIR 0x08 /* Set fairness flag upon successful arbit. */
87 #define ISMT_DESC_PEC 0x10 /* Packet Error Code */
88 #define ISMT_DESC_I2C 0x20 /* I2C Enable */
89 #define ISMT_DESC_INT 0x40 /* Interrupt */
90 #define ISMT_DESC_SOE 0x80 /* Stop On Error */
91
92 /* Hardware Descriptor Constants - Status Field */
93 #define ISMT_DESC_SCS 0x01 /* Success */
94 #define ISMT_DESC_DLTO 0x04 /* Data Low Time Out */
95 #define ISMT_DESC_NAK 0x08 /* NAK Received */
96 #define ISMT_DESC_CRC 0x10 /* CRC Error */
97 #define ISMT_DESC_CLTO 0x20 /* Clock Low Time Out */
98 #define ISMT_DESC_COL 0x40 /* Collisions */
99 #define ISMT_DESC_LPR 0x80 /* Large Packet Received */
100
101 /* Macros */
102 #define ISMT_DESC_ADDR_RW(addr, rw) (((addr) << 1) | (rw))
103
104 /* iSMT General Register address offsets (SMBBAR + <addr>) */
105 #define ISMT_GR_GCTRL 0x000 /* General Control */
106 #define ISMT_GR_SMTICL 0x008 /* SMT Interrupt Cause Location */
107 #define ISMT_GR_ERRINTMSK 0x010 /* Error Interrupt Mask */
108 #define ISMT_GR_ERRAERMSK 0x014 /* Error AER Mask */
109 #define ISMT_GR_ERRSTS 0x018 /* Error Status */
110 #define ISMT_GR_ERRINFO 0x01c /* Error Information */
111
112 /* iSMT Master Registers */
113 #define ISMT_MSTR_MDBA 0x100 /* Master Descriptor Base Address */
114 #define ISMT_MSTR_MCTRL 0x108 /* Master Control */
115 #define ISMT_MSTR_MSTS 0x10c /* Master Status */
116 #define ISMT_MSTR_MDS 0x110 /* Master Descriptor Size */
117 #define ISMT_MSTR_RPOLICY 0x114 /* Retry Policy */
118
119 /* iSMT Miscellaneous Registers */
120 #define ISMT_SPGT 0x300 /* SMBus PHY Global Timing */
121
122 /* General Control Register (GCTRL) bit definitions */
123 #define ISMT_GCTRL_TRST 0x04 /* Target Reset */
124 #define ISMT_GCTRL_KILL 0x08 /* Kill */
125 #define ISMT_GCTRL_SRST 0x40 /* Soft Reset */
126
127 /* Master Control Register (MCTRL) bit definitions */
128 #define ISMT_MCTRL_SS 0x01 /* Start/Stop */
129 #define ISMT_MCTRL_MEIE 0x10 /* Master Error Interrupt Enable */
130 #define ISMT_MCTRL_FMHP 0x00ff0000 /* Firmware Master Head Ptr (FMHP) */
131
132 /* Master Status Register (MSTS) bit definitions */
133 #define ISMT_MSTS_HMTP 0xff0000 /* HW Master Tail Pointer (HMTP) */
134 #define ISMT_MSTS_MIS 0x20 /* Master Interrupt Status (MIS) */
135 #define ISMT_MSTS_MEIS 0x10 /* Master Error Int Status (MEIS) */
136 #define ISMT_MSTS_IP 0x01 /* In Progress */
137
138 /* Master Descriptor Size (MDS) bit definitions */
139 #define ISMT_MDS_MASK 0xff /* Master Descriptor Size mask (MDS) */
140
141 /* SMBus PHY Global Timing Register (SPGT) bit definitions */
142 #define ISMT_SPGT_SPD_MASK 0xc0000000 /* SMBus Speed mask */
143 #define ISMT_SPGT_SPD_80K 0x00 /* 80 kHz */
144 #define ISMT_SPGT_SPD_100K (0x1 << 30) /* 100 kHz */
145 #define ISMT_SPGT_SPD_400K (0x2 << 30) /* 400 kHz */
146 #define ISMT_SPGT_SPD_1M (0x3 << 30) /* 1 MHz */
147
148
149 /* MSI Control Register (MSICTL) bit definitions */
150 #define ISMT_MSICTL_MSIE 0x01 /* MSI Enable */
151
152 /* iSMT Hardware Descriptor */
153 struct ismt_desc {
154 u8 tgtaddr_rw; /* target address & r/w bit */
155 u8 wr_len_cmd; /* write length in bytes or a command */
156 u8 rd_len; /* read length */
157 u8 control; /* control bits */
158 u8 status; /* status bits */
159 u8 retry; /* collision retry and retry count */
160 u8 rxbytes; /* received bytes */
161 u8 txbytes; /* transmitted bytes */
162 u32 dptr_low; /* lower 32 bit of the data pointer */
163 u32 dptr_high; /* upper 32 bit of the data pointer */
164 } __packed;
165
166 struct ismt_priv {
167 struct i2c_adapter adapter;
168 void *smba; /* PCI BAR */
169 struct pci_dev *pci_dev;
170 struct ismt_desc *hw; /* descriptor virt base addr */
171 dma_addr_t io_rng_dma; /* descriptor HW base addr */
172 u8 head; /* ring buffer head pointer */
173 struct completion cmp; /* interrupt completion */
174 u8 dma_buffer[I2C_SMBUS_BLOCK_MAX + 1]; /* temp R/W data buffer */
175 bool using_msi; /* type of interrupt flag */
176 };
177
178 /**
179 * ismt_ids - PCI device IDs supported by this driver
180 */
181 static const struct pci_device_id ismt_ids[] = {
182 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_S1200_SMT0) },
183 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_S1200_SMT1) },
184 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_AVOTON_SMT) },
185 { 0, }
186 };
187
188 MODULE_DEVICE_TABLE(pci, ismt_ids);
189
190 /* Bus speed control bits for slow debuggers - refer to the docs for usage */
191 static unsigned int bus_speed;
192 module_param(bus_speed, uint, S_IRUGO);
193 MODULE_PARM_DESC(bus_speed, "Bus Speed in kHz (0 = BIOS default)");
194
195 /**
196 * __ismt_desc_dump() - dump the contents of a specific descriptor
197 */
__ismt_desc_dump(struct device * dev,const struct ismt_desc * desc)198 static void __ismt_desc_dump(struct device *dev, const struct ismt_desc *desc)
199 {
200
201 dev_dbg(dev, "Descriptor struct: %p\n", desc);
202 dev_dbg(dev, "\ttgtaddr_rw=0x%02X\n", desc->tgtaddr_rw);
203 dev_dbg(dev, "\twr_len_cmd=0x%02X\n", desc->wr_len_cmd);
204 dev_dbg(dev, "\trd_len= 0x%02X\n", desc->rd_len);
205 dev_dbg(dev, "\tcontrol= 0x%02X\n", desc->control);
206 dev_dbg(dev, "\tstatus= 0x%02X\n", desc->status);
207 dev_dbg(dev, "\tretry= 0x%02X\n", desc->retry);
208 dev_dbg(dev, "\trxbytes= 0x%02X\n", desc->rxbytes);
209 dev_dbg(dev, "\ttxbytes= 0x%02X\n", desc->txbytes);
210 dev_dbg(dev, "\tdptr_low= 0x%08X\n", desc->dptr_low);
211 dev_dbg(dev, "\tdptr_high= 0x%08X\n", desc->dptr_high);
212 }
213 /**
214 * ismt_desc_dump() - dump the contents of a descriptor for debug purposes
215 * @priv: iSMT private data
216 */
ismt_desc_dump(struct ismt_priv * priv)217 static void ismt_desc_dump(struct ismt_priv *priv)
218 {
219 struct device *dev = &priv->pci_dev->dev;
220 struct ismt_desc *desc = &priv->hw[priv->head];
221
222 dev_dbg(dev, "Dump of the descriptor struct: 0x%X\n", priv->head);
223 __ismt_desc_dump(dev, desc);
224 }
225
226 /**
227 * ismt_gen_reg_dump() - dump the iSMT General Registers
228 * @priv: iSMT private data
229 */
ismt_gen_reg_dump(struct ismt_priv * priv)230 static void ismt_gen_reg_dump(struct ismt_priv *priv)
231 {
232 struct device *dev = &priv->pci_dev->dev;
233
234 dev_dbg(dev, "Dump of the iSMT General Registers\n");
235 dev_dbg(dev, " GCTRL.... : (0x%p)=0x%X\n",
236 priv->smba + ISMT_GR_GCTRL,
237 readl(priv->smba + ISMT_GR_GCTRL));
238 dev_dbg(dev, " SMTICL... : (0x%p)=0x%016llX\n",
239 priv->smba + ISMT_GR_SMTICL,
240 (long long unsigned int)readq(priv->smba + ISMT_GR_SMTICL));
241 dev_dbg(dev, " ERRINTMSK : (0x%p)=0x%X\n",
242 priv->smba + ISMT_GR_ERRINTMSK,
243 readl(priv->smba + ISMT_GR_ERRINTMSK));
244 dev_dbg(dev, " ERRAERMSK : (0x%p)=0x%X\n",
245 priv->smba + ISMT_GR_ERRAERMSK,
246 readl(priv->smba + ISMT_GR_ERRAERMSK));
247 dev_dbg(dev, " ERRSTS... : (0x%p)=0x%X\n",
248 priv->smba + ISMT_GR_ERRSTS,
249 readl(priv->smba + ISMT_GR_ERRSTS));
250 dev_dbg(dev, " ERRINFO.. : (0x%p)=0x%X\n",
251 priv->smba + ISMT_GR_ERRINFO,
252 readl(priv->smba + ISMT_GR_ERRINFO));
253 }
254
255 /**
256 * ismt_mstr_reg_dump() - dump the iSMT Master Registers
257 * @priv: iSMT private data
258 */
ismt_mstr_reg_dump(struct ismt_priv * priv)259 static void ismt_mstr_reg_dump(struct ismt_priv *priv)
260 {
261 struct device *dev = &priv->pci_dev->dev;
262
263 dev_dbg(dev, "Dump of the iSMT Master Registers\n");
264 dev_dbg(dev, " MDBA..... : (0x%p)=0x%016llX\n",
265 priv->smba + ISMT_MSTR_MDBA,
266 (long long unsigned int)readq(priv->smba + ISMT_MSTR_MDBA));
267 dev_dbg(dev, " MCTRL.... : (0x%p)=0x%X\n",
268 priv->smba + ISMT_MSTR_MCTRL,
269 readl(priv->smba + ISMT_MSTR_MCTRL));
270 dev_dbg(dev, " MSTS..... : (0x%p)=0x%X\n",
271 priv->smba + ISMT_MSTR_MSTS,
272 readl(priv->smba + ISMT_MSTR_MSTS));
273 dev_dbg(dev, " MDS...... : (0x%p)=0x%X\n",
274 priv->smba + ISMT_MSTR_MDS,
275 readl(priv->smba + ISMT_MSTR_MDS));
276 dev_dbg(dev, " RPOLICY.. : (0x%p)=0x%X\n",
277 priv->smba + ISMT_MSTR_RPOLICY,
278 readl(priv->smba + ISMT_MSTR_RPOLICY));
279 dev_dbg(dev, " SPGT..... : (0x%p)=0x%X\n",
280 priv->smba + ISMT_SPGT,
281 readl(priv->smba + ISMT_SPGT));
282 }
283
284 /**
285 * ismt_submit_desc() - add a descriptor to the ring
286 * @priv: iSMT private data
287 */
ismt_submit_desc(struct ismt_priv * priv)288 static void ismt_submit_desc(struct ismt_priv *priv)
289 {
290 uint fmhp;
291 uint val;
292
293 ismt_desc_dump(priv);
294 ismt_gen_reg_dump(priv);
295 ismt_mstr_reg_dump(priv);
296
297 /* Set the FMHP (Firmware Master Head Pointer)*/
298 fmhp = ((priv->head + 1) % ISMT_DESC_ENTRIES) << 16;
299 val = readl(priv->smba + ISMT_MSTR_MCTRL);
300 writel((val & ~ISMT_MCTRL_FMHP) | fmhp,
301 priv->smba + ISMT_MSTR_MCTRL);
302
303 /* Set the start bit */
304 val = readl(priv->smba + ISMT_MSTR_MCTRL);
305 writel(val | ISMT_MCTRL_SS,
306 priv->smba + ISMT_MSTR_MCTRL);
307 }
308
309 /**
310 * ismt_process_desc() - handle the completion of the descriptor
311 * @desc: the iSMT hardware descriptor
312 * @data: data buffer from the upper layer
313 * @priv: ismt_priv struct holding our dma buffer
314 * @size: SMBus transaction type
315 * @read_write: flag to indicate if this is a read or write
316 */
ismt_process_desc(const struct ismt_desc * desc,union i2c_smbus_data * data,struct ismt_priv * priv,int size,char read_write)317 static int ismt_process_desc(const struct ismt_desc *desc,
318 union i2c_smbus_data *data,
319 struct ismt_priv *priv, int size,
320 char read_write)
321 {
322 u8 *dma_buffer = priv->dma_buffer;
323
324 dev_dbg(&priv->pci_dev->dev, "Processing completed descriptor\n");
325 __ismt_desc_dump(&priv->pci_dev->dev, desc);
326
327 if (desc->status & ISMT_DESC_SCS) {
328 if (read_write == I2C_SMBUS_WRITE &&
329 size != I2C_SMBUS_PROC_CALL)
330 return 0;
331
332 switch (size) {
333 case I2C_SMBUS_BYTE:
334 case I2C_SMBUS_BYTE_DATA:
335 data->byte = dma_buffer[0];
336 break;
337 case I2C_SMBUS_WORD_DATA:
338 case I2C_SMBUS_PROC_CALL:
339 data->word = dma_buffer[0] | (dma_buffer[1] << 8);
340 break;
341 case I2C_SMBUS_BLOCK_DATA:
342 if (desc->rxbytes != dma_buffer[0] + 1)
343 return -EMSGSIZE;
344
345 memcpy(data->block, dma_buffer, desc->rxbytes);
346 break;
347 case I2C_SMBUS_I2C_BLOCK_DATA:
348 memcpy(&data->block[1], dma_buffer, desc->rxbytes);
349 data->block[0] = desc->rxbytes;
350 break;
351 }
352 return 0;
353 }
354
355 if (likely(desc->status & ISMT_DESC_NAK))
356 return -ENXIO;
357
358 if (desc->status & ISMT_DESC_CRC)
359 return -EBADMSG;
360
361 if (desc->status & ISMT_DESC_COL)
362 return -EAGAIN;
363
364 if (desc->status & ISMT_DESC_LPR)
365 return -EPROTO;
366
367 if (desc->status & (ISMT_DESC_DLTO | ISMT_DESC_CLTO))
368 return -ETIMEDOUT;
369
370 return -EIO;
371 }
372
373 /**
374 * ismt_access() - process an SMBus command
375 * @adap: the i2c host adapter
376 * @addr: address of the i2c/SMBus target
377 * @flags: command options
378 * @read_write: read from or write to device
379 * @command: the i2c/SMBus command to issue
380 * @size: SMBus transaction type
381 * @data: read/write data buffer
382 */
ismt_access(struct i2c_adapter * adap,u16 addr,unsigned short flags,char read_write,u8 command,int size,union i2c_smbus_data * data)383 static int ismt_access(struct i2c_adapter *adap, u16 addr,
384 unsigned short flags, char read_write, u8 command,
385 int size, union i2c_smbus_data *data)
386 {
387 int ret;
388 dma_addr_t dma_addr = 0; /* address of the data buffer */
389 u8 dma_size = 0;
390 enum dma_data_direction dma_direction = 0;
391 struct ismt_desc *desc;
392 struct ismt_priv *priv = i2c_get_adapdata(adap);
393 struct device *dev = &priv->pci_dev->dev;
394
395 desc = &priv->hw[priv->head];
396
397 /* Initialize the DMA buffer */
398 memset(priv->dma_buffer, 0, sizeof(priv->dma_buffer));
399
400 /* Initialize the descriptor */
401 memset(desc, 0, sizeof(struct ismt_desc));
402 desc->tgtaddr_rw = ISMT_DESC_ADDR_RW(addr, read_write);
403
404 /* Initialize common control bits */
405 if (likely(priv->using_msi))
406 desc->control = ISMT_DESC_INT | ISMT_DESC_FAIR;
407 else
408 desc->control = ISMT_DESC_FAIR;
409
410 if ((flags & I2C_CLIENT_PEC) && (size != I2C_SMBUS_QUICK)
411 && (size != I2C_SMBUS_I2C_BLOCK_DATA))
412 desc->control |= ISMT_DESC_PEC;
413
414 switch (size) {
415 case I2C_SMBUS_QUICK:
416 dev_dbg(dev, "I2C_SMBUS_QUICK\n");
417 break;
418
419 case I2C_SMBUS_BYTE:
420 if (read_write == I2C_SMBUS_WRITE) {
421 /*
422 * Send Byte
423 * The command field contains the write data
424 */
425 dev_dbg(dev, "I2C_SMBUS_BYTE: WRITE\n");
426 desc->control |= ISMT_DESC_CWRL;
427 desc->wr_len_cmd = command;
428 } else {
429 /* Receive Byte */
430 dev_dbg(dev, "I2C_SMBUS_BYTE: READ\n");
431 dma_size = 1;
432 dma_direction = DMA_FROM_DEVICE;
433 desc->rd_len = 1;
434 }
435 break;
436
437 case I2C_SMBUS_BYTE_DATA:
438 if (read_write == I2C_SMBUS_WRITE) {
439 /*
440 * Write Byte
441 * Command plus 1 data byte
442 */
443 dev_dbg(dev, "I2C_SMBUS_BYTE_DATA: WRITE\n");
444 desc->wr_len_cmd = 2;
445 dma_size = 2;
446 dma_direction = DMA_TO_DEVICE;
447 priv->dma_buffer[0] = command;
448 priv->dma_buffer[1] = data->byte;
449 } else {
450 /* Read Byte */
451 dev_dbg(dev, "I2C_SMBUS_BYTE_DATA: READ\n");
452 desc->control |= ISMT_DESC_CWRL;
453 desc->wr_len_cmd = command;
454 desc->rd_len = 1;
455 dma_size = 1;
456 dma_direction = DMA_FROM_DEVICE;
457 }
458 break;
459
460 case I2C_SMBUS_WORD_DATA:
461 if (read_write == I2C_SMBUS_WRITE) {
462 /* Write Word */
463 dev_dbg(dev, "I2C_SMBUS_WORD_DATA: WRITE\n");
464 desc->wr_len_cmd = 3;
465 dma_size = 3;
466 dma_direction = DMA_TO_DEVICE;
467 priv->dma_buffer[0] = command;
468 priv->dma_buffer[1] = data->word & 0xff;
469 priv->dma_buffer[2] = data->word >> 8;
470 } else {
471 /* Read Word */
472 dev_dbg(dev, "I2C_SMBUS_WORD_DATA: READ\n");
473 desc->wr_len_cmd = command;
474 desc->control |= ISMT_DESC_CWRL;
475 desc->rd_len = 2;
476 dma_size = 2;
477 dma_direction = DMA_FROM_DEVICE;
478 }
479 break;
480
481 case I2C_SMBUS_PROC_CALL:
482 dev_dbg(dev, "I2C_SMBUS_PROC_CALL\n");
483 desc->wr_len_cmd = 3;
484 desc->rd_len = 2;
485 dma_size = 3;
486 dma_direction = DMA_BIDIRECTIONAL;
487 priv->dma_buffer[0] = command;
488 priv->dma_buffer[1] = data->word & 0xff;
489 priv->dma_buffer[2] = data->word >> 8;
490 break;
491
492 case I2C_SMBUS_BLOCK_DATA:
493 if (read_write == I2C_SMBUS_WRITE) {
494 /* Block Write */
495 dev_dbg(dev, "I2C_SMBUS_BLOCK_DATA: WRITE\n");
496 dma_size = data->block[0] + 1;
497 dma_direction = DMA_TO_DEVICE;
498 desc->wr_len_cmd = dma_size;
499 desc->control |= ISMT_DESC_BLK;
500 priv->dma_buffer[0] = command;
501 memcpy(&priv->dma_buffer[1], &data->block[1], dma_size - 1);
502 } else {
503 /* Block Read */
504 dev_dbg(dev, "I2C_SMBUS_BLOCK_DATA: READ\n");
505 dma_size = I2C_SMBUS_BLOCK_MAX;
506 dma_direction = DMA_FROM_DEVICE;
507 desc->rd_len = dma_size;
508 desc->wr_len_cmd = command;
509 desc->control |= (ISMT_DESC_BLK | ISMT_DESC_CWRL);
510 }
511 break;
512
513 case I2C_SMBUS_I2C_BLOCK_DATA:
514 /* Make sure the length is valid */
515 if (data->block[0] < 1)
516 data->block[0] = 1;
517
518 if (data->block[0] > I2C_SMBUS_BLOCK_MAX)
519 data->block[0] = I2C_SMBUS_BLOCK_MAX;
520
521 if (read_write == I2C_SMBUS_WRITE) {
522 /* i2c Block Write */
523 dev_dbg(dev, "I2C_SMBUS_I2C_BLOCK_DATA: WRITE\n");
524 dma_size = data->block[0] + 1;
525 dma_direction = DMA_TO_DEVICE;
526 desc->wr_len_cmd = dma_size;
527 desc->control |= ISMT_DESC_I2C;
528 priv->dma_buffer[0] = command;
529 memcpy(&priv->dma_buffer[1], &data->block[1], dma_size - 1);
530 } else {
531 /* i2c Block Read */
532 dev_dbg(dev, "I2C_SMBUS_I2C_BLOCK_DATA: READ\n");
533 dma_size = data->block[0];
534 dma_direction = DMA_FROM_DEVICE;
535 desc->rd_len = dma_size;
536 desc->wr_len_cmd = command;
537 desc->control |= (ISMT_DESC_I2C | ISMT_DESC_CWRL);
538 /*
539 * Per the "Table 15-15. I2C Commands",
540 * in the External Design Specification (EDS),
541 * (Document Number: 508084, Revision: 2.0),
542 * the _rw bit must be 0
543 */
544 desc->tgtaddr_rw = ISMT_DESC_ADDR_RW(addr, 0);
545 }
546 break;
547
548 default:
549 dev_err(dev, "Unsupported transaction %d\n",
550 size);
551 return -EOPNOTSUPP;
552 }
553
554 /* map the data buffer */
555 if (dma_size != 0) {
556 dev_dbg(dev, " dev=%p\n", dev);
557 dev_dbg(dev, " data=%p\n", data);
558 dev_dbg(dev, " dma_buffer=%p\n", priv->dma_buffer);
559 dev_dbg(dev, " dma_size=%d\n", dma_size);
560 dev_dbg(dev, " dma_direction=%d\n", dma_direction);
561
562 dma_addr = dma_map_single(dev,
563 priv->dma_buffer,
564 dma_size,
565 dma_direction);
566
567 if (dma_mapping_error(dev, dma_addr)) {
568 dev_err(dev, "Error in mapping dma buffer %p\n",
569 priv->dma_buffer);
570 return -EIO;
571 }
572
573 dev_dbg(dev, " dma_addr = 0x%016llX\n",
574 (unsigned long long)dma_addr);
575
576 desc->dptr_low = lower_32_bits(dma_addr);
577 desc->dptr_high = upper_32_bits(dma_addr);
578 }
579
580 reinit_completion(&priv->cmp);
581
582 /* Add the descriptor */
583 ismt_submit_desc(priv);
584
585 /* Now we wait for interrupt completion, 1s */
586 ret = wait_for_completion_timeout(&priv->cmp, HZ*1);
587
588 /* unmap the data buffer */
589 if (dma_size != 0)
590 dma_unmap_single(&adap->dev, dma_addr, dma_size, dma_direction);
591
592 if (unlikely(!ret)) {
593 dev_err(dev, "completion wait timed out\n");
594 ret = -ETIMEDOUT;
595 goto out;
596 }
597
598 /* do any post processing of the descriptor here */
599 ret = ismt_process_desc(desc, data, priv, size, read_write);
600
601 out:
602 /* Update the ring pointer */
603 priv->head++;
604 priv->head %= ISMT_DESC_ENTRIES;
605
606 return ret;
607 }
608
609 /**
610 * ismt_func() - report which i2c commands are supported by this adapter
611 * @adap: the i2c host adapter
612 */
ismt_func(struct i2c_adapter * adap)613 static u32 ismt_func(struct i2c_adapter *adap)
614 {
615 return I2C_FUNC_SMBUS_QUICK |
616 I2C_FUNC_SMBUS_BYTE |
617 I2C_FUNC_SMBUS_BYTE_DATA |
618 I2C_FUNC_SMBUS_WORD_DATA |
619 I2C_FUNC_SMBUS_PROC_CALL |
620 I2C_FUNC_SMBUS_BLOCK_DATA |
621 I2C_FUNC_SMBUS_I2C_BLOCK |
622 I2C_FUNC_SMBUS_PEC;
623 }
624
625 /**
626 * smbus_algorithm - the adapter algorithm and supported functionality
627 * @smbus_xfer: the adapter algorithm
628 * @functionality: functionality supported by the adapter
629 */
630 static const struct i2c_algorithm smbus_algorithm = {
631 .smbus_xfer = ismt_access,
632 .functionality = ismt_func,
633 };
634
635 /**
636 * ismt_handle_isr() - interrupt handler bottom half
637 * @priv: iSMT private data
638 */
ismt_handle_isr(struct ismt_priv * priv)639 static irqreturn_t ismt_handle_isr(struct ismt_priv *priv)
640 {
641 complete(&priv->cmp);
642
643 return IRQ_HANDLED;
644 }
645
646
647 /**
648 * ismt_do_interrupt() - IRQ interrupt handler
649 * @vec: interrupt vector
650 * @data: iSMT private data
651 */
ismt_do_interrupt(int vec,void * data)652 static irqreturn_t ismt_do_interrupt(int vec, void *data)
653 {
654 u32 val;
655 struct ismt_priv *priv = data;
656
657 /*
658 * check to see it's our interrupt, return IRQ_NONE if not ours
659 * since we are sharing interrupt
660 */
661 val = readl(priv->smba + ISMT_MSTR_MSTS);
662
663 if (!(val & (ISMT_MSTS_MIS | ISMT_MSTS_MEIS)))
664 return IRQ_NONE;
665 else
666 writel(val | ISMT_MSTS_MIS | ISMT_MSTS_MEIS,
667 priv->smba + ISMT_MSTR_MSTS);
668
669 return ismt_handle_isr(priv);
670 }
671
672 /**
673 * ismt_do_msi_interrupt() - MSI interrupt handler
674 * @vec: interrupt vector
675 * @data: iSMT private data
676 */
ismt_do_msi_interrupt(int vec,void * data)677 static irqreturn_t ismt_do_msi_interrupt(int vec, void *data)
678 {
679 return ismt_handle_isr(data);
680 }
681
682 /**
683 * ismt_hw_init() - initialize the iSMT hardware
684 * @priv: iSMT private data
685 */
ismt_hw_init(struct ismt_priv * priv)686 static void ismt_hw_init(struct ismt_priv *priv)
687 {
688 u32 val;
689 struct device *dev = &priv->pci_dev->dev;
690
691 /* initialize the Master Descriptor Base Address (MDBA) */
692 writeq(priv->io_rng_dma, priv->smba + ISMT_MSTR_MDBA);
693
694 /* initialize the Master Control Register (MCTRL) */
695 writel(ISMT_MCTRL_MEIE, priv->smba + ISMT_MSTR_MCTRL);
696
697 /* initialize the Master Status Register (MSTS) */
698 writel(0, priv->smba + ISMT_MSTR_MSTS);
699
700 /* initialize the Master Descriptor Size (MDS) */
701 val = readl(priv->smba + ISMT_MSTR_MDS);
702 writel((val & ~ISMT_MDS_MASK) | (ISMT_DESC_ENTRIES - 1),
703 priv->smba + ISMT_MSTR_MDS);
704
705 /*
706 * Set the SMBus speed (could use this for slow HW debuggers)
707 */
708
709 val = readl(priv->smba + ISMT_SPGT);
710
711 switch (bus_speed) {
712 case 0:
713 break;
714
715 case 80:
716 dev_dbg(dev, "Setting SMBus clock to 80 kHz\n");
717 writel(((val & ~ISMT_SPGT_SPD_MASK) | ISMT_SPGT_SPD_80K),
718 priv->smba + ISMT_SPGT);
719 break;
720
721 case 100:
722 dev_dbg(dev, "Setting SMBus clock to 100 kHz\n");
723 writel(((val & ~ISMT_SPGT_SPD_MASK) | ISMT_SPGT_SPD_100K),
724 priv->smba + ISMT_SPGT);
725 break;
726
727 case 400:
728 dev_dbg(dev, "Setting SMBus clock to 400 kHz\n");
729 writel(((val & ~ISMT_SPGT_SPD_MASK) | ISMT_SPGT_SPD_400K),
730 priv->smba + ISMT_SPGT);
731 break;
732
733 case 1000:
734 dev_dbg(dev, "Setting SMBus clock to 1000 kHz\n");
735 writel(((val & ~ISMT_SPGT_SPD_MASK) | ISMT_SPGT_SPD_1M),
736 priv->smba + ISMT_SPGT);
737 break;
738
739 default:
740 dev_warn(dev, "Invalid SMBus clock speed, only 0, 80, 100, 400, and 1000 are valid\n");
741 break;
742 }
743
744 val = readl(priv->smba + ISMT_SPGT);
745
746 switch (val & ISMT_SPGT_SPD_MASK) {
747 case ISMT_SPGT_SPD_80K:
748 bus_speed = 80;
749 break;
750 case ISMT_SPGT_SPD_100K:
751 bus_speed = 100;
752 break;
753 case ISMT_SPGT_SPD_400K:
754 bus_speed = 400;
755 break;
756 case ISMT_SPGT_SPD_1M:
757 bus_speed = 1000;
758 break;
759 }
760 dev_dbg(dev, "SMBus clock is running at %d kHz\n", bus_speed);
761 }
762
763 /**
764 * ismt_dev_init() - initialize the iSMT data structures
765 * @priv: iSMT private data
766 */
ismt_dev_init(struct ismt_priv * priv)767 static int ismt_dev_init(struct ismt_priv *priv)
768 {
769 /* allocate memory for the descriptor */
770 priv->hw = dmam_alloc_coherent(&priv->pci_dev->dev,
771 (ISMT_DESC_ENTRIES
772 * sizeof(struct ismt_desc)),
773 &priv->io_rng_dma,
774 GFP_KERNEL);
775 if (!priv->hw)
776 return -ENOMEM;
777
778 memset(priv->hw, 0, (ISMT_DESC_ENTRIES * sizeof(struct ismt_desc)));
779
780 priv->head = 0;
781 init_completion(&priv->cmp);
782
783 return 0;
784 }
785
786 /**
787 * ismt_int_init() - initialize interrupts
788 * @priv: iSMT private data
789 */
ismt_int_init(struct ismt_priv * priv)790 static int ismt_int_init(struct ismt_priv *priv)
791 {
792 int err;
793
794 /* Try using MSI interrupts */
795 err = pci_enable_msi(priv->pci_dev);
796 if (err) {
797 dev_warn(&priv->pci_dev->dev,
798 "Unable to use MSI interrupts, falling back to legacy\n");
799 goto intx;
800 }
801
802 err = devm_request_irq(&priv->pci_dev->dev,
803 priv->pci_dev->irq,
804 ismt_do_msi_interrupt,
805 0,
806 "ismt-msi",
807 priv);
808 if (err) {
809 pci_disable_msi(priv->pci_dev);
810 goto intx;
811 }
812
813 priv->using_msi = true;
814 goto done;
815
816 /* Try using legacy interrupts */
817 intx:
818 err = devm_request_irq(&priv->pci_dev->dev,
819 priv->pci_dev->irq,
820 ismt_do_interrupt,
821 IRQF_SHARED,
822 "ismt-intx",
823 priv);
824 if (err) {
825 dev_err(&priv->pci_dev->dev, "no usable interrupts\n");
826 return -ENODEV;
827 }
828
829 priv->using_msi = false;
830
831 done:
832 return 0;
833 }
834
835 static struct pci_driver ismt_driver;
836
837 /**
838 * ismt_probe() - probe for iSMT devices
839 * @pdev: PCI-Express device
840 * @id: PCI-Express device ID
841 */
842 static int
ismt_probe(struct pci_dev * pdev,const struct pci_device_id * id)843 ismt_probe(struct pci_dev *pdev, const struct pci_device_id *id)
844 {
845 int err;
846 struct ismt_priv *priv;
847 unsigned long start, len;
848
849 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
850 if (!priv)
851 return -ENOMEM;
852
853 pci_set_drvdata(pdev, priv);
854 i2c_set_adapdata(&priv->adapter, priv);
855 priv->adapter.owner = THIS_MODULE;
856
857 priv->adapter.class = I2C_CLASS_HWMON;
858
859 priv->adapter.algo = &smbus_algorithm;
860
861 /* set up the sysfs linkage to our parent device */
862 priv->adapter.dev.parent = &pdev->dev;
863
864 /* number of retries on lost arbitration */
865 priv->adapter.retries = ISMT_MAX_RETRIES;
866
867 priv->pci_dev = pdev;
868
869 err = pcim_enable_device(pdev);
870 if (err) {
871 dev_err(&pdev->dev, "Failed to enable SMBus PCI device (%d)\n",
872 err);
873 return err;
874 }
875
876 /* enable bus mastering */
877 pci_set_master(pdev);
878
879 /* Determine the address of the SMBus area */
880 start = pci_resource_start(pdev, SMBBAR);
881 len = pci_resource_len(pdev, SMBBAR);
882 if (!start || !len) {
883 dev_err(&pdev->dev,
884 "SMBus base address uninitialized, upgrade BIOS\n");
885 return -ENODEV;
886 }
887
888 snprintf(priv->adapter.name, sizeof(priv->adapter.name),
889 "SMBus iSMT adapter at %lx", start);
890
891 dev_dbg(&priv->pci_dev->dev, " start=0x%lX\n", start);
892 dev_dbg(&priv->pci_dev->dev, " len=0x%lX\n", len);
893
894 err = acpi_check_resource_conflict(&pdev->resource[SMBBAR]);
895 if (err) {
896 dev_err(&pdev->dev, "ACPI resource conflict!\n");
897 return err;
898 }
899
900 err = pci_request_region(pdev, SMBBAR, ismt_driver.name);
901 if (err) {
902 dev_err(&pdev->dev,
903 "Failed to request SMBus region 0x%lx-0x%lx\n",
904 start, start + len);
905 return err;
906 }
907
908 priv->smba = pcim_iomap(pdev, SMBBAR, len);
909 if (!priv->smba) {
910 dev_err(&pdev->dev, "Unable to ioremap SMBus BAR\n");
911 err = -ENODEV;
912 goto fail;
913 }
914
915 if ((pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) != 0) ||
916 (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)) != 0)) {
917 if ((pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) != 0) ||
918 (pci_set_consistent_dma_mask(pdev,
919 DMA_BIT_MASK(32)) != 0)) {
920 dev_err(&pdev->dev, "pci_set_dma_mask fail %p\n",
921 pdev);
922 err = -ENODEV;
923 goto fail;
924 }
925 }
926
927 err = ismt_dev_init(priv);
928 if (err)
929 goto fail;
930
931 ismt_hw_init(priv);
932
933 err = ismt_int_init(priv);
934 if (err)
935 goto fail;
936
937 err = i2c_add_adapter(&priv->adapter);
938 if (err) {
939 dev_err(&pdev->dev, "Failed to add SMBus iSMT adapter\n");
940 err = -ENODEV;
941 goto fail;
942 }
943 return 0;
944
945 fail:
946 pci_release_region(pdev, SMBBAR);
947 return err;
948 }
949
950 /**
951 * ismt_remove() - release driver resources
952 * @pdev: PCI-Express device
953 */
ismt_remove(struct pci_dev * pdev)954 static void ismt_remove(struct pci_dev *pdev)
955 {
956 struct ismt_priv *priv = pci_get_drvdata(pdev);
957
958 i2c_del_adapter(&priv->adapter);
959 pci_release_region(pdev, SMBBAR);
960 }
961
962 /**
963 * ismt_suspend() - place the device in suspend
964 * @pdev: PCI-Express device
965 * @mesg: PM message
966 */
967 #ifdef CONFIG_PM
ismt_suspend(struct pci_dev * pdev,pm_message_t mesg)968 static int ismt_suspend(struct pci_dev *pdev, pm_message_t mesg)
969 {
970 pci_save_state(pdev);
971 pci_set_power_state(pdev, pci_choose_state(pdev, mesg));
972 return 0;
973 }
974
975 /**
976 * ismt_resume() - PCI resume code
977 * @pdev: PCI-Express device
978 */
ismt_resume(struct pci_dev * pdev)979 static int ismt_resume(struct pci_dev *pdev)
980 {
981 pci_set_power_state(pdev, PCI_D0);
982 pci_restore_state(pdev);
983 return pci_enable_device(pdev);
984 }
985
986 #else
987
988 #define ismt_suspend NULL
989 #define ismt_resume NULL
990
991 #endif
992
993 static struct pci_driver ismt_driver = {
994 .name = "ismt_smbus",
995 .id_table = ismt_ids,
996 .probe = ismt_probe,
997 .remove = ismt_remove,
998 .suspend = ismt_suspend,
999 .resume = ismt_resume,
1000 };
1001
1002 module_pci_driver(ismt_driver);
1003
1004 MODULE_LICENSE("Dual BSD/GPL");
1005 MODULE_AUTHOR("Bill E. Brown <bill.e.brown@intel.com>");
1006 MODULE_DESCRIPTION("Intel SMBus Message Transport (iSMT) driver");
1007