1 /*
2 * isphist.c
3 *
4 * TI OMAP3 ISP - Histogram module
5 *
6 * Copyright (C) 2010 Nokia Corporation
7 * Copyright (C) 2009 Texas Instruments, Inc.
8 *
9 * Contacts: David Cohen <dacohen@gmail.com>
10 * Laurent Pinchart <laurent.pinchart@ideasonboard.com>
11 * Sakari Ailus <sakari.ailus@iki.fi>
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
16 */
17
18 #include <linux/delay.h>
19 #include <linux/slab.h>
20 #include <linux/uaccess.h>
21 #include <linux/device.h>
22
23 #include "isp.h"
24 #include "ispreg.h"
25 #include "isphist.h"
26
27 #define OMAP24XX_DMA_NO_DEVICE 0
28
29 #define HIST_CONFIG_DMA 1
30
31 #define HIST_USING_DMA(hist) ((hist)->dma_ch >= 0)
32
33 /*
34 * hist_reset_mem - clear Histogram memory before start stats engine.
35 */
hist_reset_mem(struct ispstat * hist)36 static void hist_reset_mem(struct ispstat *hist)
37 {
38 struct isp_device *isp = hist->isp;
39 struct omap3isp_hist_config *conf = hist->priv;
40 unsigned int i;
41
42 isp_reg_writel(isp, 0, OMAP3_ISP_IOMEM_HIST, ISPHIST_ADDR);
43
44 /*
45 * By setting it, the histogram internal buffer is being cleared at the
46 * same time it's being read. This bit must be cleared afterwards.
47 */
48 isp_reg_set(isp, OMAP3_ISP_IOMEM_HIST, ISPHIST_CNT, ISPHIST_CNT_CLEAR);
49
50 /*
51 * We'll clear 4 words at each iteration for optimization. It avoids
52 * 3/4 of the jumps. We also know HIST_MEM_SIZE is divisible by 4.
53 */
54 for (i = OMAP3ISP_HIST_MEM_SIZE / 4; i > 0; i--) {
55 isp_reg_readl(isp, OMAP3_ISP_IOMEM_HIST, ISPHIST_DATA);
56 isp_reg_readl(isp, OMAP3_ISP_IOMEM_HIST, ISPHIST_DATA);
57 isp_reg_readl(isp, OMAP3_ISP_IOMEM_HIST, ISPHIST_DATA);
58 isp_reg_readl(isp, OMAP3_ISP_IOMEM_HIST, ISPHIST_DATA);
59 }
60 isp_reg_clr(isp, OMAP3_ISP_IOMEM_HIST, ISPHIST_CNT, ISPHIST_CNT_CLEAR);
61
62 hist->wait_acc_frames = conf->num_acc_frames;
63 }
64
hist_dma_config(struct ispstat * hist)65 static void hist_dma_config(struct ispstat *hist)
66 {
67 struct isp_device *isp = hist->isp;
68
69 hist->dma_config.data_type = OMAP_DMA_DATA_TYPE_S32;
70 hist->dma_config.sync_mode = OMAP_DMA_SYNC_ELEMENT;
71 hist->dma_config.frame_count = 1;
72 hist->dma_config.src_amode = OMAP_DMA_AMODE_CONSTANT;
73 hist->dma_config.src_start = isp->mmio_base_phys[OMAP3_ISP_IOMEM_HIST]
74 + ISPHIST_DATA;
75 hist->dma_config.dst_amode = OMAP_DMA_AMODE_POST_INC;
76 hist->dma_config.src_or_dst_synch = OMAP_DMA_SRC_SYNC;
77 }
78
79 /*
80 * hist_setup_regs - Helper function to update Histogram registers.
81 */
hist_setup_regs(struct ispstat * hist,void * priv)82 static void hist_setup_regs(struct ispstat *hist, void *priv)
83 {
84 struct isp_device *isp = hist->isp;
85 struct omap3isp_hist_config *conf = priv;
86 int c;
87 u32 cnt;
88 u32 wb_gain;
89 u32 reg_hor[OMAP3ISP_HIST_MAX_REGIONS];
90 u32 reg_ver[OMAP3ISP_HIST_MAX_REGIONS];
91
92 if (!hist->update || hist->state == ISPSTAT_DISABLED ||
93 hist->state == ISPSTAT_DISABLING)
94 return;
95
96 cnt = conf->cfa << ISPHIST_CNT_CFA_SHIFT;
97
98 wb_gain = conf->wg[0] << ISPHIST_WB_GAIN_WG00_SHIFT;
99 wb_gain |= conf->wg[1] << ISPHIST_WB_GAIN_WG01_SHIFT;
100 wb_gain |= conf->wg[2] << ISPHIST_WB_GAIN_WG02_SHIFT;
101 if (conf->cfa == OMAP3ISP_HIST_CFA_BAYER)
102 wb_gain |= conf->wg[3] << ISPHIST_WB_GAIN_WG03_SHIFT;
103
104 /* Regions size and position */
105 for (c = 0; c < OMAP3ISP_HIST_MAX_REGIONS; c++) {
106 if (c < conf->num_regions) {
107 reg_hor[c] = (conf->region[c].h_start <<
108 ISPHIST_REG_START_SHIFT)
109 | (conf->region[c].h_end <<
110 ISPHIST_REG_END_SHIFT);
111 reg_ver[c] = (conf->region[c].v_start <<
112 ISPHIST_REG_START_SHIFT)
113 | (conf->region[c].v_end <<
114 ISPHIST_REG_END_SHIFT);
115 } else {
116 reg_hor[c] = 0;
117 reg_ver[c] = 0;
118 }
119 }
120
121 cnt |= conf->hist_bins << ISPHIST_CNT_BINS_SHIFT;
122 switch (conf->hist_bins) {
123 case OMAP3ISP_HIST_BINS_256:
124 cnt |= (ISPHIST_IN_BIT_WIDTH_CCDC - 8) <<
125 ISPHIST_CNT_SHIFT_SHIFT;
126 break;
127 case OMAP3ISP_HIST_BINS_128:
128 cnt |= (ISPHIST_IN_BIT_WIDTH_CCDC - 7) <<
129 ISPHIST_CNT_SHIFT_SHIFT;
130 break;
131 case OMAP3ISP_HIST_BINS_64:
132 cnt |= (ISPHIST_IN_BIT_WIDTH_CCDC - 6) <<
133 ISPHIST_CNT_SHIFT_SHIFT;
134 break;
135 default: /* OMAP3ISP_HIST_BINS_32 */
136 cnt |= (ISPHIST_IN_BIT_WIDTH_CCDC - 5) <<
137 ISPHIST_CNT_SHIFT_SHIFT;
138 break;
139 }
140
141 hist_reset_mem(hist);
142
143 isp_reg_writel(isp, cnt, OMAP3_ISP_IOMEM_HIST, ISPHIST_CNT);
144 isp_reg_writel(isp, wb_gain, OMAP3_ISP_IOMEM_HIST, ISPHIST_WB_GAIN);
145 isp_reg_writel(isp, reg_hor[0], OMAP3_ISP_IOMEM_HIST, ISPHIST_R0_HORZ);
146 isp_reg_writel(isp, reg_ver[0], OMAP3_ISP_IOMEM_HIST, ISPHIST_R0_VERT);
147 isp_reg_writel(isp, reg_hor[1], OMAP3_ISP_IOMEM_HIST, ISPHIST_R1_HORZ);
148 isp_reg_writel(isp, reg_ver[1], OMAP3_ISP_IOMEM_HIST, ISPHIST_R1_VERT);
149 isp_reg_writel(isp, reg_hor[2], OMAP3_ISP_IOMEM_HIST, ISPHIST_R2_HORZ);
150 isp_reg_writel(isp, reg_ver[2], OMAP3_ISP_IOMEM_HIST, ISPHIST_R2_VERT);
151 isp_reg_writel(isp, reg_hor[3], OMAP3_ISP_IOMEM_HIST, ISPHIST_R3_HORZ);
152 isp_reg_writel(isp, reg_ver[3], OMAP3_ISP_IOMEM_HIST, ISPHIST_R3_VERT);
153
154 hist->update = 0;
155 hist->config_counter += hist->inc_config;
156 hist->inc_config = 0;
157 hist->buf_size = conf->buf_size;
158 }
159
hist_enable(struct ispstat * hist,int enable)160 static void hist_enable(struct ispstat *hist, int enable)
161 {
162 if (enable) {
163 isp_reg_set(hist->isp, OMAP3_ISP_IOMEM_HIST, ISPHIST_PCR,
164 ISPHIST_PCR_ENABLE);
165 omap3isp_subclk_enable(hist->isp, OMAP3_ISP_SUBCLK_HIST);
166 } else {
167 isp_reg_clr(hist->isp, OMAP3_ISP_IOMEM_HIST, ISPHIST_PCR,
168 ISPHIST_PCR_ENABLE);
169 omap3isp_subclk_disable(hist->isp, OMAP3_ISP_SUBCLK_HIST);
170 }
171 }
172
hist_busy(struct ispstat * hist)173 static int hist_busy(struct ispstat *hist)
174 {
175 return isp_reg_readl(hist->isp, OMAP3_ISP_IOMEM_HIST, ISPHIST_PCR)
176 & ISPHIST_PCR_BUSY;
177 }
178
hist_dma_cb(int lch,u16 ch_status,void * data)179 static void hist_dma_cb(int lch, u16 ch_status, void *data)
180 {
181 struct ispstat *hist = data;
182
183 if (ch_status & ~OMAP_DMA_BLOCK_IRQ) {
184 dev_dbg(hist->isp->dev, "hist: DMA error. status = 0x%04x\n",
185 ch_status);
186 omap_stop_dma(lch);
187 hist_reset_mem(hist);
188 atomic_set(&hist->buf_err, 1);
189 }
190 isp_reg_clr(hist->isp, OMAP3_ISP_IOMEM_HIST, ISPHIST_CNT,
191 ISPHIST_CNT_CLEAR);
192
193 omap3isp_stat_dma_isr(hist);
194 if (hist->state != ISPSTAT_DISABLED)
195 omap3isp_hist_dma_done(hist->isp);
196 }
197
hist_buf_dma(struct ispstat * hist)198 static int hist_buf_dma(struct ispstat *hist)
199 {
200 dma_addr_t dma_addr = hist->active_buf->dma_addr;
201
202 if (unlikely(!dma_addr)) {
203 dev_dbg(hist->isp->dev, "hist: invalid DMA buffer address\n");
204 hist_reset_mem(hist);
205 return STAT_NO_BUF;
206 }
207
208 isp_reg_writel(hist->isp, 0, OMAP3_ISP_IOMEM_HIST, ISPHIST_ADDR);
209 isp_reg_set(hist->isp, OMAP3_ISP_IOMEM_HIST, ISPHIST_CNT,
210 ISPHIST_CNT_CLEAR);
211 omap3isp_flush(hist->isp);
212 hist->dma_config.dst_start = dma_addr;
213 hist->dma_config.elem_count = hist->buf_size / sizeof(u32);
214 omap_set_dma_params(hist->dma_ch, &hist->dma_config);
215
216 omap_start_dma(hist->dma_ch);
217
218 return STAT_BUF_WAITING_DMA;
219 }
220
hist_buf_pio(struct ispstat * hist)221 static int hist_buf_pio(struct ispstat *hist)
222 {
223 struct isp_device *isp = hist->isp;
224 u32 *buf = hist->active_buf->virt_addr;
225 unsigned int i;
226
227 if (!buf) {
228 dev_dbg(isp->dev, "hist: invalid PIO buffer address\n");
229 hist_reset_mem(hist);
230 return STAT_NO_BUF;
231 }
232
233 isp_reg_writel(isp, 0, OMAP3_ISP_IOMEM_HIST, ISPHIST_ADDR);
234
235 /*
236 * By setting it, the histogram internal buffer is being cleared at the
237 * same time it's being read. This bit must be cleared just after all
238 * data is acquired.
239 */
240 isp_reg_set(isp, OMAP3_ISP_IOMEM_HIST, ISPHIST_CNT, ISPHIST_CNT_CLEAR);
241
242 /*
243 * We'll read 4 times a 4-bytes-word at each iteration for
244 * optimization. It avoids 3/4 of the jumps. We also know buf_size is
245 * divisible by 16.
246 */
247 for (i = hist->buf_size / 16; i > 0; i--) {
248 *buf++ = isp_reg_readl(isp, OMAP3_ISP_IOMEM_HIST, ISPHIST_DATA);
249 *buf++ = isp_reg_readl(isp, OMAP3_ISP_IOMEM_HIST, ISPHIST_DATA);
250 *buf++ = isp_reg_readl(isp, OMAP3_ISP_IOMEM_HIST, ISPHIST_DATA);
251 *buf++ = isp_reg_readl(isp, OMAP3_ISP_IOMEM_HIST, ISPHIST_DATA);
252 }
253 isp_reg_clr(hist->isp, OMAP3_ISP_IOMEM_HIST, ISPHIST_CNT,
254 ISPHIST_CNT_CLEAR);
255
256 return STAT_BUF_DONE;
257 }
258
259 /*
260 * hist_buf_process - Callback from ISP driver for HIST interrupt.
261 */
hist_buf_process(struct ispstat * hist)262 static int hist_buf_process(struct ispstat *hist)
263 {
264 struct omap3isp_hist_config *user_cfg = hist->priv;
265 int ret;
266
267 if (atomic_read(&hist->buf_err) || hist->state != ISPSTAT_ENABLED) {
268 hist_reset_mem(hist);
269 return STAT_NO_BUF;
270 }
271
272 if (--(hist->wait_acc_frames))
273 return STAT_NO_BUF;
274
275 if (HIST_USING_DMA(hist))
276 ret = hist_buf_dma(hist);
277 else
278 ret = hist_buf_pio(hist);
279
280 hist->wait_acc_frames = user_cfg->num_acc_frames;
281
282 return ret;
283 }
284
hist_get_buf_size(struct omap3isp_hist_config * conf)285 static u32 hist_get_buf_size(struct omap3isp_hist_config *conf)
286 {
287 return OMAP3ISP_HIST_MEM_SIZE_BINS(conf->hist_bins) * conf->num_regions;
288 }
289
290 /*
291 * hist_validate_params - Helper function to check user given params.
292 * @new_conf: Pointer to user configuration structure.
293 *
294 * Returns 0 on success configuration.
295 */
hist_validate_params(struct ispstat * hist,void * new_conf)296 static int hist_validate_params(struct ispstat *hist, void *new_conf)
297 {
298 struct omap3isp_hist_config *user_cfg = new_conf;
299 int c;
300 u32 buf_size;
301
302 if (user_cfg->cfa > OMAP3ISP_HIST_CFA_FOVEONX3)
303 return -EINVAL;
304
305 /* Regions size and position */
306
307 if ((user_cfg->num_regions < OMAP3ISP_HIST_MIN_REGIONS) ||
308 (user_cfg->num_regions > OMAP3ISP_HIST_MAX_REGIONS))
309 return -EINVAL;
310
311 /* Regions */
312 for (c = 0; c < user_cfg->num_regions; c++) {
313 if (user_cfg->region[c].h_start & ~ISPHIST_REG_START_END_MASK)
314 return -EINVAL;
315 if (user_cfg->region[c].h_end & ~ISPHIST_REG_START_END_MASK)
316 return -EINVAL;
317 if (user_cfg->region[c].v_start & ~ISPHIST_REG_START_END_MASK)
318 return -EINVAL;
319 if (user_cfg->region[c].v_end & ~ISPHIST_REG_START_END_MASK)
320 return -EINVAL;
321 if (user_cfg->region[c].h_start > user_cfg->region[c].h_end)
322 return -EINVAL;
323 if (user_cfg->region[c].v_start > user_cfg->region[c].v_end)
324 return -EINVAL;
325 }
326
327 switch (user_cfg->num_regions) {
328 case 1:
329 if (user_cfg->hist_bins > OMAP3ISP_HIST_BINS_256)
330 return -EINVAL;
331 break;
332 case 2:
333 if (user_cfg->hist_bins > OMAP3ISP_HIST_BINS_128)
334 return -EINVAL;
335 break;
336 default: /* 3 or 4 */
337 if (user_cfg->hist_bins > OMAP3ISP_HIST_BINS_64)
338 return -EINVAL;
339 break;
340 }
341
342 buf_size = hist_get_buf_size(user_cfg);
343 if (buf_size > user_cfg->buf_size)
344 /* User's buf_size request wasn't enough */
345 user_cfg->buf_size = buf_size;
346 else if (user_cfg->buf_size > OMAP3ISP_HIST_MAX_BUF_SIZE)
347 user_cfg->buf_size = OMAP3ISP_HIST_MAX_BUF_SIZE;
348
349 return 0;
350 }
351
hist_comp_params(struct ispstat * hist,struct omap3isp_hist_config * user_cfg)352 static int hist_comp_params(struct ispstat *hist,
353 struct omap3isp_hist_config *user_cfg)
354 {
355 struct omap3isp_hist_config *cur_cfg = hist->priv;
356 int c;
357
358 if (cur_cfg->cfa != user_cfg->cfa)
359 return 1;
360
361 if (cur_cfg->num_acc_frames != user_cfg->num_acc_frames)
362 return 1;
363
364 if (cur_cfg->hist_bins != user_cfg->hist_bins)
365 return 1;
366
367 for (c = 0; c < OMAP3ISP_HIST_MAX_WG; c++) {
368 if (c == 3 && user_cfg->cfa == OMAP3ISP_HIST_CFA_FOVEONX3)
369 break;
370 else if (cur_cfg->wg[c] != user_cfg->wg[c])
371 return 1;
372 }
373
374 if (cur_cfg->num_regions != user_cfg->num_regions)
375 return 1;
376
377 /* Regions */
378 for (c = 0; c < user_cfg->num_regions; c++) {
379 if (cur_cfg->region[c].h_start != user_cfg->region[c].h_start)
380 return 1;
381 if (cur_cfg->region[c].h_end != user_cfg->region[c].h_end)
382 return 1;
383 if (cur_cfg->region[c].v_start != user_cfg->region[c].v_start)
384 return 1;
385 if (cur_cfg->region[c].v_end != user_cfg->region[c].v_end)
386 return 1;
387 }
388
389 return 0;
390 }
391
392 /*
393 * hist_update_params - Helper function to check and store user given params.
394 * @new_conf: Pointer to user configuration structure.
395 */
hist_set_params(struct ispstat * hist,void * new_conf)396 static void hist_set_params(struct ispstat *hist, void *new_conf)
397 {
398 struct omap3isp_hist_config *user_cfg = new_conf;
399 struct omap3isp_hist_config *cur_cfg = hist->priv;
400
401 if (!hist->configured || hist_comp_params(hist, user_cfg)) {
402 memcpy(cur_cfg, user_cfg, sizeof(*user_cfg));
403 if (user_cfg->num_acc_frames == 0)
404 user_cfg->num_acc_frames = 1;
405 hist->inc_config++;
406 hist->update = 1;
407 /*
408 * User might be asked for a bigger buffer than necessary for
409 * this configuration. In order to return the right amount of
410 * data during buffer request, let's calculate the size here
411 * instead of stick with user_cfg->buf_size.
412 */
413 cur_cfg->buf_size = hist_get_buf_size(cur_cfg);
414
415 }
416 }
417
hist_ioctl(struct v4l2_subdev * sd,unsigned int cmd,void * arg)418 static long hist_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
419 {
420 struct ispstat *stat = v4l2_get_subdevdata(sd);
421
422 switch (cmd) {
423 case VIDIOC_OMAP3ISP_HIST_CFG:
424 return omap3isp_stat_config(stat, arg);
425 case VIDIOC_OMAP3ISP_STAT_REQ:
426 return omap3isp_stat_request_statistics(stat, arg);
427 case VIDIOC_OMAP3ISP_STAT_EN: {
428 int *en = arg;
429 return omap3isp_stat_enable(stat, !!*en);
430 }
431 }
432
433 return -ENOIOCTLCMD;
434
435 }
436
437 static const struct ispstat_ops hist_ops = {
438 .validate_params = hist_validate_params,
439 .set_params = hist_set_params,
440 .setup_regs = hist_setup_regs,
441 .enable = hist_enable,
442 .busy = hist_busy,
443 .buf_process = hist_buf_process,
444 };
445
446 static const struct v4l2_subdev_core_ops hist_subdev_core_ops = {
447 .ioctl = hist_ioctl,
448 .subscribe_event = omap3isp_stat_subscribe_event,
449 .unsubscribe_event = omap3isp_stat_unsubscribe_event,
450 };
451
452 static const struct v4l2_subdev_video_ops hist_subdev_video_ops = {
453 .s_stream = omap3isp_stat_s_stream,
454 };
455
456 static const struct v4l2_subdev_ops hist_subdev_ops = {
457 .core = &hist_subdev_core_ops,
458 .video = &hist_subdev_video_ops,
459 };
460
461 /*
462 * omap3isp_hist_init - Module Initialization.
463 */
omap3isp_hist_init(struct isp_device * isp)464 int omap3isp_hist_init(struct isp_device *isp)
465 {
466 struct ispstat *hist = &isp->isp_hist;
467 struct omap3isp_hist_config *hist_cfg;
468 int ret = -1;
469
470 hist_cfg = devm_kzalloc(isp->dev, sizeof(*hist_cfg), GFP_KERNEL);
471 if (hist_cfg == NULL)
472 return -ENOMEM;
473
474 hist->isp = isp;
475
476 if (HIST_CONFIG_DMA)
477 ret = omap_request_dma(OMAP24XX_DMA_NO_DEVICE, "DMA_ISP_HIST",
478 hist_dma_cb, hist, &hist->dma_ch);
479 if (ret) {
480 if (HIST_CONFIG_DMA)
481 dev_warn(isp->dev, "hist: DMA request channel failed. "
482 "Using PIO only.\n");
483 hist->dma_ch = -1;
484 } else {
485 dev_dbg(isp->dev, "hist: DMA channel = %d\n", hist->dma_ch);
486 hist_dma_config(hist);
487 omap_enable_dma_irq(hist->dma_ch, OMAP_DMA_BLOCK_IRQ);
488 }
489
490 hist->ops = &hist_ops;
491 hist->priv = hist_cfg;
492 hist->event_type = V4L2_EVENT_OMAP3ISP_HIST;
493
494 ret = omap3isp_stat_init(hist, "histogram", &hist_subdev_ops);
495 if (ret) {
496 if (HIST_USING_DMA(hist))
497 omap_free_dma(hist->dma_ch);
498 }
499
500 return ret;
501 }
502
503 /*
504 * omap3isp_hist_cleanup - Module cleanup.
505 */
omap3isp_hist_cleanup(struct isp_device * isp)506 void omap3isp_hist_cleanup(struct isp_device *isp)
507 {
508 if (HIST_USING_DMA(&isp->isp_hist))
509 omap_free_dma(isp->isp_hist.dma_ch);
510 omap3isp_stat_cleanup(&isp->isp_hist);
511 }
512