1 /*
2 * vsp1_bru.c -- R-Car VSP1 Blend ROP Unit
3 *
4 * Copyright (C) 2013 Renesas Corporation
5 *
6 * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 */
13
14 #include <linux/device.h>
15 #include <linux/gfp.h>
16
17 #include <media/v4l2-subdev.h>
18
19 #include "vsp1.h"
20 #include "vsp1_bru.h"
21 #include "vsp1_rwpf.h"
22
23 #define BRU_MIN_SIZE 4U
24 #define BRU_MAX_SIZE 8190U
25
26 /* -----------------------------------------------------------------------------
27 * Device Access
28 */
29
vsp1_bru_read(struct vsp1_bru * bru,u32 reg)30 static inline u32 vsp1_bru_read(struct vsp1_bru *bru, u32 reg)
31 {
32 return vsp1_read(bru->entity.vsp1, reg);
33 }
34
vsp1_bru_write(struct vsp1_bru * bru,u32 reg,u32 data)35 static inline void vsp1_bru_write(struct vsp1_bru *bru, u32 reg, u32 data)
36 {
37 vsp1_write(bru->entity.vsp1, reg, data);
38 }
39
40 /* -----------------------------------------------------------------------------
41 * Controls
42 */
43
bru_s_ctrl(struct v4l2_ctrl * ctrl)44 static int bru_s_ctrl(struct v4l2_ctrl *ctrl)
45 {
46 struct vsp1_bru *bru =
47 container_of(ctrl->handler, struct vsp1_bru, ctrls);
48
49 if (!vsp1_entity_is_streaming(&bru->entity))
50 return 0;
51
52 switch (ctrl->id) {
53 case V4L2_CID_BG_COLOR:
54 vsp1_bru_write(bru, VI6_BRU_VIRRPF_COL, ctrl->val |
55 (0xff << VI6_BRU_VIRRPF_COL_A_SHIFT));
56 break;
57 }
58
59 return 0;
60 }
61
62 static const struct v4l2_ctrl_ops bru_ctrl_ops = {
63 .s_ctrl = bru_s_ctrl,
64 };
65
66 /* -----------------------------------------------------------------------------
67 * V4L2 Subdevice Core Operations
68 */
69
bru_s_stream(struct v4l2_subdev * subdev,int enable)70 static int bru_s_stream(struct v4l2_subdev *subdev, int enable)
71 {
72 struct vsp1_pipeline *pipe = to_vsp1_pipeline(&subdev->entity);
73 struct vsp1_bru *bru = to_bru(subdev);
74 struct v4l2_mbus_framefmt *format;
75 unsigned int flags;
76 unsigned int i;
77 int ret;
78
79 ret = vsp1_entity_set_streaming(&bru->entity, enable);
80 if (ret < 0)
81 return ret;
82
83 if (!enable)
84 return 0;
85
86 format = &bru->entity.formats[BRU_PAD_SOURCE];
87
88 /* The hardware is extremely flexible but we have no userspace API to
89 * expose all the parameters, nor is it clear whether we would have use
90 * cases for all the supported modes. Let's just harcode the parameters
91 * to sane default values for now.
92 */
93
94 /* Disable dithering and enable color data normalization unless the
95 * format at the pipeline output is premultiplied.
96 */
97 flags = pipe->output ? pipe->output->video.format.flags : 0;
98 vsp1_bru_write(bru, VI6_BRU_INCTRL,
99 flags & V4L2_PIX_FMT_FLAG_PREMUL_ALPHA ?
100 0 : VI6_BRU_INCTRL_NRM);
101
102 /* Set the background position to cover the whole output image. */
103 vsp1_bru_write(bru, VI6_BRU_VIRRPF_SIZE,
104 (format->width << VI6_BRU_VIRRPF_SIZE_HSIZE_SHIFT) |
105 (format->height << VI6_BRU_VIRRPF_SIZE_VSIZE_SHIFT));
106 vsp1_bru_write(bru, VI6_BRU_VIRRPF_LOC, 0);
107
108 /* Route BRU input 1 as SRC input to the ROP unit and configure the ROP
109 * unit with a NOP operation to make BRU input 1 available as the
110 * Blend/ROP unit B SRC input.
111 */
112 vsp1_bru_write(bru, VI6_BRU_ROP, VI6_BRU_ROP_DSTSEL_BRUIN(1) |
113 VI6_BRU_ROP_CROP(VI6_ROP_NOP) |
114 VI6_BRU_ROP_AROP(VI6_ROP_NOP));
115
116 for (i = 0; i < 4; ++i) {
117 bool premultiplied = false;
118 u32 ctrl = 0;
119
120 /* Configure all Blend/ROP units corresponding to an enabled BRU
121 * input for alpha blending. Blend/ROP units corresponding to
122 * disabled BRU inputs are used in ROP NOP mode to ignore the
123 * SRC input.
124 */
125 if (bru->inputs[i].rpf) {
126 ctrl |= VI6_BRU_CTRL_RBC;
127
128 premultiplied = bru->inputs[i].rpf->video.format.flags
129 & V4L2_PIX_FMT_FLAG_PREMUL_ALPHA;
130 } else {
131 ctrl |= VI6_BRU_CTRL_CROP(VI6_ROP_NOP)
132 | VI6_BRU_CTRL_AROP(VI6_ROP_NOP);
133 }
134
135 /* Select the virtual RPF as the Blend/ROP unit A DST input to
136 * serve as a background color.
137 */
138 if (i == 0)
139 ctrl |= VI6_BRU_CTRL_DSTSEL_VRPF;
140
141 /* Route BRU inputs 0 to 3 as SRC inputs to Blend/ROP units A to
142 * D in that order. The Blend/ROP unit B SRC is hardwired to the
143 * ROP unit output, the corresponding register bits must be set
144 * to 0.
145 */
146 if (i != 1)
147 ctrl |= VI6_BRU_CTRL_SRCSEL_BRUIN(i);
148
149 vsp1_bru_write(bru, VI6_BRU_CTRL(i), ctrl);
150
151 /* Harcode the blending formula to
152 *
153 * DSTc = DSTc * (1 - SRCa) + SRCc * SRCa
154 * DSTa = DSTa * (1 - SRCa) + SRCa
155 *
156 * when the SRC input isn't premultiplied, and to
157 *
158 * DSTc = DSTc * (1 - SRCa) + SRCc
159 * DSTa = DSTa * (1 - SRCa) + SRCa
160 *
161 * otherwise.
162 */
163 vsp1_bru_write(bru, VI6_BRU_BLD(i),
164 VI6_BRU_BLD_CCMDX_255_SRC_A |
165 (premultiplied ? VI6_BRU_BLD_CCMDY_COEFY :
166 VI6_BRU_BLD_CCMDY_SRC_A) |
167 VI6_BRU_BLD_ACMDX_255_SRC_A |
168 VI6_BRU_BLD_ACMDY_COEFY |
169 (0xff << VI6_BRU_BLD_COEFY_SHIFT));
170 }
171
172 return 0;
173 }
174
175 /* -----------------------------------------------------------------------------
176 * V4L2 Subdevice Pad Operations
177 */
178
179 /*
180 * The BRU can't perform format conversion, all sink and source formats must be
181 * identical. We pick the format on the first sink pad (pad 0) and propagate it
182 * to all other pads.
183 */
184
bru_enum_mbus_code(struct v4l2_subdev * subdev,struct v4l2_subdev_fh * fh,struct v4l2_subdev_mbus_code_enum * code)185 static int bru_enum_mbus_code(struct v4l2_subdev *subdev,
186 struct v4l2_subdev_fh *fh,
187 struct v4l2_subdev_mbus_code_enum *code)
188 {
189 static const unsigned int codes[] = {
190 V4L2_MBUS_FMT_ARGB8888_1X32,
191 V4L2_MBUS_FMT_AYUV8_1X32,
192 };
193 struct v4l2_mbus_framefmt *format;
194
195 if (code->pad == BRU_PAD_SINK(0)) {
196 if (code->index >= ARRAY_SIZE(codes))
197 return -EINVAL;
198
199 code->code = codes[code->index];
200 } else {
201 if (code->index)
202 return -EINVAL;
203
204 format = v4l2_subdev_get_try_format(fh, BRU_PAD_SINK(0));
205 code->code = format->code;
206 }
207
208 return 0;
209 }
210
bru_enum_frame_size(struct v4l2_subdev * subdev,struct v4l2_subdev_fh * fh,struct v4l2_subdev_frame_size_enum * fse)211 static int bru_enum_frame_size(struct v4l2_subdev *subdev,
212 struct v4l2_subdev_fh *fh,
213 struct v4l2_subdev_frame_size_enum *fse)
214 {
215 if (fse->index)
216 return -EINVAL;
217
218 if (fse->code != V4L2_MBUS_FMT_ARGB8888_1X32 &&
219 fse->code != V4L2_MBUS_FMT_AYUV8_1X32)
220 return -EINVAL;
221
222 fse->min_width = BRU_MIN_SIZE;
223 fse->max_width = BRU_MAX_SIZE;
224 fse->min_height = BRU_MIN_SIZE;
225 fse->max_height = BRU_MAX_SIZE;
226
227 return 0;
228 }
229
bru_get_compose(struct vsp1_bru * bru,struct v4l2_subdev_fh * fh,unsigned int pad,u32 which)230 static struct v4l2_rect *bru_get_compose(struct vsp1_bru *bru,
231 struct v4l2_subdev_fh *fh,
232 unsigned int pad, u32 which)
233 {
234 switch (which) {
235 case V4L2_SUBDEV_FORMAT_TRY:
236 return v4l2_subdev_get_try_crop(fh, pad);
237 case V4L2_SUBDEV_FORMAT_ACTIVE:
238 return &bru->inputs[pad].compose;
239 default:
240 return NULL;
241 }
242 }
243
bru_get_format(struct v4l2_subdev * subdev,struct v4l2_subdev_fh * fh,struct v4l2_subdev_format * fmt)244 static int bru_get_format(struct v4l2_subdev *subdev, struct v4l2_subdev_fh *fh,
245 struct v4l2_subdev_format *fmt)
246 {
247 struct vsp1_bru *bru = to_bru(subdev);
248
249 fmt->format = *vsp1_entity_get_pad_format(&bru->entity, fh, fmt->pad,
250 fmt->which);
251
252 return 0;
253 }
254
bru_try_format(struct vsp1_bru * bru,struct v4l2_subdev_fh * fh,unsigned int pad,struct v4l2_mbus_framefmt * fmt,enum v4l2_subdev_format_whence which)255 static void bru_try_format(struct vsp1_bru *bru, struct v4l2_subdev_fh *fh,
256 unsigned int pad, struct v4l2_mbus_framefmt *fmt,
257 enum v4l2_subdev_format_whence which)
258 {
259 struct v4l2_mbus_framefmt *format;
260
261 switch (pad) {
262 case BRU_PAD_SINK(0):
263 /* Default to YUV if the requested format is not supported. */
264 if (fmt->code != V4L2_MBUS_FMT_ARGB8888_1X32 &&
265 fmt->code != V4L2_MBUS_FMT_AYUV8_1X32)
266 fmt->code = V4L2_MBUS_FMT_AYUV8_1X32;
267 break;
268
269 default:
270 /* The BRU can't perform format conversion. */
271 format = vsp1_entity_get_pad_format(&bru->entity, fh,
272 BRU_PAD_SINK(0), which);
273 fmt->code = format->code;
274 break;
275 }
276
277 fmt->width = clamp(fmt->width, BRU_MIN_SIZE, BRU_MAX_SIZE);
278 fmt->height = clamp(fmt->height, BRU_MIN_SIZE, BRU_MAX_SIZE);
279 fmt->field = V4L2_FIELD_NONE;
280 fmt->colorspace = V4L2_COLORSPACE_SRGB;
281 }
282
bru_set_format(struct v4l2_subdev * subdev,struct v4l2_subdev_fh * fh,struct v4l2_subdev_format * fmt)283 static int bru_set_format(struct v4l2_subdev *subdev, struct v4l2_subdev_fh *fh,
284 struct v4l2_subdev_format *fmt)
285 {
286 struct vsp1_bru *bru = to_bru(subdev);
287 struct v4l2_mbus_framefmt *format;
288
289 bru_try_format(bru, fh, fmt->pad, &fmt->format, fmt->which);
290
291 format = vsp1_entity_get_pad_format(&bru->entity, fh, fmt->pad,
292 fmt->which);
293 *format = fmt->format;
294
295 /* Reset the compose rectangle */
296 if (fmt->pad != BRU_PAD_SOURCE) {
297 struct v4l2_rect *compose;
298
299 compose = bru_get_compose(bru, fh, fmt->pad, fmt->which);
300 compose->left = 0;
301 compose->top = 0;
302 compose->width = format->width;
303 compose->height = format->height;
304 }
305
306 /* Propagate the format code to all pads */
307 if (fmt->pad == BRU_PAD_SINK(0)) {
308 unsigned int i;
309
310 for (i = 0; i <= BRU_PAD_SOURCE; ++i) {
311 format = vsp1_entity_get_pad_format(&bru->entity, fh,
312 i, fmt->which);
313 format->code = fmt->format.code;
314 }
315 }
316
317 return 0;
318 }
319
bru_get_selection(struct v4l2_subdev * subdev,struct v4l2_subdev_fh * fh,struct v4l2_subdev_selection * sel)320 static int bru_get_selection(struct v4l2_subdev *subdev,
321 struct v4l2_subdev_fh *fh,
322 struct v4l2_subdev_selection *sel)
323 {
324 struct vsp1_bru *bru = to_bru(subdev);
325
326 if (sel->pad == BRU_PAD_SOURCE)
327 return -EINVAL;
328
329 switch (sel->target) {
330 case V4L2_SEL_TGT_COMPOSE_BOUNDS:
331 sel->r.left = 0;
332 sel->r.top = 0;
333 sel->r.width = BRU_MAX_SIZE;
334 sel->r.height = BRU_MAX_SIZE;
335 return 0;
336
337 case V4L2_SEL_TGT_COMPOSE:
338 sel->r = *bru_get_compose(bru, fh, sel->pad, sel->which);
339 return 0;
340
341 default:
342 return -EINVAL;
343 }
344 }
345
bru_set_selection(struct v4l2_subdev * subdev,struct v4l2_subdev_fh * fh,struct v4l2_subdev_selection * sel)346 static int bru_set_selection(struct v4l2_subdev *subdev,
347 struct v4l2_subdev_fh *fh,
348 struct v4l2_subdev_selection *sel)
349 {
350 struct vsp1_bru *bru = to_bru(subdev);
351 struct v4l2_mbus_framefmt *format;
352 struct v4l2_rect *compose;
353
354 if (sel->pad == BRU_PAD_SOURCE)
355 return -EINVAL;
356
357 if (sel->target != V4L2_SEL_TGT_COMPOSE)
358 return -EINVAL;
359
360 /* The compose rectangle top left corner must be inside the output
361 * frame.
362 */
363 format = vsp1_entity_get_pad_format(&bru->entity, fh, BRU_PAD_SOURCE,
364 sel->which);
365 sel->r.left = clamp_t(unsigned int, sel->r.left, 0, format->width - 1);
366 sel->r.top = clamp_t(unsigned int, sel->r.top, 0, format->height - 1);
367
368 /* Scaling isn't supported, the compose rectangle size must be identical
369 * to the sink format size.
370 */
371 format = vsp1_entity_get_pad_format(&bru->entity, fh, sel->pad,
372 sel->which);
373 sel->r.width = format->width;
374 sel->r.height = format->height;
375
376 compose = bru_get_compose(bru, fh, sel->pad, sel->which);
377 *compose = sel->r;
378
379 return 0;
380 }
381
382 /* -----------------------------------------------------------------------------
383 * V4L2 Subdevice Operations
384 */
385
386 static struct v4l2_subdev_video_ops bru_video_ops = {
387 .s_stream = bru_s_stream,
388 };
389
390 static struct v4l2_subdev_pad_ops bru_pad_ops = {
391 .enum_mbus_code = bru_enum_mbus_code,
392 .enum_frame_size = bru_enum_frame_size,
393 .get_fmt = bru_get_format,
394 .set_fmt = bru_set_format,
395 .get_selection = bru_get_selection,
396 .set_selection = bru_set_selection,
397 };
398
399 static struct v4l2_subdev_ops bru_ops = {
400 .video = &bru_video_ops,
401 .pad = &bru_pad_ops,
402 };
403
404 /* -----------------------------------------------------------------------------
405 * Initialization and Cleanup
406 */
407
vsp1_bru_create(struct vsp1_device * vsp1)408 struct vsp1_bru *vsp1_bru_create(struct vsp1_device *vsp1)
409 {
410 struct v4l2_subdev *subdev;
411 struct vsp1_bru *bru;
412 int ret;
413
414 bru = devm_kzalloc(vsp1->dev, sizeof(*bru), GFP_KERNEL);
415 if (bru == NULL)
416 return ERR_PTR(-ENOMEM);
417
418 bru->entity.type = VSP1_ENTITY_BRU;
419
420 ret = vsp1_entity_init(vsp1, &bru->entity, 5);
421 if (ret < 0)
422 return ERR_PTR(ret);
423
424 /* Initialize the V4L2 subdev. */
425 subdev = &bru->entity.subdev;
426 v4l2_subdev_init(subdev, &bru_ops);
427
428 subdev->entity.ops = &vsp1_media_ops;
429 subdev->internal_ops = &vsp1_subdev_internal_ops;
430 snprintf(subdev->name, sizeof(subdev->name), "%s bru",
431 dev_name(vsp1->dev));
432 v4l2_set_subdevdata(subdev, bru);
433 subdev->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
434
435 vsp1_entity_init_formats(subdev, NULL);
436
437 /* Initialize the control handler. */
438 v4l2_ctrl_handler_init(&bru->ctrls, 1);
439 v4l2_ctrl_new_std(&bru->ctrls, &bru_ctrl_ops, V4L2_CID_BG_COLOR,
440 0, 0xffffff, 1, 0);
441
442 bru->entity.subdev.ctrl_handler = &bru->ctrls;
443
444 if (bru->ctrls.error) {
445 dev_err(vsp1->dev, "bru: failed to initialize controls\n");
446 ret = bru->ctrls.error;
447 vsp1_entity_destroy(&bru->entity);
448 return ERR_PTR(ret);
449 }
450
451 return bru;
452 }
453