1 /* Driver for Realtek PCI-Express card reader
2 *
3 * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2, or (at your option) any
8 * later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, see <http://www.gnu.org/licenses/>.
17 *
18 * Author:
19 * Wei WANG <wei_wang@realsil.com.cn>
20 * Roger Tseng <rogerable@realtek.com>
21 */
22
23 #include <linux/module.h>
24 #include <linux/delay.h>
25 #include <linux/mfd/rtsx_pci.h>
26
27 #include "rtsx_pcr.h"
28
rts5227_fill_driving(struct rtsx_pcr * pcr,u8 voltage)29 static void rts5227_fill_driving(struct rtsx_pcr *pcr, u8 voltage)
30 {
31 u8 driving_3v3[4][3] = {
32 {0x13, 0x13, 0x13},
33 {0x96, 0x96, 0x96},
34 {0x7F, 0x7F, 0x7F},
35 {0x96, 0x96, 0x96},
36 };
37 u8 driving_1v8[4][3] = {
38 {0x99, 0x99, 0x99},
39 {0xAA, 0xAA, 0xAA},
40 {0xFE, 0xFE, 0xFE},
41 {0xB3, 0xB3, 0xB3},
42 };
43 u8 (*driving)[3], drive_sel;
44
45 if (voltage == OUTPUT_3V3) {
46 driving = driving_3v3;
47 drive_sel = pcr->sd30_drive_sel_3v3;
48 } else {
49 driving = driving_1v8;
50 drive_sel = pcr->sd30_drive_sel_1v8;
51 }
52
53 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_CLK_DRIVE_SEL,
54 0xFF, driving[drive_sel][0]);
55 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_CMD_DRIVE_SEL,
56 0xFF, driving[drive_sel][1]);
57 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_DAT_DRIVE_SEL,
58 0xFF, driving[drive_sel][2]);
59 }
60
rts5227_fetch_vendor_settings(struct rtsx_pcr * pcr)61 static void rts5227_fetch_vendor_settings(struct rtsx_pcr *pcr)
62 {
63 u32 reg;
64
65 rtsx_pci_read_config_dword(pcr, PCR_SETTING_REG1, ®);
66 dev_dbg(&(pcr->pci->dev), "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg);
67
68 if (!rtsx_vendor_setting_valid(reg))
69 return;
70
71 pcr->aspm_en = rtsx_reg_to_aspm(reg);
72 pcr->sd30_drive_sel_1v8 = rtsx_reg_to_sd30_drive_sel_1v8(reg);
73 pcr->card_drive_sel &= 0x3F;
74 pcr->card_drive_sel |= rtsx_reg_to_card_drive_sel(reg);
75
76 rtsx_pci_read_config_dword(pcr, PCR_SETTING_REG2, ®);
77 dev_dbg(&(pcr->pci->dev), "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG2, reg);
78 pcr->sd30_drive_sel_3v3 = rtsx_reg_to_sd30_drive_sel_3v3(reg);
79 if (rtsx_reg_check_reverse_socket(reg))
80 pcr->flags |= PCR_REVERSE_SOCKET;
81 }
82
rts5227_force_power_down(struct rtsx_pcr * pcr,u8 pm_state)83 static void rts5227_force_power_down(struct rtsx_pcr *pcr, u8 pm_state)
84 {
85 /* Set relink_time to 0 */
86 rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 1, 0xFF, 0);
87 rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 2, 0xFF, 0);
88 rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 3, 0x01, 0);
89
90 if (pm_state == HOST_ENTER_S3)
91 rtsx_pci_write_register(pcr, PM_CTRL3, 0x10, 0x10);
92
93 rtsx_pci_write_register(pcr, FPDCTL, 0x03, 0x03);
94 }
95
rts5227_extra_init_hw(struct rtsx_pcr * pcr)96 static int rts5227_extra_init_hw(struct rtsx_pcr *pcr)
97 {
98 u16 cap;
99
100 rtsx_pci_init_cmd(pcr);
101
102 /* Configure GPIO as output */
103 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, GPIO_CTL, 0x02, 0x02);
104 /* Reset ASPM state to default value */
105 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, ASPM_FORCE_CTL, 0x3F, 0);
106 /* Switch LDO3318 source from DV33 to card_3v3 */
107 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x00);
108 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x01);
109 /* LED shine disabled, set initial shine cycle period */
110 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, OLT_LED_CTL, 0x0F, 0x02);
111 /* Configure LTR */
112 pcie_capability_read_word(pcr->pci, PCI_EXP_DEVCTL2, &cap);
113 if (cap & PCI_EXP_DEVCTL2_LTR_EN)
114 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LTR_CTL, 0xFF, 0xA3);
115 /* Configure OBFF */
116 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, OBFF_CFG, 0x03, 0x03);
117 /* Configure driving */
118 rts5227_fill_driving(pcr, OUTPUT_3V3);
119 /* Configure force_clock_req */
120 if (pcr->flags & PCR_REVERSE_SOCKET)
121 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
122 AUTOLOAD_CFG_BASE + 3, 0xB8, 0xB8);
123 else
124 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
125 AUTOLOAD_CFG_BASE + 3, 0xB8, 0x88);
126 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PM_CTRL3, 0x10, 0x00);
127
128 return rtsx_pci_send_cmd(pcr, 100);
129 }
130
rts5227_optimize_phy(struct rtsx_pcr * pcr)131 static int rts5227_optimize_phy(struct rtsx_pcr *pcr)
132 {
133 /* Optimize RX sensitivity */
134 return rtsx_pci_write_phy_register(pcr, 0x00, 0xBA42);
135 }
136
rts5227_turn_on_led(struct rtsx_pcr * pcr)137 static int rts5227_turn_on_led(struct rtsx_pcr *pcr)
138 {
139 return rtsx_pci_write_register(pcr, GPIO_CTL, 0x02, 0x02);
140 }
141
rts5227_turn_off_led(struct rtsx_pcr * pcr)142 static int rts5227_turn_off_led(struct rtsx_pcr *pcr)
143 {
144 return rtsx_pci_write_register(pcr, GPIO_CTL, 0x02, 0x00);
145 }
146
rts5227_enable_auto_blink(struct rtsx_pcr * pcr)147 static int rts5227_enable_auto_blink(struct rtsx_pcr *pcr)
148 {
149 return rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x08, 0x08);
150 }
151
rts5227_disable_auto_blink(struct rtsx_pcr * pcr)152 static int rts5227_disable_auto_blink(struct rtsx_pcr *pcr)
153 {
154 return rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x08, 0x00);
155 }
156
rts5227_card_power_on(struct rtsx_pcr * pcr,int card)157 static int rts5227_card_power_on(struct rtsx_pcr *pcr, int card)
158 {
159 int err;
160
161 rtsx_pci_init_cmd(pcr);
162 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
163 SD_POWER_MASK, SD_PARTIAL_POWER_ON);
164 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
165 LDO3318_PWR_MASK, 0x02);
166 err = rtsx_pci_send_cmd(pcr, 100);
167 if (err < 0)
168 return err;
169
170 /* To avoid too large in-rush current */
171 udelay(150);
172
173 rtsx_pci_init_cmd(pcr);
174 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
175 SD_POWER_MASK, SD_POWER_ON);
176 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
177 LDO3318_PWR_MASK, 0x06);
178 err = rtsx_pci_send_cmd(pcr, 100);
179 if (err < 0)
180 return err;
181
182 return 0;
183 }
184
rts5227_card_power_off(struct rtsx_pcr * pcr,int card)185 static int rts5227_card_power_off(struct rtsx_pcr *pcr, int card)
186 {
187 rtsx_pci_init_cmd(pcr);
188 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
189 SD_POWER_MASK | PMOS_STRG_MASK,
190 SD_POWER_OFF | PMOS_STRG_400mA);
191 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
192 LDO3318_PWR_MASK, 0X00);
193 return rtsx_pci_send_cmd(pcr, 100);
194 }
195
rts5227_switch_output_voltage(struct rtsx_pcr * pcr,u8 voltage)196 static int rts5227_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
197 {
198 int err;
199
200 if (voltage == OUTPUT_3V3) {
201 err = rtsx_pci_write_phy_register(pcr, 0x08, 0x4FC0 | 0x24);
202 if (err < 0)
203 return err;
204 } else if (voltage == OUTPUT_1V8) {
205 err = rtsx_pci_write_phy_register(pcr, 0x11, 0x3C02);
206 if (err < 0)
207 return err;
208 err = rtsx_pci_write_phy_register(pcr, 0x08, 0x4C80 | 0x24);
209 if (err < 0)
210 return err;
211 } else {
212 return -EINVAL;
213 }
214
215 /* set pad drive */
216 rtsx_pci_init_cmd(pcr);
217 rts5227_fill_driving(pcr, voltage);
218 return rtsx_pci_send_cmd(pcr, 100);
219 }
220
221 static const struct pcr_ops rts5227_pcr_ops = {
222 .fetch_vendor_settings = rts5227_fetch_vendor_settings,
223 .extra_init_hw = rts5227_extra_init_hw,
224 .optimize_phy = rts5227_optimize_phy,
225 .turn_on_led = rts5227_turn_on_led,
226 .turn_off_led = rts5227_turn_off_led,
227 .enable_auto_blink = rts5227_enable_auto_blink,
228 .disable_auto_blink = rts5227_disable_auto_blink,
229 .card_power_on = rts5227_card_power_on,
230 .card_power_off = rts5227_card_power_off,
231 .switch_output_voltage = rts5227_switch_output_voltage,
232 .cd_deglitch = NULL,
233 .conv_clk_and_div_n = NULL,
234 .force_power_down = rts5227_force_power_down,
235 };
236
237 /* SD Pull Control Enable:
238 * SD_DAT[3:0] ==> pull up
239 * SD_CD ==> pull up
240 * SD_WP ==> pull up
241 * SD_CMD ==> pull up
242 * SD_CLK ==> pull down
243 */
244 static const u32 rts5227_sd_pull_ctl_enable_tbl[] = {
245 RTSX_REG_PAIR(CARD_PULL_CTL2, 0xAA),
246 RTSX_REG_PAIR(CARD_PULL_CTL3, 0xE9),
247 0,
248 };
249
250 /* SD Pull Control Disable:
251 * SD_DAT[3:0] ==> pull down
252 * SD_CD ==> pull up
253 * SD_WP ==> pull down
254 * SD_CMD ==> pull down
255 * SD_CLK ==> pull down
256 */
257 static const u32 rts5227_sd_pull_ctl_disable_tbl[] = {
258 RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55),
259 RTSX_REG_PAIR(CARD_PULL_CTL3, 0xD5),
260 0,
261 };
262
263 /* MS Pull Control Enable:
264 * MS CD ==> pull up
265 * others ==> pull down
266 */
267 static const u32 rts5227_ms_pull_ctl_enable_tbl[] = {
268 RTSX_REG_PAIR(CARD_PULL_CTL5, 0x55),
269 RTSX_REG_PAIR(CARD_PULL_CTL6, 0x15),
270 0,
271 };
272
273 /* MS Pull Control Disable:
274 * MS CD ==> pull up
275 * others ==> pull down
276 */
277 static const u32 rts5227_ms_pull_ctl_disable_tbl[] = {
278 RTSX_REG_PAIR(CARD_PULL_CTL5, 0x55),
279 RTSX_REG_PAIR(CARD_PULL_CTL6, 0x15),
280 0,
281 };
282
rts5227_init_params(struct rtsx_pcr * pcr)283 void rts5227_init_params(struct rtsx_pcr *pcr)
284 {
285 pcr->extra_caps = EXTRA_CAPS_SD_SDR50 | EXTRA_CAPS_SD_SDR104;
286 pcr->num_slots = 2;
287 pcr->ops = &rts5227_pcr_ops;
288
289 pcr->flags = 0;
290 pcr->card_drive_sel = RTSX_CARD_DRIVE_DEFAULT;
291 pcr->sd30_drive_sel_1v8 = CFG_DRIVER_TYPE_B;
292 pcr->sd30_drive_sel_3v3 = CFG_DRIVER_TYPE_B;
293 pcr->aspm_en = ASPM_L1_EN;
294 pcr->tx_initial_phase = SET_CLOCK_PHASE(27, 27, 15);
295 pcr->rx_initial_phase = SET_CLOCK_PHASE(30, 7, 7);
296
297 pcr->sd_pull_ctl_enable_tbl = rts5227_sd_pull_ctl_enable_tbl;
298 pcr->sd_pull_ctl_disable_tbl = rts5227_sd_pull_ctl_disable_tbl;
299 pcr->ms_pull_ctl_enable_tbl = rts5227_ms_pull_ctl_enable_tbl;
300 pcr->ms_pull_ctl_disable_tbl = rts5227_ms_pull_ctl_disable_tbl;
301 }
302