1 /*
2 * Synopsys DesignWare Multimedia Card Interface driver
3 * (Based on NXP driver for lpc 31xx)
4 *
5 * Copyright (C) 2009 NXP Semiconductors
6 * Copyright (C) 2009, 2010 Imagination Technologies Ltd.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 */
13
14 #include <linux/blkdev.h>
15 #include <linux/clk.h>
16 #include <linux/debugfs.h>
17 #include <linux/device.h>
18 #include <linux/dma-mapping.h>
19 #include <linux/err.h>
20 #include <linux/init.h>
21 #include <linux/interrupt.h>
22 #include <linux/ioport.h>
23 #include <linux/module.h>
24 #include <linux/platform_device.h>
25 #include <linux/seq_file.h>
26 #include <linux/slab.h>
27 #include <linux/stat.h>
28 #include <linux/delay.h>
29 #include <linux/irq.h>
30 #include <linux/mmc/host.h>
31 #include <linux/mmc/mmc.h>
32 #include <linux/mmc/sd.h>
33 #include <linux/mmc/sdio.h>
34 #include <linux/mmc/dw_mmc.h>
35 #include <linux/bitops.h>
36 #include <linux/regulator/consumer.h>
37 #include <linux/workqueue.h>
38 #include <linux/of.h>
39 #include <linux/of_gpio.h>
40 #include <linux/mmc/slot-gpio.h>
41
42 #include "dw_mmc.h"
43
44 /* Common flag combinations */
45 #define DW_MCI_DATA_ERROR_FLAGS (SDMMC_INT_DRTO | SDMMC_INT_DCRC | \
46 SDMMC_INT_HTO | SDMMC_INT_SBE | \
47 SDMMC_INT_EBE)
48 #define DW_MCI_CMD_ERROR_FLAGS (SDMMC_INT_RTO | SDMMC_INT_RCRC | \
49 SDMMC_INT_RESP_ERR)
50 #define DW_MCI_ERROR_FLAGS (DW_MCI_DATA_ERROR_FLAGS | \
51 DW_MCI_CMD_ERROR_FLAGS | SDMMC_INT_HLE)
52 #define DW_MCI_SEND_STATUS 1
53 #define DW_MCI_RECV_STATUS 2
54 #define DW_MCI_DMA_THRESHOLD 16
55
56 #define DW_MCI_FREQ_MAX 200000000 /* unit: HZ */
57 #define DW_MCI_FREQ_MIN 400000 /* unit: HZ */
58
59 #ifdef CONFIG_MMC_DW_IDMAC
60 #define IDMAC_INT_CLR (SDMMC_IDMAC_INT_AI | SDMMC_IDMAC_INT_NI | \
61 SDMMC_IDMAC_INT_CES | SDMMC_IDMAC_INT_DU | \
62 SDMMC_IDMAC_INT_FBE | SDMMC_IDMAC_INT_RI | \
63 SDMMC_IDMAC_INT_TI)
64
65 struct idmac_desc {
66 u32 des0; /* Control Descriptor */
67 #define IDMAC_DES0_DIC BIT(1)
68 #define IDMAC_DES0_LD BIT(2)
69 #define IDMAC_DES0_FD BIT(3)
70 #define IDMAC_DES0_CH BIT(4)
71 #define IDMAC_DES0_ER BIT(5)
72 #define IDMAC_DES0_CES BIT(30)
73 #define IDMAC_DES0_OWN BIT(31)
74
75 u32 des1; /* Buffer sizes */
76 #define IDMAC_SET_BUFFER1_SIZE(d, s) \
77 ((d)->des1 = ((d)->des1 & 0x03ffe000) | ((s) & 0x1fff))
78
79 u32 des2; /* buffer 1 physical address */
80
81 u32 des3; /* buffer 2 physical address */
82 };
83 #endif /* CONFIG_MMC_DW_IDMAC */
84
85 static bool dw_mci_reset(struct dw_mci *host);
86
87 #if defined(CONFIG_DEBUG_FS)
dw_mci_req_show(struct seq_file * s,void * v)88 static int dw_mci_req_show(struct seq_file *s, void *v)
89 {
90 struct dw_mci_slot *slot = s->private;
91 struct mmc_request *mrq;
92 struct mmc_command *cmd;
93 struct mmc_command *stop;
94 struct mmc_data *data;
95
96 /* Make sure we get a consistent snapshot */
97 spin_lock_bh(&slot->host->lock);
98 mrq = slot->mrq;
99
100 if (mrq) {
101 cmd = mrq->cmd;
102 data = mrq->data;
103 stop = mrq->stop;
104
105 if (cmd)
106 seq_printf(s,
107 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
108 cmd->opcode, cmd->arg, cmd->flags,
109 cmd->resp[0], cmd->resp[1], cmd->resp[2],
110 cmd->resp[2], cmd->error);
111 if (data)
112 seq_printf(s, "DATA %u / %u * %u flg %x err %d\n",
113 data->bytes_xfered, data->blocks,
114 data->blksz, data->flags, data->error);
115 if (stop)
116 seq_printf(s,
117 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
118 stop->opcode, stop->arg, stop->flags,
119 stop->resp[0], stop->resp[1], stop->resp[2],
120 stop->resp[2], stop->error);
121 }
122
123 spin_unlock_bh(&slot->host->lock);
124
125 return 0;
126 }
127
dw_mci_req_open(struct inode * inode,struct file * file)128 static int dw_mci_req_open(struct inode *inode, struct file *file)
129 {
130 return single_open(file, dw_mci_req_show, inode->i_private);
131 }
132
133 static const struct file_operations dw_mci_req_fops = {
134 .owner = THIS_MODULE,
135 .open = dw_mci_req_open,
136 .read = seq_read,
137 .llseek = seq_lseek,
138 .release = single_release,
139 };
140
dw_mci_regs_show(struct seq_file * s,void * v)141 static int dw_mci_regs_show(struct seq_file *s, void *v)
142 {
143 seq_printf(s, "STATUS:\t0x%08x\n", SDMMC_STATUS);
144 seq_printf(s, "RINTSTS:\t0x%08x\n", SDMMC_RINTSTS);
145 seq_printf(s, "CMD:\t0x%08x\n", SDMMC_CMD);
146 seq_printf(s, "CTRL:\t0x%08x\n", SDMMC_CTRL);
147 seq_printf(s, "INTMASK:\t0x%08x\n", SDMMC_INTMASK);
148 seq_printf(s, "CLKENA:\t0x%08x\n", SDMMC_CLKENA);
149
150 return 0;
151 }
152
dw_mci_regs_open(struct inode * inode,struct file * file)153 static int dw_mci_regs_open(struct inode *inode, struct file *file)
154 {
155 return single_open(file, dw_mci_regs_show, inode->i_private);
156 }
157
158 static const struct file_operations dw_mci_regs_fops = {
159 .owner = THIS_MODULE,
160 .open = dw_mci_regs_open,
161 .read = seq_read,
162 .llseek = seq_lseek,
163 .release = single_release,
164 };
165
dw_mci_init_debugfs(struct dw_mci_slot * slot)166 static void dw_mci_init_debugfs(struct dw_mci_slot *slot)
167 {
168 struct mmc_host *mmc = slot->mmc;
169 struct dw_mci *host = slot->host;
170 struct dentry *root;
171 struct dentry *node;
172
173 root = mmc->debugfs_root;
174 if (!root)
175 return;
176
177 node = debugfs_create_file("regs", S_IRUSR, root, host,
178 &dw_mci_regs_fops);
179 if (!node)
180 goto err;
181
182 node = debugfs_create_file("req", S_IRUSR, root, slot,
183 &dw_mci_req_fops);
184 if (!node)
185 goto err;
186
187 node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state);
188 if (!node)
189 goto err;
190
191 node = debugfs_create_x32("pending_events", S_IRUSR, root,
192 (u32 *)&host->pending_events);
193 if (!node)
194 goto err;
195
196 node = debugfs_create_x32("completed_events", S_IRUSR, root,
197 (u32 *)&host->completed_events);
198 if (!node)
199 goto err;
200
201 return;
202
203 err:
204 dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n");
205 }
206 #endif /* defined(CONFIG_DEBUG_FS) */
207
208 static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg);
209
dw_mci_prepare_command(struct mmc_host * mmc,struct mmc_command * cmd)210 static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command *cmd)
211 {
212 struct mmc_data *data;
213 struct dw_mci_slot *slot = mmc_priv(mmc);
214 struct dw_mci *host = slot->host;
215 const struct dw_mci_drv_data *drv_data = slot->host->drv_data;
216 u32 cmdr;
217 cmd->error = -EINPROGRESS;
218
219 cmdr = cmd->opcode;
220
221 if (cmd->opcode == MMC_STOP_TRANSMISSION ||
222 cmd->opcode == MMC_GO_IDLE_STATE ||
223 cmd->opcode == MMC_GO_INACTIVE_STATE ||
224 (cmd->opcode == SD_IO_RW_DIRECT &&
225 ((cmd->arg >> 9) & 0x1FFFF) == SDIO_CCCR_ABORT))
226 cmdr |= SDMMC_CMD_STOP;
227 else if (cmd->opcode != MMC_SEND_STATUS && cmd->data)
228 cmdr |= SDMMC_CMD_PRV_DAT_WAIT;
229
230 if (cmd->opcode == SD_SWITCH_VOLTAGE) {
231 u32 clk_en_a;
232
233 /* Special bit makes CMD11 not die */
234 cmdr |= SDMMC_CMD_VOLT_SWITCH;
235
236 /* Change state to continue to handle CMD11 weirdness */
237 WARN_ON(slot->host->state != STATE_SENDING_CMD);
238 slot->host->state = STATE_SENDING_CMD11;
239
240 /*
241 * We need to disable low power mode (automatic clock stop)
242 * while doing voltage switch so we don't confuse the card,
243 * since stopping the clock is a specific part of the UHS
244 * voltage change dance.
245 *
246 * Note that low power mode (SDMMC_CLKEN_LOW_PWR) will be
247 * unconditionally turned back on in dw_mci_setup_bus() if it's
248 * ever called with a non-zero clock. That shouldn't happen
249 * until the voltage change is all done.
250 */
251 clk_en_a = mci_readl(host, CLKENA);
252 clk_en_a &= ~(SDMMC_CLKEN_LOW_PWR << slot->id);
253 mci_writel(host, CLKENA, clk_en_a);
254 mci_send_cmd(slot, SDMMC_CMD_UPD_CLK |
255 SDMMC_CMD_PRV_DAT_WAIT, 0);
256 }
257
258 if (cmd->flags & MMC_RSP_PRESENT) {
259 /* We expect a response, so set this bit */
260 cmdr |= SDMMC_CMD_RESP_EXP;
261 if (cmd->flags & MMC_RSP_136)
262 cmdr |= SDMMC_CMD_RESP_LONG;
263 }
264
265 if (cmd->flags & MMC_RSP_CRC)
266 cmdr |= SDMMC_CMD_RESP_CRC;
267
268 data = cmd->data;
269 if (data) {
270 cmdr |= SDMMC_CMD_DAT_EXP;
271 if (data->flags & MMC_DATA_STREAM)
272 cmdr |= SDMMC_CMD_STRM_MODE;
273 if (data->flags & MMC_DATA_WRITE)
274 cmdr |= SDMMC_CMD_DAT_WR;
275 }
276
277 if (drv_data && drv_data->prepare_command)
278 drv_data->prepare_command(slot->host, &cmdr);
279
280 return cmdr;
281 }
282
dw_mci_prep_stop_abort(struct dw_mci * host,struct mmc_command * cmd)283 static u32 dw_mci_prep_stop_abort(struct dw_mci *host, struct mmc_command *cmd)
284 {
285 struct mmc_command *stop;
286 u32 cmdr;
287
288 if (!cmd->data)
289 return 0;
290
291 stop = &host->stop_abort;
292 cmdr = cmd->opcode;
293 memset(stop, 0, sizeof(struct mmc_command));
294
295 if (cmdr == MMC_READ_SINGLE_BLOCK ||
296 cmdr == MMC_READ_MULTIPLE_BLOCK ||
297 cmdr == MMC_WRITE_BLOCK ||
298 cmdr == MMC_WRITE_MULTIPLE_BLOCK) {
299 stop->opcode = MMC_STOP_TRANSMISSION;
300 stop->arg = 0;
301 stop->flags = MMC_RSP_R1B | MMC_CMD_AC;
302 } else if (cmdr == SD_IO_RW_EXTENDED) {
303 stop->opcode = SD_IO_RW_DIRECT;
304 stop->arg |= (1 << 31) | (0 << 28) | (SDIO_CCCR_ABORT << 9) |
305 ((cmd->arg >> 28) & 0x7);
306 stop->flags = MMC_RSP_SPI_R5 | MMC_RSP_R5 | MMC_CMD_AC;
307 } else {
308 return 0;
309 }
310
311 cmdr = stop->opcode | SDMMC_CMD_STOP |
312 SDMMC_CMD_RESP_CRC | SDMMC_CMD_RESP_EXP;
313
314 return cmdr;
315 }
316
dw_mci_start_command(struct dw_mci * host,struct mmc_command * cmd,u32 cmd_flags)317 static void dw_mci_start_command(struct dw_mci *host,
318 struct mmc_command *cmd, u32 cmd_flags)
319 {
320 host->cmd = cmd;
321 dev_vdbg(host->dev,
322 "start command: ARGR=0x%08x CMDR=0x%08x\n",
323 cmd->arg, cmd_flags);
324
325 mci_writel(host, CMDARG, cmd->arg);
326 wmb();
327
328 mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START);
329 }
330
send_stop_abort(struct dw_mci * host,struct mmc_data * data)331 static inline void send_stop_abort(struct dw_mci *host, struct mmc_data *data)
332 {
333 struct mmc_command *stop = data->stop ? data->stop : &host->stop_abort;
334 dw_mci_start_command(host, stop, host->stop_cmdr);
335 }
336
337 /* DMA interface functions */
dw_mci_stop_dma(struct dw_mci * host)338 static void dw_mci_stop_dma(struct dw_mci *host)
339 {
340 if (host->using_dma) {
341 host->dma_ops->stop(host);
342 host->dma_ops->cleanup(host);
343 }
344
345 /* Data transfer was stopped by the interrupt handler */
346 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
347 }
348
dw_mci_get_dma_dir(struct mmc_data * data)349 static int dw_mci_get_dma_dir(struct mmc_data *data)
350 {
351 if (data->flags & MMC_DATA_WRITE)
352 return DMA_TO_DEVICE;
353 else
354 return DMA_FROM_DEVICE;
355 }
356
357 #ifdef CONFIG_MMC_DW_IDMAC
dw_mci_dma_cleanup(struct dw_mci * host)358 static void dw_mci_dma_cleanup(struct dw_mci *host)
359 {
360 struct mmc_data *data = host->data;
361
362 if (data)
363 if (!data->host_cookie)
364 dma_unmap_sg(host->dev,
365 data->sg,
366 data->sg_len,
367 dw_mci_get_dma_dir(data));
368 }
369
dw_mci_idmac_reset(struct dw_mci * host)370 static void dw_mci_idmac_reset(struct dw_mci *host)
371 {
372 u32 bmod = mci_readl(host, BMOD);
373 /* Software reset of DMA */
374 bmod |= SDMMC_IDMAC_SWRESET;
375 mci_writel(host, BMOD, bmod);
376 }
377
dw_mci_idmac_stop_dma(struct dw_mci * host)378 static void dw_mci_idmac_stop_dma(struct dw_mci *host)
379 {
380 u32 temp;
381
382 /* Disable and reset the IDMAC interface */
383 temp = mci_readl(host, CTRL);
384 temp &= ~SDMMC_CTRL_USE_IDMAC;
385 temp |= SDMMC_CTRL_DMA_RESET;
386 mci_writel(host, CTRL, temp);
387
388 /* Stop the IDMAC running */
389 temp = mci_readl(host, BMOD);
390 temp &= ~(SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB);
391 temp |= SDMMC_IDMAC_SWRESET;
392 mci_writel(host, BMOD, temp);
393 }
394
dw_mci_idmac_complete_dma(struct dw_mci * host)395 static void dw_mci_idmac_complete_dma(struct dw_mci *host)
396 {
397 struct mmc_data *data = host->data;
398
399 dev_vdbg(host->dev, "DMA complete\n");
400
401 host->dma_ops->cleanup(host);
402
403 /*
404 * If the card was removed, data will be NULL. No point in trying to
405 * send the stop command or waiting for NBUSY in this case.
406 */
407 if (data) {
408 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
409 tasklet_schedule(&host->tasklet);
410 }
411 }
412
dw_mci_translate_sglist(struct dw_mci * host,struct mmc_data * data,unsigned int sg_len)413 static void dw_mci_translate_sglist(struct dw_mci *host, struct mmc_data *data,
414 unsigned int sg_len)
415 {
416 int i;
417 struct idmac_desc *desc = host->sg_cpu;
418
419 for (i = 0; i < sg_len; i++, desc++) {
420 unsigned int length = sg_dma_len(&data->sg[i]);
421 u32 mem_addr = sg_dma_address(&data->sg[i]);
422
423 /* Set the OWN bit and disable interrupts for this descriptor */
424 desc->des0 = IDMAC_DES0_OWN | IDMAC_DES0_DIC | IDMAC_DES0_CH;
425
426 /* Buffer length */
427 IDMAC_SET_BUFFER1_SIZE(desc, length);
428
429 /* Physical address to DMA to/from */
430 desc->des2 = mem_addr;
431 }
432
433 /* Set first descriptor */
434 desc = host->sg_cpu;
435 desc->des0 |= IDMAC_DES0_FD;
436
437 /* Set last descriptor */
438 desc = host->sg_cpu + (i - 1) * sizeof(struct idmac_desc);
439 desc->des0 &= ~(IDMAC_DES0_CH | IDMAC_DES0_DIC);
440 desc->des0 |= IDMAC_DES0_LD;
441
442 wmb();
443 }
444
dw_mci_idmac_start_dma(struct dw_mci * host,unsigned int sg_len)445 static void dw_mci_idmac_start_dma(struct dw_mci *host, unsigned int sg_len)
446 {
447 u32 temp;
448
449 dw_mci_translate_sglist(host, host->data, sg_len);
450
451 /* Select IDMAC interface */
452 temp = mci_readl(host, CTRL);
453 temp |= SDMMC_CTRL_USE_IDMAC;
454 mci_writel(host, CTRL, temp);
455
456 wmb();
457
458 /* Enable the IDMAC */
459 temp = mci_readl(host, BMOD);
460 temp |= SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB;
461 mci_writel(host, BMOD, temp);
462
463 /* Start it running */
464 mci_writel(host, PLDMND, 1);
465 }
466
dw_mci_idmac_init(struct dw_mci * host)467 static int dw_mci_idmac_init(struct dw_mci *host)
468 {
469 struct idmac_desc *p;
470 int i;
471
472 /* Number of descriptors in the ring buffer */
473 host->ring_size = PAGE_SIZE / sizeof(struct idmac_desc);
474
475 /* Forward link the descriptor list */
476 for (i = 0, p = host->sg_cpu; i < host->ring_size - 1; i++, p++)
477 p->des3 = host->sg_dma + (sizeof(struct idmac_desc) * (i + 1));
478
479 /* Set the last descriptor as the end-of-ring descriptor */
480 p->des3 = host->sg_dma;
481 p->des0 = IDMAC_DES0_ER;
482
483 dw_mci_idmac_reset(host);
484
485 /* Mask out interrupts - get Tx & Rx complete only */
486 mci_writel(host, IDSTS, IDMAC_INT_CLR);
487 mci_writel(host, IDINTEN, SDMMC_IDMAC_INT_NI | SDMMC_IDMAC_INT_RI |
488 SDMMC_IDMAC_INT_TI);
489
490 /* Set the descriptor base address */
491 mci_writel(host, DBADDR, host->sg_dma);
492 return 0;
493 }
494
495 static const struct dw_mci_dma_ops dw_mci_idmac_ops = {
496 .init = dw_mci_idmac_init,
497 .start = dw_mci_idmac_start_dma,
498 .stop = dw_mci_idmac_stop_dma,
499 .complete = dw_mci_idmac_complete_dma,
500 .cleanup = dw_mci_dma_cleanup,
501 };
502 #endif /* CONFIG_MMC_DW_IDMAC */
503
dw_mci_pre_dma_transfer(struct dw_mci * host,struct mmc_data * data,bool next)504 static int dw_mci_pre_dma_transfer(struct dw_mci *host,
505 struct mmc_data *data,
506 bool next)
507 {
508 struct scatterlist *sg;
509 unsigned int i, sg_len;
510
511 if (!next && data->host_cookie)
512 return data->host_cookie;
513
514 /*
515 * We don't do DMA on "complex" transfers, i.e. with
516 * non-word-aligned buffers or lengths. Also, we don't bother
517 * with all the DMA setup overhead for short transfers.
518 */
519 if (data->blocks * data->blksz < DW_MCI_DMA_THRESHOLD)
520 return -EINVAL;
521
522 if (data->blksz & 3)
523 return -EINVAL;
524
525 for_each_sg(data->sg, sg, data->sg_len, i) {
526 if (sg->offset & 3 || sg->length & 3)
527 return -EINVAL;
528 }
529
530 sg_len = dma_map_sg(host->dev,
531 data->sg,
532 data->sg_len,
533 dw_mci_get_dma_dir(data));
534 if (sg_len == 0)
535 return -EINVAL;
536
537 if (next)
538 data->host_cookie = sg_len;
539
540 return sg_len;
541 }
542
dw_mci_pre_req(struct mmc_host * mmc,struct mmc_request * mrq,bool is_first_req)543 static void dw_mci_pre_req(struct mmc_host *mmc,
544 struct mmc_request *mrq,
545 bool is_first_req)
546 {
547 struct dw_mci_slot *slot = mmc_priv(mmc);
548 struct mmc_data *data = mrq->data;
549
550 if (!slot->host->use_dma || !data)
551 return;
552
553 if (data->host_cookie) {
554 data->host_cookie = 0;
555 return;
556 }
557
558 if (dw_mci_pre_dma_transfer(slot->host, mrq->data, 1) < 0)
559 data->host_cookie = 0;
560 }
561
dw_mci_post_req(struct mmc_host * mmc,struct mmc_request * mrq,int err)562 static void dw_mci_post_req(struct mmc_host *mmc,
563 struct mmc_request *mrq,
564 int err)
565 {
566 struct dw_mci_slot *slot = mmc_priv(mmc);
567 struct mmc_data *data = mrq->data;
568
569 if (!slot->host->use_dma || !data)
570 return;
571
572 if (data->host_cookie)
573 dma_unmap_sg(slot->host->dev,
574 data->sg,
575 data->sg_len,
576 dw_mci_get_dma_dir(data));
577 data->host_cookie = 0;
578 }
579
dw_mci_adjust_fifoth(struct dw_mci * host,struct mmc_data * data)580 static void dw_mci_adjust_fifoth(struct dw_mci *host, struct mmc_data *data)
581 {
582 #ifdef CONFIG_MMC_DW_IDMAC
583 unsigned int blksz = data->blksz;
584 const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256};
585 u32 fifo_width = 1 << host->data_shift;
586 u32 blksz_depth = blksz / fifo_width, fifoth_val;
587 u32 msize = 0, rx_wmark = 1, tx_wmark, tx_wmark_invers;
588 int idx = (sizeof(mszs) / sizeof(mszs[0])) - 1;
589
590 tx_wmark = (host->fifo_depth) / 2;
591 tx_wmark_invers = host->fifo_depth - tx_wmark;
592
593 /*
594 * MSIZE is '1',
595 * if blksz is not a multiple of the FIFO width
596 */
597 if (blksz % fifo_width) {
598 msize = 0;
599 rx_wmark = 1;
600 goto done;
601 }
602
603 do {
604 if (!((blksz_depth % mszs[idx]) ||
605 (tx_wmark_invers % mszs[idx]))) {
606 msize = idx;
607 rx_wmark = mszs[idx] - 1;
608 break;
609 }
610 } while (--idx > 0);
611 /*
612 * If idx is '0', it won't be tried
613 * Thus, initial values are uesed
614 */
615 done:
616 fifoth_val = SDMMC_SET_FIFOTH(msize, rx_wmark, tx_wmark);
617 mci_writel(host, FIFOTH, fifoth_val);
618 #endif
619 }
620
dw_mci_ctrl_rd_thld(struct dw_mci * host,struct mmc_data * data)621 static void dw_mci_ctrl_rd_thld(struct dw_mci *host, struct mmc_data *data)
622 {
623 unsigned int blksz = data->blksz;
624 u32 blksz_depth, fifo_depth;
625 u16 thld_size;
626
627 WARN_ON(!(data->flags & MMC_DATA_READ));
628
629 /*
630 * CDTHRCTL doesn't exist prior to 240A (in fact that register offset is
631 * in the FIFO region, so we really shouldn't access it).
632 */
633 if (host->verid < DW_MMC_240A)
634 return;
635
636 if (host->timing != MMC_TIMING_MMC_HS200 &&
637 host->timing != MMC_TIMING_UHS_SDR104)
638 goto disable;
639
640 blksz_depth = blksz / (1 << host->data_shift);
641 fifo_depth = host->fifo_depth;
642
643 if (blksz_depth > fifo_depth)
644 goto disable;
645
646 /*
647 * If (blksz_depth) >= (fifo_depth >> 1), should be 'thld_size <= blksz'
648 * If (blksz_depth) < (fifo_depth >> 1), should be thld_size = blksz
649 * Currently just choose blksz.
650 */
651 thld_size = blksz;
652 mci_writel(host, CDTHRCTL, SDMMC_SET_RD_THLD(thld_size, 1));
653 return;
654
655 disable:
656 mci_writel(host, CDTHRCTL, SDMMC_SET_RD_THLD(0, 0));
657 }
658
dw_mci_submit_data_dma(struct dw_mci * host,struct mmc_data * data)659 static int dw_mci_submit_data_dma(struct dw_mci *host, struct mmc_data *data)
660 {
661 int sg_len;
662 u32 temp;
663
664 host->using_dma = 0;
665
666 /* If we don't have a channel, we can't do DMA */
667 if (!host->use_dma)
668 return -ENODEV;
669
670 sg_len = dw_mci_pre_dma_transfer(host, data, 0);
671 if (sg_len < 0) {
672 host->dma_ops->stop(host);
673 return sg_len;
674 }
675
676 host->using_dma = 1;
677
678 dev_vdbg(host->dev,
679 "sd sg_cpu: %#lx sg_dma: %#lx sg_len: %d\n",
680 (unsigned long)host->sg_cpu, (unsigned long)host->sg_dma,
681 sg_len);
682
683 /*
684 * Decide the MSIZE and RX/TX Watermark.
685 * If current block size is same with previous size,
686 * no need to update fifoth.
687 */
688 if (host->prev_blksz != data->blksz)
689 dw_mci_adjust_fifoth(host, data);
690
691 /* Enable the DMA interface */
692 temp = mci_readl(host, CTRL);
693 temp |= SDMMC_CTRL_DMA_ENABLE;
694 mci_writel(host, CTRL, temp);
695
696 /* Disable RX/TX IRQs, let DMA handle it */
697 temp = mci_readl(host, INTMASK);
698 temp &= ~(SDMMC_INT_RXDR | SDMMC_INT_TXDR);
699 mci_writel(host, INTMASK, temp);
700
701 host->dma_ops->start(host, sg_len);
702
703 return 0;
704 }
705
dw_mci_submit_data(struct dw_mci * host,struct mmc_data * data)706 static void dw_mci_submit_data(struct dw_mci *host, struct mmc_data *data)
707 {
708 u32 temp;
709
710 data->error = -EINPROGRESS;
711
712 WARN_ON(host->data);
713 host->sg = NULL;
714 host->data = data;
715
716 if (data->flags & MMC_DATA_READ) {
717 host->dir_status = DW_MCI_RECV_STATUS;
718 dw_mci_ctrl_rd_thld(host, data);
719 } else {
720 host->dir_status = DW_MCI_SEND_STATUS;
721 }
722
723 if (dw_mci_submit_data_dma(host, data)) {
724 int flags = SG_MITER_ATOMIC;
725 if (host->data->flags & MMC_DATA_READ)
726 flags |= SG_MITER_TO_SG;
727 else
728 flags |= SG_MITER_FROM_SG;
729
730 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
731 host->sg = data->sg;
732 host->part_buf_start = 0;
733 host->part_buf_count = 0;
734
735 mci_writel(host, RINTSTS, SDMMC_INT_TXDR | SDMMC_INT_RXDR);
736 temp = mci_readl(host, INTMASK);
737 temp |= SDMMC_INT_TXDR | SDMMC_INT_RXDR;
738 mci_writel(host, INTMASK, temp);
739
740 temp = mci_readl(host, CTRL);
741 temp &= ~SDMMC_CTRL_DMA_ENABLE;
742 mci_writel(host, CTRL, temp);
743
744 /*
745 * Use the initial fifoth_val for PIO mode.
746 * If next issued data may be transfered by DMA mode,
747 * prev_blksz should be invalidated.
748 */
749 mci_writel(host, FIFOTH, host->fifoth_val);
750 host->prev_blksz = 0;
751 } else {
752 /*
753 * Keep the current block size.
754 * It will be used to decide whether to update
755 * fifoth register next time.
756 */
757 host->prev_blksz = data->blksz;
758 }
759 }
760
mci_send_cmd(struct dw_mci_slot * slot,u32 cmd,u32 arg)761 static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg)
762 {
763 struct dw_mci *host = slot->host;
764 unsigned long timeout = jiffies + msecs_to_jiffies(500);
765 unsigned int cmd_status = 0;
766
767 mci_writel(host, CMDARG, arg);
768 wmb();
769 mci_writel(host, CMD, SDMMC_CMD_START | cmd);
770
771 while (time_before(jiffies, timeout)) {
772 cmd_status = mci_readl(host, CMD);
773 if (!(cmd_status & SDMMC_CMD_START))
774 return;
775 }
776 dev_err(&slot->mmc->class_dev,
777 "Timeout sending command (cmd %#x arg %#x status %#x)\n",
778 cmd, arg, cmd_status);
779 }
780
dw_mci_setup_bus(struct dw_mci_slot * slot,bool force_clkinit)781 static void dw_mci_setup_bus(struct dw_mci_slot *slot, bool force_clkinit)
782 {
783 struct dw_mci *host = slot->host;
784 unsigned int clock = slot->clock;
785 u32 div;
786 u32 clk_en_a;
787 u32 sdmmc_cmd_bits = SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT;
788
789 /* We must continue to set bit 28 in CMD until the change is complete */
790 if (host->state == STATE_WAITING_CMD11_DONE)
791 sdmmc_cmd_bits |= SDMMC_CMD_VOLT_SWITCH;
792
793 if (!clock) {
794 mci_writel(host, CLKENA, 0);
795 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
796 } else if (clock != host->current_speed || force_clkinit) {
797 div = host->bus_hz / clock;
798 if (host->bus_hz % clock && host->bus_hz > clock)
799 /*
800 * move the + 1 after the divide to prevent
801 * over-clocking the card.
802 */
803 div += 1;
804
805 div = (host->bus_hz != clock) ? DIV_ROUND_UP(div, 2) : 0;
806
807 if ((clock << div) != slot->__clk_old || force_clkinit)
808 dev_info(&slot->mmc->class_dev,
809 "Bus speed (slot %d) = %dHz (slot req %dHz, actual %dHZ div = %d)\n",
810 slot->id, host->bus_hz, clock,
811 div ? ((host->bus_hz / div) >> 1) :
812 host->bus_hz, div);
813
814 /* disable clock */
815 mci_writel(host, CLKENA, 0);
816 mci_writel(host, CLKSRC, 0);
817
818 /* inform CIU */
819 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
820
821 /* set clock to desired speed */
822 mci_writel(host, CLKDIV, div);
823
824 /* inform CIU */
825 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
826
827 /* enable clock; only low power if no SDIO */
828 clk_en_a = SDMMC_CLKEN_ENABLE << slot->id;
829 if (!(mci_readl(host, INTMASK) & SDMMC_INT_SDIO(slot->id)))
830 clk_en_a |= SDMMC_CLKEN_LOW_PWR << slot->id;
831 mci_writel(host, CLKENA, clk_en_a);
832
833 /* inform CIU */
834 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
835
836 /* keep the clock with reflecting clock dividor */
837 slot->__clk_old = clock << div;
838 }
839
840 host->current_speed = clock;
841
842 /* Set the current slot bus width */
843 mci_writel(host, CTYPE, (slot->ctype << slot->id));
844 }
845
__dw_mci_start_request(struct dw_mci * host,struct dw_mci_slot * slot,struct mmc_command * cmd)846 static void __dw_mci_start_request(struct dw_mci *host,
847 struct dw_mci_slot *slot,
848 struct mmc_command *cmd)
849 {
850 struct mmc_request *mrq;
851 struct mmc_data *data;
852 u32 cmdflags;
853
854 mrq = slot->mrq;
855
856 host->cur_slot = slot;
857 host->mrq = mrq;
858
859 host->pending_events = 0;
860 host->completed_events = 0;
861 host->cmd_status = 0;
862 host->data_status = 0;
863 host->dir_status = 0;
864
865 data = cmd->data;
866 if (data) {
867 mci_writel(host, TMOUT, 0xFFFFFFFF);
868 mci_writel(host, BYTCNT, data->blksz*data->blocks);
869 mci_writel(host, BLKSIZ, data->blksz);
870 }
871
872 cmdflags = dw_mci_prepare_command(slot->mmc, cmd);
873
874 /* this is the first command, send the initialization clock */
875 if (test_and_clear_bit(DW_MMC_CARD_NEED_INIT, &slot->flags))
876 cmdflags |= SDMMC_CMD_INIT;
877
878 if (data) {
879 dw_mci_submit_data(host, data);
880 wmb();
881 }
882
883 dw_mci_start_command(host, cmd, cmdflags);
884
885 if (mrq->stop)
886 host->stop_cmdr = dw_mci_prepare_command(slot->mmc, mrq->stop);
887 else
888 host->stop_cmdr = dw_mci_prep_stop_abort(host, cmd);
889 }
890
dw_mci_start_request(struct dw_mci * host,struct dw_mci_slot * slot)891 static void dw_mci_start_request(struct dw_mci *host,
892 struct dw_mci_slot *slot)
893 {
894 struct mmc_request *mrq = slot->mrq;
895 struct mmc_command *cmd;
896
897 cmd = mrq->sbc ? mrq->sbc : mrq->cmd;
898 __dw_mci_start_request(host, slot, cmd);
899 }
900
901 /* must be called with host->lock held */
dw_mci_queue_request(struct dw_mci * host,struct dw_mci_slot * slot,struct mmc_request * mrq)902 static void dw_mci_queue_request(struct dw_mci *host, struct dw_mci_slot *slot,
903 struct mmc_request *mrq)
904 {
905 dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n",
906 host->state);
907
908 slot->mrq = mrq;
909
910 if (host->state == STATE_WAITING_CMD11_DONE) {
911 dev_warn(&slot->mmc->class_dev,
912 "Voltage change didn't complete\n");
913 /*
914 * this case isn't expected to happen, so we can
915 * either crash here or just try to continue on
916 * in the closest possible state
917 */
918 host->state = STATE_IDLE;
919 }
920
921 if (host->state == STATE_IDLE) {
922 host->state = STATE_SENDING_CMD;
923 dw_mci_start_request(host, slot);
924 } else {
925 list_add_tail(&slot->queue_node, &host->queue);
926 }
927 }
928
dw_mci_request(struct mmc_host * mmc,struct mmc_request * mrq)929 static void dw_mci_request(struct mmc_host *mmc, struct mmc_request *mrq)
930 {
931 struct dw_mci_slot *slot = mmc_priv(mmc);
932 struct dw_mci *host = slot->host;
933
934 WARN_ON(slot->mrq);
935
936 /*
937 * The check for card presence and queueing of the request must be
938 * atomic, otherwise the card could be removed in between and the
939 * request wouldn't fail until another card was inserted.
940 */
941 spin_lock_bh(&host->lock);
942
943 if (!test_bit(DW_MMC_CARD_PRESENT, &slot->flags)) {
944 spin_unlock_bh(&host->lock);
945 mrq->cmd->error = -ENOMEDIUM;
946 mmc_request_done(mmc, mrq);
947 return;
948 }
949
950 dw_mci_queue_request(host, slot, mrq);
951
952 spin_unlock_bh(&host->lock);
953 }
954
dw_mci_set_ios(struct mmc_host * mmc,struct mmc_ios * ios)955 static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
956 {
957 struct dw_mci_slot *slot = mmc_priv(mmc);
958 const struct dw_mci_drv_data *drv_data = slot->host->drv_data;
959 u32 regs;
960 int ret;
961
962 switch (ios->bus_width) {
963 case MMC_BUS_WIDTH_4:
964 slot->ctype = SDMMC_CTYPE_4BIT;
965 break;
966 case MMC_BUS_WIDTH_8:
967 slot->ctype = SDMMC_CTYPE_8BIT;
968 break;
969 default:
970 /* set default 1 bit mode */
971 slot->ctype = SDMMC_CTYPE_1BIT;
972 }
973
974 regs = mci_readl(slot->host, UHS_REG);
975
976 /* DDR mode set */
977 if (ios->timing == MMC_TIMING_MMC_DDR52)
978 regs |= ((0x1 << slot->id) << 16);
979 else
980 regs &= ~((0x1 << slot->id) << 16);
981
982 mci_writel(slot->host, UHS_REG, regs);
983 slot->host->timing = ios->timing;
984
985 /*
986 * Use mirror of ios->clock to prevent race with mmc
987 * core ios update when finding the minimum.
988 */
989 slot->clock = ios->clock;
990
991 if (drv_data && drv_data->set_ios)
992 drv_data->set_ios(slot->host, ios);
993
994 /* Slot specific timing and width adjustment */
995 dw_mci_setup_bus(slot, false);
996
997 if (slot->host->state == STATE_WAITING_CMD11_DONE && ios->clock != 0)
998 slot->host->state = STATE_IDLE;
999
1000 switch (ios->power_mode) {
1001 case MMC_POWER_UP:
1002 if (!IS_ERR(mmc->supply.vmmc)) {
1003 ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc,
1004 ios->vdd);
1005 if (ret) {
1006 dev_err(slot->host->dev,
1007 "failed to enable vmmc regulator\n");
1008 /*return, if failed turn on vmmc*/
1009 return;
1010 }
1011 }
1012 if (!IS_ERR(mmc->supply.vqmmc) && !slot->host->vqmmc_enabled) {
1013 ret = regulator_enable(mmc->supply.vqmmc);
1014 if (ret < 0)
1015 dev_err(slot->host->dev,
1016 "failed to enable vqmmc regulator\n");
1017 else
1018 slot->host->vqmmc_enabled = true;
1019 }
1020 set_bit(DW_MMC_CARD_NEED_INIT, &slot->flags);
1021 regs = mci_readl(slot->host, PWREN);
1022 regs |= (1 << slot->id);
1023 mci_writel(slot->host, PWREN, regs);
1024 break;
1025 case MMC_POWER_OFF:
1026 if (!IS_ERR(mmc->supply.vmmc))
1027 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1028
1029 if (!IS_ERR(mmc->supply.vqmmc) && slot->host->vqmmc_enabled) {
1030 regulator_disable(mmc->supply.vqmmc);
1031 slot->host->vqmmc_enabled = false;
1032 }
1033
1034 regs = mci_readl(slot->host, PWREN);
1035 regs &= ~(1 << slot->id);
1036 mci_writel(slot->host, PWREN, regs);
1037 break;
1038 default:
1039 break;
1040 }
1041 }
1042
dw_mci_card_busy(struct mmc_host * mmc)1043 static int dw_mci_card_busy(struct mmc_host *mmc)
1044 {
1045 struct dw_mci_slot *slot = mmc_priv(mmc);
1046 u32 status;
1047
1048 /*
1049 * Check the busy bit which is low when DAT[3:0]
1050 * (the data lines) are 0000
1051 */
1052 status = mci_readl(slot->host, STATUS);
1053
1054 return !!(status & SDMMC_STATUS_BUSY);
1055 }
1056
dw_mci_switch_voltage(struct mmc_host * mmc,struct mmc_ios * ios)1057 static int dw_mci_switch_voltage(struct mmc_host *mmc, struct mmc_ios *ios)
1058 {
1059 struct dw_mci_slot *slot = mmc_priv(mmc);
1060 struct dw_mci *host = slot->host;
1061 u32 uhs;
1062 u32 v18 = SDMMC_UHS_18V << slot->id;
1063 int min_uv, max_uv;
1064 int ret;
1065
1066 /*
1067 * Program the voltage. Note that some instances of dw_mmc may use
1068 * the UHS_REG for this. For other instances (like exynos) the UHS_REG
1069 * does no harm but you need to set the regulator directly. Try both.
1070 */
1071 uhs = mci_readl(host, UHS_REG);
1072 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) {
1073 min_uv = 2700000;
1074 max_uv = 3600000;
1075 uhs &= ~v18;
1076 } else {
1077 min_uv = 1700000;
1078 max_uv = 1950000;
1079 uhs |= v18;
1080 }
1081 if (!IS_ERR(mmc->supply.vqmmc)) {
1082 ret = regulator_set_voltage(mmc->supply.vqmmc, min_uv, max_uv);
1083
1084 if (ret) {
1085 dev_err(&mmc->class_dev,
1086 "Regulator set error %d: %d - %d\n",
1087 ret, min_uv, max_uv);
1088 return ret;
1089 }
1090 }
1091 mci_writel(host, UHS_REG, uhs);
1092
1093 return 0;
1094 }
1095
dw_mci_get_ro(struct mmc_host * mmc)1096 static int dw_mci_get_ro(struct mmc_host *mmc)
1097 {
1098 int read_only;
1099 struct dw_mci_slot *slot = mmc_priv(mmc);
1100 int gpio_ro = mmc_gpio_get_ro(mmc);
1101
1102 /* Use platform get_ro function, else try on board write protect */
1103 if ((slot->quirks & DW_MCI_SLOT_QUIRK_NO_WRITE_PROTECT) ||
1104 (slot->host->quirks & DW_MCI_QUIRK_NO_WRITE_PROTECT))
1105 read_only = 0;
1106 else if (!IS_ERR_VALUE(gpio_ro))
1107 read_only = gpio_ro;
1108 else
1109 read_only =
1110 mci_readl(slot->host, WRTPRT) & (1 << slot->id) ? 1 : 0;
1111
1112 dev_dbg(&mmc->class_dev, "card is %s\n",
1113 read_only ? "read-only" : "read-write");
1114
1115 return read_only;
1116 }
1117
dw_mci_get_cd(struct mmc_host * mmc)1118 static int dw_mci_get_cd(struct mmc_host *mmc)
1119 {
1120 int present;
1121 struct dw_mci_slot *slot = mmc_priv(mmc);
1122 struct dw_mci_board *brd = slot->host->pdata;
1123 struct dw_mci *host = slot->host;
1124 int gpio_cd = mmc_gpio_get_cd(mmc);
1125
1126 /* Use platform get_cd function, else try onboard card detect */
1127 if (brd->quirks & DW_MCI_QUIRK_BROKEN_CARD_DETECTION)
1128 present = 1;
1129 else if (!IS_ERR_VALUE(gpio_cd))
1130 present = gpio_cd;
1131 else
1132 present = (mci_readl(slot->host, CDETECT) & (1 << slot->id))
1133 == 0 ? 1 : 0;
1134
1135 spin_lock_bh(&host->lock);
1136 if (present) {
1137 set_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1138 dev_dbg(&mmc->class_dev, "card is present\n");
1139 } else {
1140 clear_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1141 dev_dbg(&mmc->class_dev, "card is not present\n");
1142 }
1143 spin_unlock_bh(&host->lock);
1144
1145 return present;
1146 }
1147
1148 /*
1149 * Disable lower power mode.
1150 *
1151 * Low power mode will stop the card clock when idle. According to the
1152 * description of the CLKENA register we should disable low power mode
1153 * for SDIO cards if we need SDIO interrupts to work.
1154 *
1155 * This function is fast if low power mode is already disabled.
1156 */
dw_mci_disable_low_power(struct dw_mci_slot * slot)1157 static void dw_mci_disable_low_power(struct dw_mci_slot *slot)
1158 {
1159 struct dw_mci *host = slot->host;
1160 u32 clk_en_a;
1161 const u32 clken_low_pwr = SDMMC_CLKEN_LOW_PWR << slot->id;
1162
1163 clk_en_a = mci_readl(host, CLKENA);
1164
1165 if (clk_en_a & clken_low_pwr) {
1166 mci_writel(host, CLKENA, clk_en_a & ~clken_low_pwr);
1167 mci_send_cmd(slot, SDMMC_CMD_UPD_CLK |
1168 SDMMC_CMD_PRV_DAT_WAIT, 0);
1169 }
1170 }
1171
dw_mci_enable_sdio_irq(struct mmc_host * mmc,int enb)1172 static void dw_mci_enable_sdio_irq(struct mmc_host *mmc, int enb)
1173 {
1174 struct dw_mci_slot *slot = mmc_priv(mmc);
1175 struct dw_mci *host = slot->host;
1176 u32 int_mask;
1177
1178 /* Enable/disable Slot Specific SDIO interrupt */
1179 int_mask = mci_readl(host, INTMASK);
1180 if (enb) {
1181 /*
1182 * Turn off low power mode if it was enabled. This is a bit of
1183 * a heavy operation and we disable / enable IRQs a lot, so
1184 * we'll leave low power mode disabled and it will get
1185 * re-enabled again in dw_mci_setup_bus().
1186 */
1187 dw_mci_disable_low_power(slot);
1188
1189 mci_writel(host, INTMASK,
1190 (int_mask | SDMMC_INT_SDIO(slot->id)));
1191 } else {
1192 mci_writel(host, INTMASK,
1193 (int_mask & ~SDMMC_INT_SDIO(slot->id)));
1194 }
1195 }
1196
dw_mci_execute_tuning(struct mmc_host * mmc,u32 opcode)1197 static int dw_mci_execute_tuning(struct mmc_host *mmc, u32 opcode)
1198 {
1199 struct dw_mci_slot *slot = mmc_priv(mmc);
1200 struct dw_mci *host = slot->host;
1201 const struct dw_mci_drv_data *drv_data = host->drv_data;
1202 struct dw_mci_tuning_data tuning_data;
1203 int err = -ENOSYS;
1204
1205 if (opcode == MMC_SEND_TUNING_BLOCK_HS200) {
1206 if (mmc->ios.bus_width == MMC_BUS_WIDTH_8) {
1207 tuning_data.blk_pattern = tuning_blk_pattern_8bit;
1208 tuning_data.blksz = sizeof(tuning_blk_pattern_8bit);
1209 } else if (mmc->ios.bus_width == MMC_BUS_WIDTH_4) {
1210 tuning_data.blk_pattern = tuning_blk_pattern_4bit;
1211 tuning_data.blksz = sizeof(tuning_blk_pattern_4bit);
1212 } else {
1213 return -EINVAL;
1214 }
1215 } else if (opcode == MMC_SEND_TUNING_BLOCK) {
1216 tuning_data.blk_pattern = tuning_blk_pattern_4bit;
1217 tuning_data.blksz = sizeof(tuning_blk_pattern_4bit);
1218 } else {
1219 dev_err(host->dev,
1220 "Undefined command(%d) for tuning\n", opcode);
1221 return -EINVAL;
1222 }
1223
1224 if (drv_data && drv_data->execute_tuning)
1225 err = drv_data->execute_tuning(slot, opcode, &tuning_data);
1226 return err;
1227 }
1228
1229 static const struct mmc_host_ops dw_mci_ops = {
1230 .request = dw_mci_request,
1231 .pre_req = dw_mci_pre_req,
1232 .post_req = dw_mci_post_req,
1233 .set_ios = dw_mci_set_ios,
1234 .get_ro = dw_mci_get_ro,
1235 .get_cd = dw_mci_get_cd,
1236 .enable_sdio_irq = dw_mci_enable_sdio_irq,
1237 .execute_tuning = dw_mci_execute_tuning,
1238 .card_busy = dw_mci_card_busy,
1239 .start_signal_voltage_switch = dw_mci_switch_voltage,
1240
1241 };
1242
dw_mci_request_end(struct dw_mci * host,struct mmc_request * mrq)1243 static void dw_mci_request_end(struct dw_mci *host, struct mmc_request *mrq)
1244 __releases(&host->lock)
1245 __acquires(&host->lock)
1246 {
1247 struct dw_mci_slot *slot;
1248 struct mmc_host *prev_mmc = host->cur_slot->mmc;
1249
1250 WARN_ON(host->cmd || host->data);
1251
1252 host->cur_slot->mrq = NULL;
1253 host->mrq = NULL;
1254 if (!list_empty(&host->queue)) {
1255 slot = list_entry(host->queue.next,
1256 struct dw_mci_slot, queue_node);
1257 list_del(&slot->queue_node);
1258 dev_vdbg(host->dev, "list not empty: %s is next\n",
1259 mmc_hostname(slot->mmc));
1260 host->state = STATE_SENDING_CMD;
1261 dw_mci_start_request(host, slot);
1262 } else {
1263 dev_vdbg(host->dev, "list empty\n");
1264
1265 if (host->state == STATE_SENDING_CMD11)
1266 host->state = STATE_WAITING_CMD11_DONE;
1267 else
1268 host->state = STATE_IDLE;
1269 }
1270
1271 spin_unlock(&host->lock);
1272 mmc_request_done(prev_mmc, mrq);
1273 spin_lock(&host->lock);
1274 }
1275
dw_mci_command_complete(struct dw_mci * host,struct mmc_command * cmd)1276 static int dw_mci_command_complete(struct dw_mci *host, struct mmc_command *cmd)
1277 {
1278 u32 status = host->cmd_status;
1279
1280 host->cmd_status = 0;
1281
1282 /* Read the response from the card (up to 16 bytes) */
1283 if (cmd->flags & MMC_RSP_PRESENT) {
1284 if (cmd->flags & MMC_RSP_136) {
1285 cmd->resp[3] = mci_readl(host, RESP0);
1286 cmd->resp[2] = mci_readl(host, RESP1);
1287 cmd->resp[1] = mci_readl(host, RESP2);
1288 cmd->resp[0] = mci_readl(host, RESP3);
1289 } else {
1290 cmd->resp[0] = mci_readl(host, RESP0);
1291 cmd->resp[1] = 0;
1292 cmd->resp[2] = 0;
1293 cmd->resp[3] = 0;
1294 }
1295 }
1296
1297 if (status & SDMMC_INT_RTO)
1298 cmd->error = -ETIMEDOUT;
1299 else if ((cmd->flags & MMC_RSP_CRC) && (status & SDMMC_INT_RCRC))
1300 cmd->error = -EILSEQ;
1301 else if (status & SDMMC_INT_RESP_ERR)
1302 cmd->error = -EIO;
1303 else
1304 cmd->error = 0;
1305
1306 if (cmd->error) {
1307 /* newer ip versions need a delay between retries */
1308 if (host->quirks & DW_MCI_QUIRK_RETRY_DELAY)
1309 mdelay(20);
1310 }
1311
1312 return cmd->error;
1313 }
1314
dw_mci_data_complete(struct dw_mci * host,struct mmc_data * data)1315 static int dw_mci_data_complete(struct dw_mci *host, struct mmc_data *data)
1316 {
1317 u32 status = host->data_status;
1318
1319 if (status & DW_MCI_DATA_ERROR_FLAGS) {
1320 if (status & SDMMC_INT_DRTO) {
1321 data->error = -ETIMEDOUT;
1322 } else if (status & SDMMC_INT_DCRC) {
1323 data->error = -EILSEQ;
1324 } else if (status & SDMMC_INT_EBE) {
1325 if (host->dir_status ==
1326 DW_MCI_SEND_STATUS) {
1327 /*
1328 * No data CRC status was returned.
1329 * The number of bytes transferred
1330 * will be exaggerated in PIO mode.
1331 */
1332 data->bytes_xfered = 0;
1333 data->error = -ETIMEDOUT;
1334 } else if (host->dir_status ==
1335 DW_MCI_RECV_STATUS) {
1336 data->error = -EIO;
1337 }
1338 } else {
1339 /* SDMMC_INT_SBE is included */
1340 data->error = -EIO;
1341 }
1342
1343 dev_dbg(host->dev, "data error, status 0x%08x\n", status);
1344
1345 /*
1346 * After an error, there may be data lingering
1347 * in the FIFO
1348 */
1349 dw_mci_reset(host);
1350 } else {
1351 data->bytes_xfered = data->blocks * data->blksz;
1352 data->error = 0;
1353 }
1354
1355 return data->error;
1356 }
1357
dw_mci_tasklet_func(unsigned long priv)1358 static void dw_mci_tasklet_func(unsigned long priv)
1359 {
1360 struct dw_mci *host = (struct dw_mci *)priv;
1361 struct mmc_data *data;
1362 struct mmc_command *cmd;
1363 struct mmc_request *mrq;
1364 enum dw_mci_state state;
1365 enum dw_mci_state prev_state;
1366 unsigned int err;
1367
1368 spin_lock(&host->lock);
1369
1370 state = host->state;
1371 data = host->data;
1372 mrq = host->mrq;
1373
1374 do {
1375 prev_state = state;
1376
1377 switch (state) {
1378 case STATE_IDLE:
1379 case STATE_WAITING_CMD11_DONE:
1380 break;
1381
1382 case STATE_SENDING_CMD11:
1383 case STATE_SENDING_CMD:
1384 if (!test_and_clear_bit(EVENT_CMD_COMPLETE,
1385 &host->pending_events))
1386 break;
1387
1388 cmd = host->cmd;
1389 host->cmd = NULL;
1390 set_bit(EVENT_CMD_COMPLETE, &host->completed_events);
1391 err = dw_mci_command_complete(host, cmd);
1392 if (cmd == mrq->sbc && !err) {
1393 prev_state = state = STATE_SENDING_CMD;
1394 __dw_mci_start_request(host, host->cur_slot,
1395 mrq->cmd);
1396 goto unlock;
1397 }
1398
1399 if (cmd->data && err) {
1400 dw_mci_stop_dma(host);
1401 send_stop_abort(host, data);
1402 state = STATE_SENDING_STOP;
1403 break;
1404 }
1405
1406 if (!cmd->data || err) {
1407 dw_mci_request_end(host, mrq);
1408 goto unlock;
1409 }
1410
1411 prev_state = state = STATE_SENDING_DATA;
1412 /* fall through */
1413
1414 case STATE_SENDING_DATA:
1415 /*
1416 * We could get a data error and never a transfer
1417 * complete so we'd better check for it here.
1418 *
1419 * Note that we don't really care if we also got a
1420 * transfer complete; stopping the DMA and sending an
1421 * abort won't hurt.
1422 */
1423 if (test_and_clear_bit(EVENT_DATA_ERROR,
1424 &host->pending_events)) {
1425 dw_mci_stop_dma(host);
1426 send_stop_abort(host, data);
1427 state = STATE_DATA_ERROR;
1428 break;
1429 }
1430
1431 if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
1432 &host->pending_events))
1433 break;
1434
1435 set_bit(EVENT_XFER_COMPLETE, &host->completed_events);
1436
1437 /*
1438 * Handle an EVENT_DATA_ERROR that might have shown up
1439 * before the transfer completed. This might not have
1440 * been caught by the check above because the interrupt
1441 * could have gone off between the previous check and
1442 * the check for transfer complete.
1443 *
1444 * Technically this ought not be needed assuming we
1445 * get a DATA_COMPLETE eventually (we'll notice the
1446 * error and end the request), but it shouldn't hurt.
1447 *
1448 * This has the advantage of sending the stop command.
1449 */
1450 if (test_and_clear_bit(EVENT_DATA_ERROR,
1451 &host->pending_events)) {
1452 dw_mci_stop_dma(host);
1453 send_stop_abort(host, data);
1454 state = STATE_DATA_ERROR;
1455 break;
1456 }
1457 prev_state = state = STATE_DATA_BUSY;
1458
1459 /* fall through */
1460
1461 case STATE_DATA_BUSY:
1462 if (!test_and_clear_bit(EVENT_DATA_COMPLETE,
1463 &host->pending_events))
1464 break;
1465
1466 host->data = NULL;
1467 set_bit(EVENT_DATA_COMPLETE, &host->completed_events);
1468 err = dw_mci_data_complete(host, data);
1469
1470 if (!err) {
1471 if (!data->stop || mrq->sbc) {
1472 if (mrq->sbc && data->stop)
1473 data->stop->error = 0;
1474 dw_mci_request_end(host, mrq);
1475 goto unlock;
1476 }
1477
1478 /* stop command for open-ended transfer*/
1479 if (data->stop)
1480 send_stop_abort(host, data);
1481 } else {
1482 /*
1483 * If we don't have a command complete now we'll
1484 * never get one since we just reset everything;
1485 * better end the request.
1486 *
1487 * If we do have a command complete we'll fall
1488 * through to the SENDING_STOP command and
1489 * everything will be peachy keen.
1490 */
1491 if (!test_bit(EVENT_CMD_COMPLETE,
1492 &host->pending_events)) {
1493 host->cmd = NULL;
1494 dw_mci_request_end(host, mrq);
1495 goto unlock;
1496 }
1497 }
1498
1499 /*
1500 * If err has non-zero,
1501 * stop-abort command has been already issued.
1502 */
1503 prev_state = state = STATE_SENDING_STOP;
1504
1505 /* fall through */
1506
1507 case STATE_SENDING_STOP:
1508 if (!test_and_clear_bit(EVENT_CMD_COMPLETE,
1509 &host->pending_events))
1510 break;
1511
1512 /* CMD error in data command */
1513 if (mrq->cmd->error && mrq->data)
1514 dw_mci_reset(host);
1515
1516 host->cmd = NULL;
1517 host->data = NULL;
1518
1519 if (mrq->stop)
1520 dw_mci_command_complete(host, mrq->stop);
1521 else
1522 host->cmd_status = 0;
1523
1524 dw_mci_request_end(host, mrq);
1525 goto unlock;
1526
1527 case STATE_DATA_ERROR:
1528 if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
1529 &host->pending_events))
1530 break;
1531
1532 state = STATE_DATA_BUSY;
1533 break;
1534 }
1535 } while (state != prev_state);
1536
1537 host->state = state;
1538 unlock:
1539 spin_unlock(&host->lock);
1540
1541 }
1542
1543 /* push final bytes to part_buf, only use during push */
dw_mci_set_part_bytes(struct dw_mci * host,void * buf,int cnt)1544 static void dw_mci_set_part_bytes(struct dw_mci *host, void *buf, int cnt)
1545 {
1546 memcpy((void *)&host->part_buf, buf, cnt);
1547 host->part_buf_count = cnt;
1548 }
1549
1550 /* append bytes to part_buf, only use during push */
dw_mci_push_part_bytes(struct dw_mci * host,void * buf,int cnt)1551 static int dw_mci_push_part_bytes(struct dw_mci *host, void *buf, int cnt)
1552 {
1553 cnt = min(cnt, (1 << host->data_shift) - host->part_buf_count);
1554 memcpy((void *)&host->part_buf + host->part_buf_count, buf, cnt);
1555 host->part_buf_count += cnt;
1556 return cnt;
1557 }
1558
1559 /* pull first bytes from part_buf, only use during pull */
dw_mci_pull_part_bytes(struct dw_mci * host,void * buf,int cnt)1560 static int dw_mci_pull_part_bytes(struct dw_mci *host, void *buf, int cnt)
1561 {
1562 cnt = min(cnt, (int)host->part_buf_count);
1563 if (cnt) {
1564 memcpy(buf, (void *)&host->part_buf + host->part_buf_start,
1565 cnt);
1566 host->part_buf_count -= cnt;
1567 host->part_buf_start += cnt;
1568 }
1569 return cnt;
1570 }
1571
1572 /* pull final bytes from the part_buf, assuming it's just been filled */
dw_mci_pull_final_bytes(struct dw_mci * host,void * buf,int cnt)1573 static void dw_mci_pull_final_bytes(struct dw_mci *host, void *buf, int cnt)
1574 {
1575 memcpy(buf, &host->part_buf, cnt);
1576 host->part_buf_start = cnt;
1577 host->part_buf_count = (1 << host->data_shift) - cnt;
1578 }
1579
dw_mci_push_data16(struct dw_mci * host,void * buf,int cnt)1580 static void dw_mci_push_data16(struct dw_mci *host, void *buf, int cnt)
1581 {
1582 struct mmc_data *data = host->data;
1583 int init_cnt = cnt;
1584
1585 /* try and push anything in the part_buf */
1586 if (unlikely(host->part_buf_count)) {
1587 int len = dw_mci_push_part_bytes(host, buf, cnt);
1588 buf += len;
1589 cnt -= len;
1590 if (host->part_buf_count == 2) {
1591 mci_writew(host, DATA(host->data_offset),
1592 host->part_buf16);
1593 host->part_buf_count = 0;
1594 }
1595 }
1596 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1597 if (unlikely((unsigned long)buf & 0x1)) {
1598 while (cnt >= 2) {
1599 u16 aligned_buf[64];
1600 int len = min(cnt & -2, (int)sizeof(aligned_buf));
1601 int items = len >> 1;
1602 int i;
1603 /* memcpy from input buffer into aligned buffer */
1604 memcpy(aligned_buf, buf, len);
1605 buf += len;
1606 cnt -= len;
1607 /* push data from aligned buffer into fifo */
1608 for (i = 0; i < items; ++i)
1609 mci_writew(host, DATA(host->data_offset),
1610 aligned_buf[i]);
1611 }
1612 } else
1613 #endif
1614 {
1615 u16 *pdata = buf;
1616 for (; cnt >= 2; cnt -= 2)
1617 mci_writew(host, DATA(host->data_offset), *pdata++);
1618 buf = pdata;
1619 }
1620 /* put anything remaining in the part_buf */
1621 if (cnt) {
1622 dw_mci_set_part_bytes(host, buf, cnt);
1623 /* Push data if we have reached the expected data length */
1624 if ((data->bytes_xfered + init_cnt) ==
1625 (data->blksz * data->blocks))
1626 mci_writew(host, DATA(host->data_offset),
1627 host->part_buf16);
1628 }
1629 }
1630
dw_mci_pull_data16(struct dw_mci * host,void * buf,int cnt)1631 static void dw_mci_pull_data16(struct dw_mci *host, void *buf, int cnt)
1632 {
1633 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1634 if (unlikely((unsigned long)buf & 0x1)) {
1635 while (cnt >= 2) {
1636 /* pull data from fifo into aligned buffer */
1637 u16 aligned_buf[64];
1638 int len = min(cnt & -2, (int)sizeof(aligned_buf));
1639 int items = len >> 1;
1640 int i;
1641 for (i = 0; i < items; ++i)
1642 aligned_buf[i] = mci_readw(host,
1643 DATA(host->data_offset));
1644 /* memcpy from aligned buffer into output buffer */
1645 memcpy(buf, aligned_buf, len);
1646 buf += len;
1647 cnt -= len;
1648 }
1649 } else
1650 #endif
1651 {
1652 u16 *pdata = buf;
1653 for (; cnt >= 2; cnt -= 2)
1654 *pdata++ = mci_readw(host, DATA(host->data_offset));
1655 buf = pdata;
1656 }
1657 if (cnt) {
1658 host->part_buf16 = mci_readw(host, DATA(host->data_offset));
1659 dw_mci_pull_final_bytes(host, buf, cnt);
1660 }
1661 }
1662
dw_mci_push_data32(struct dw_mci * host,void * buf,int cnt)1663 static void dw_mci_push_data32(struct dw_mci *host, void *buf, int cnt)
1664 {
1665 struct mmc_data *data = host->data;
1666 int init_cnt = cnt;
1667
1668 /* try and push anything in the part_buf */
1669 if (unlikely(host->part_buf_count)) {
1670 int len = dw_mci_push_part_bytes(host, buf, cnt);
1671 buf += len;
1672 cnt -= len;
1673 if (host->part_buf_count == 4) {
1674 mci_writel(host, DATA(host->data_offset),
1675 host->part_buf32);
1676 host->part_buf_count = 0;
1677 }
1678 }
1679 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1680 if (unlikely((unsigned long)buf & 0x3)) {
1681 while (cnt >= 4) {
1682 u32 aligned_buf[32];
1683 int len = min(cnt & -4, (int)sizeof(aligned_buf));
1684 int items = len >> 2;
1685 int i;
1686 /* memcpy from input buffer into aligned buffer */
1687 memcpy(aligned_buf, buf, len);
1688 buf += len;
1689 cnt -= len;
1690 /* push data from aligned buffer into fifo */
1691 for (i = 0; i < items; ++i)
1692 mci_writel(host, DATA(host->data_offset),
1693 aligned_buf[i]);
1694 }
1695 } else
1696 #endif
1697 {
1698 u32 *pdata = buf;
1699 for (; cnt >= 4; cnt -= 4)
1700 mci_writel(host, DATA(host->data_offset), *pdata++);
1701 buf = pdata;
1702 }
1703 /* put anything remaining in the part_buf */
1704 if (cnt) {
1705 dw_mci_set_part_bytes(host, buf, cnt);
1706 /* Push data if we have reached the expected data length */
1707 if ((data->bytes_xfered + init_cnt) ==
1708 (data->blksz * data->blocks))
1709 mci_writel(host, DATA(host->data_offset),
1710 host->part_buf32);
1711 }
1712 }
1713
dw_mci_pull_data32(struct dw_mci * host,void * buf,int cnt)1714 static void dw_mci_pull_data32(struct dw_mci *host, void *buf, int cnt)
1715 {
1716 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1717 if (unlikely((unsigned long)buf & 0x3)) {
1718 while (cnt >= 4) {
1719 /* pull data from fifo into aligned buffer */
1720 u32 aligned_buf[32];
1721 int len = min(cnt & -4, (int)sizeof(aligned_buf));
1722 int items = len >> 2;
1723 int i;
1724 for (i = 0; i < items; ++i)
1725 aligned_buf[i] = mci_readl(host,
1726 DATA(host->data_offset));
1727 /* memcpy from aligned buffer into output buffer */
1728 memcpy(buf, aligned_buf, len);
1729 buf += len;
1730 cnt -= len;
1731 }
1732 } else
1733 #endif
1734 {
1735 u32 *pdata = buf;
1736 for (; cnt >= 4; cnt -= 4)
1737 *pdata++ = mci_readl(host, DATA(host->data_offset));
1738 buf = pdata;
1739 }
1740 if (cnt) {
1741 host->part_buf32 = mci_readl(host, DATA(host->data_offset));
1742 dw_mci_pull_final_bytes(host, buf, cnt);
1743 }
1744 }
1745
dw_mci_push_data64(struct dw_mci * host,void * buf,int cnt)1746 static void dw_mci_push_data64(struct dw_mci *host, void *buf, int cnt)
1747 {
1748 struct mmc_data *data = host->data;
1749 int init_cnt = cnt;
1750
1751 /* try and push anything in the part_buf */
1752 if (unlikely(host->part_buf_count)) {
1753 int len = dw_mci_push_part_bytes(host, buf, cnt);
1754 buf += len;
1755 cnt -= len;
1756
1757 if (host->part_buf_count == 8) {
1758 mci_writeq(host, DATA(host->data_offset),
1759 host->part_buf);
1760 host->part_buf_count = 0;
1761 }
1762 }
1763 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1764 if (unlikely((unsigned long)buf & 0x7)) {
1765 while (cnt >= 8) {
1766 u64 aligned_buf[16];
1767 int len = min(cnt & -8, (int)sizeof(aligned_buf));
1768 int items = len >> 3;
1769 int i;
1770 /* memcpy from input buffer into aligned buffer */
1771 memcpy(aligned_buf, buf, len);
1772 buf += len;
1773 cnt -= len;
1774 /* push data from aligned buffer into fifo */
1775 for (i = 0; i < items; ++i)
1776 mci_writeq(host, DATA(host->data_offset),
1777 aligned_buf[i]);
1778 }
1779 } else
1780 #endif
1781 {
1782 u64 *pdata = buf;
1783 for (; cnt >= 8; cnt -= 8)
1784 mci_writeq(host, DATA(host->data_offset), *pdata++);
1785 buf = pdata;
1786 }
1787 /* put anything remaining in the part_buf */
1788 if (cnt) {
1789 dw_mci_set_part_bytes(host, buf, cnt);
1790 /* Push data if we have reached the expected data length */
1791 if ((data->bytes_xfered + init_cnt) ==
1792 (data->blksz * data->blocks))
1793 mci_writeq(host, DATA(host->data_offset),
1794 host->part_buf);
1795 }
1796 }
1797
dw_mci_pull_data64(struct dw_mci * host,void * buf,int cnt)1798 static void dw_mci_pull_data64(struct dw_mci *host, void *buf, int cnt)
1799 {
1800 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1801 if (unlikely((unsigned long)buf & 0x7)) {
1802 while (cnt >= 8) {
1803 /* pull data from fifo into aligned buffer */
1804 u64 aligned_buf[16];
1805 int len = min(cnt & -8, (int)sizeof(aligned_buf));
1806 int items = len >> 3;
1807 int i;
1808 for (i = 0; i < items; ++i)
1809 aligned_buf[i] = mci_readq(host,
1810 DATA(host->data_offset));
1811 /* memcpy from aligned buffer into output buffer */
1812 memcpy(buf, aligned_buf, len);
1813 buf += len;
1814 cnt -= len;
1815 }
1816 } else
1817 #endif
1818 {
1819 u64 *pdata = buf;
1820 for (; cnt >= 8; cnt -= 8)
1821 *pdata++ = mci_readq(host, DATA(host->data_offset));
1822 buf = pdata;
1823 }
1824 if (cnt) {
1825 host->part_buf = mci_readq(host, DATA(host->data_offset));
1826 dw_mci_pull_final_bytes(host, buf, cnt);
1827 }
1828 }
1829
dw_mci_pull_data(struct dw_mci * host,void * buf,int cnt)1830 static void dw_mci_pull_data(struct dw_mci *host, void *buf, int cnt)
1831 {
1832 int len;
1833
1834 /* get remaining partial bytes */
1835 len = dw_mci_pull_part_bytes(host, buf, cnt);
1836 if (unlikely(len == cnt))
1837 return;
1838 buf += len;
1839 cnt -= len;
1840
1841 /* get the rest of the data */
1842 host->pull_data(host, buf, cnt);
1843 }
1844
dw_mci_read_data_pio(struct dw_mci * host,bool dto)1845 static void dw_mci_read_data_pio(struct dw_mci *host, bool dto)
1846 {
1847 struct sg_mapping_iter *sg_miter = &host->sg_miter;
1848 void *buf;
1849 unsigned int offset;
1850 struct mmc_data *data = host->data;
1851 int shift = host->data_shift;
1852 u32 status;
1853 unsigned int len;
1854 unsigned int remain, fcnt;
1855
1856 do {
1857 if (!sg_miter_next(sg_miter))
1858 goto done;
1859
1860 host->sg = sg_miter->piter.sg;
1861 buf = sg_miter->addr;
1862 remain = sg_miter->length;
1863 offset = 0;
1864
1865 do {
1866 fcnt = (SDMMC_GET_FCNT(mci_readl(host, STATUS))
1867 << shift) + host->part_buf_count;
1868 len = min(remain, fcnt);
1869 if (!len)
1870 break;
1871 dw_mci_pull_data(host, (void *)(buf + offset), len);
1872 data->bytes_xfered += len;
1873 offset += len;
1874 remain -= len;
1875 } while (remain);
1876
1877 sg_miter->consumed = offset;
1878 status = mci_readl(host, MINTSTS);
1879 mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
1880 /* if the RXDR is ready read again */
1881 } while ((status & SDMMC_INT_RXDR) ||
1882 (dto && SDMMC_GET_FCNT(mci_readl(host, STATUS))));
1883
1884 if (!remain) {
1885 if (!sg_miter_next(sg_miter))
1886 goto done;
1887 sg_miter->consumed = 0;
1888 }
1889 sg_miter_stop(sg_miter);
1890 return;
1891
1892 done:
1893 sg_miter_stop(sg_miter);
1894 host->sg = NULL;
1895 smp_wmb();
1896 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
1897 }
1898
dw_mci_write_data_pio(struct dw_mci * host)1899 static void dw_mci_write_data_pio(struct dw_mci *host)
1900 {
1901 struct sg_mapping_iter *sg_miter = &host->sg_miter;
1902 void *buf;
1903 unsigned int offset;
1904 struct mmc_data *data = host->data;
1905 int shift = host->data_shift;
1906 u32 status;
1907 unsigned int len;
1908 unsigned int fifo_depth = host->fifo_depth;
1909 unsigned int remain, fcnt;
1910
1911 do {
1912 if (!sg_miter_next(sg_miter))
1913 goto done;
1914
1915 host->sg = sg_miter->piter.sg;
1916 buf = sg_miter->addr;
1917 remain = sg_miter->length;
1918 offset = 0;
1919
1920 do {
1921 fcnt = ((fifo_depth -
1922 SDMMC_GET_FCNT(mci_readl(host, STATUS)))
1923 << shift) - host->part_buf_count;
1924 len = min(remain, fcnt);
1925 if (!len)
1926 break;
1927 host->push_data(host, (void *)(buf + offset), len);
1928 data->bytes_xfered += len;
1929 offset += len;
1930 remain -= len;
1931 } while (remain);
1932
1933 sg_miter->consumed = offset;
1934 status = mci_readl(host, MINTSTS);
1935 mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
1936 } while (status & SDMMC_INT_TXDR); /* if TXDR write again */
1937
1938 if (!remain) {
1939 if (!sg_miter_next(sg_miter))
1940 goto done;
1941 sg_miter->consumed = 0;
1942 }
1943 sg_miter_stop(sg_miter);
1944 return;
1945
1946 done:
1947 sg_miter_stop(sg_miter);
1948 host->sg = NULL;
1949 smp_wmb();
1950 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
1951 }
1952
dw_mci_cmd_interrupt(struct dw_mci * host,u32 status)1953 static void dw_mci_cmd_interrupt(struct dw_mci *host, u32 status)
1954 {
1955 if (!host->cmd_status)
1956 host->cmd_status = status;
1957
1958 smp_wmb();
1959
1960 set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
1961 tasklet_schedule(&host->tasklet);
1962 }
1963
dw_mci_interrupt(int irq,void * dev_id)1964 static irqreturn_t dw_mci_interrupt(int irq, void *dev_id)
1965 {
1966 struct dw_mci *host = dev_id;
1967 u32 pending;
1968 int i;
1969
1970 pending = mci_readl(host, MINTSTS); /* read-only mask reg */
1971
1972 /*
1973 * DTO fix - version 2.10a and below, and only if internal DMA
1974 * is configured.
1975 */
1976 if (host->quirks & DW_MCI_QUIRK_IDMAC_DTO) {
1977 if (!pending &&
1978 ((mci_readl(host, STATUS) >> 17) & 0x1fff))
1979 pending |= SDMMC_INT_DATA_OVER;
1980 }
1981
1982 if (pending) {
1983 /* Check volt switch first, since it can look like an error */
1984 if ((host->state == STATE_SENDING_CMD11) &&
1985 (pending & SDMMC_INT_VOLT_SWITCH)) {
1986 mci_writel(host, RINTSTS, SDMMC_INT_VOLT_SWITCH);
1987 pending &= ~SDMMC_INT_VOLT_SWITCH;
1988 dw_mci_cmd_interrupt(host, pending);
1989 }
1990
1991 if (pending & DW_MCI_CMD_ERROR_FLAGS) {
1992 mci_writel(host, RINTSTS, DW_MCI_CMD_ERROR_FLAGS);
1993 host->cmd_status = pending;
1994 smp_wmb();
1995 set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
1996 }
1997
1998 if (pending & DW_MCI_DATA_ERROR_FLAGS) {
1999 /* if there is an error report DATA_ERROR */
2000 mci_writel(host, RINTSTS, DW_MCI_DATA_ERROR_FLAGS);
2001 host->data_status = pending;
2002 smp_wmb();
2003 set_bit(EVENT_DATA_ERROR, &host->pending_events);
2004 tasklet_schedule(&host->tasklet);
2005 }
2006
2007 if (pending & SDMMC_INT_DATA_OVER) {
2008 mci_writel(host, RINTSTS, SDMMC_INT_DATA_OVER);
2009 if (!host->data_status)
2010 host->data_status = pending;
2011 smp_wmb();
2012 if (host->dir_status == DW_MCI_RECV_STATUS) {
2013 if (host->sg != NULL)
2014 dw_mci_read_data_pio(host, true);
2015 }
2016 set_bit(EVENT_DATA_COMPLETE, &host->pending_events);
2017 tasklet_schedule(&host->tasklet);
2018 }
2019
2020 if (pending & SDMMC_INT_RXDR) {
2021 mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
2022 if (host->dir_status == DW_MCI_RECV_STATUS && host->sg)
2023 dw_mci_read_data_pio(host, false);
2024 }
2025
2026 if (pending & SDMMC_INT_TXDR) {
2027 mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
2028 if (host->dir_status == DW_MCI_SEND_STATUS && host->sg)
2029 dw_mci_write_data_pio(host);
2030 }
2031
2032 if (pending & SDMMC_INT_CMD_DONE) {
2033 mci_writel(host, RINTSTS, SDMMC_INT_CMD_DONE);
2034 dw_mci_cmd_interrupt(host, pending);
2035 }
2036
2037 if (pending & SDMMC_INT_CD) {
2038 mci_writel(host, RINTSTS, SDMMC_INT_CD);
2039 queue_work(host->card_workqueue, &host->card_work);
2040 }
2041
2042 /* Handle SDIO Interrupts */
2043 for (i = 0; i < host->num_slots; i++) {
2044 struct dw_mci_slot *slot = host->slot[i];
2045 if (pending & SDMMC_INT_SDIO(i)) {
2046 mci_writel(host, RINTSTS, SDMMC_INT_SDIO(i));
2047 mmc_signal_sdio_irq(slot->mmc);
2048 }
2049 }
2050
2051 }
2052
2053 #ifdef CONFIG_MMC_DW_IDMAC
2054 /* Handle DMA interrupts */
2055 pending = mci_readl(host, IDSTS);
2056 if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) {
2057 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI);
2058 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_NI);
2059 host->dma_ops->complete(host);
2060 }
2061 #endif
2062
2063 return IRQ_HANDLED;
2064 }
2065
dw_mci_work_routine_card(struct work_struct * work)2066 static void dw_mci_work_routine_card(struct work_struct *work)
2067 {
2068 struct dw_mci *host = container_of(work, struct dw_mci, card_work);
2069 int i;
2070
2071 for (i = 0; i < host->num_slots; i++) {
2072 struct dw_mci_slot *slot = host->slot[i];
2073 struct mmc_host *mmc = slot->mmc;
2074 struct mmc_request *mrq;
2075 int present;
2076
2077 present = dw_mci_get_cd(mmc);
2078 while (present != slot->last_detect_state) {
2079 dev_dbg(&slot->mmc->class_dev, "card %s\n",
2080 present ? "inserted" : "removed");
2081
2082 spin_lock_bh(&host->lock);
2083
2084 /* Card change detected */
2085 slot->last_detect_state = present;
2086
2087 /* Clean up queue if present */
2088 mrq = slot->mrq;
2089 if (mrq) {
2090 if (mrq == host->mrq) {
2091 host->data = NULL;
2092 host->cmd = NULL;
2093
2094 switch (host->state) {
2095 case STATE_IDLE:
2096 case STATE_WAITING_CMD11_DONE:
2097 break;
2098 case STATE_SENDING_CMD11:
2099 case STATE_SENDING_CMD:
2100 mrq->cmd->error = -ENOMEDIUM;
2101 if (!mrq->data)
2102 break;
2103 /* fall through */
2104 case STATE_SENDING_DATA:
2105 mrq->data->error = -ENOMEDIUM;
2106 dw_mci_stop_dma(host);
2107 break;
2108 case STATE_DATA_BUSY:
2109 case STATE_DATA_ERROR:
2110 if (mrq->data->error == -EINPROGRESS)
2111 mrq->data->error = -ENOMEDIUM;
2112 /* fall through */
2113 case STATE_SENDING_STOP:
2114 if (mrq->stop)
2115 mrq->stop->error = -ENOMEDIUM;
2116 break;
2117 }
2118
2119 dw_mci_request_end(host, mrq);
2120 } else {
2121 list_del(&slot->queue_node);
2122 mrq->cmd->error = -ENOMEDIUM;
2123 if (mrq->data)
2124 mrq->data->error = -ENOMEDIUM;
2125 if (mrq->stop)
2126 mrq->stop->error = -ENOMEDIUM;
2127
2128 spin_unlock(&host->lock);
2129 mmc_request_done(slot->mmc, mrq);
2130 spin_lock(&host->lock);
2131 }
2132 }
2133
2134 /* Power down slot */
2135 if (present == 0)
2136 dw_mci_reset(host);
2137
2138 spin_unlock_bh(&host->lock);
2139
2140 present = dw_mci_get_cd(mmc);
2141 }
2142
2143 mmc_detect_change(slot->mmc,
2144 msecs_to_jiffies(host->pdata->detect_delay_ms));
2145 }
2146 }
2147
2148 #ifdef CONFIG_OF
2149 /* given a slot id, find out the device node representing that slot */
dw_mci_of_find_slot_node(struct device * dev,u8 slot)2150 static struct device_node *dw_mci_of_find_slot_node(struct device *dev, u8 slot)
2151 {
2152 struct device_node *np;
2153 const __be32 *addr;
2154 int len;
2155
2156 if (!dev || !dev->of_node)
2157 return NULL;
2158
2159 for_each_child_of_node(dev->of_node, np) {
2160 addr = of_get_property(np, "reg", &len);
2161 if (!addr || (len < sizeof(int)))
2162 continue;
2163 if (be32_to_cpup(addr) == slot)
2164 return np;
2165 }
2166 return NULL;
2167 }
2168
2169 static struct dw_mci_of_slot_quirks {
2170 char *quirk;
2171 int id;
2172 } of_slot_quirks[] = {
2173 {
2174 .quirk = "disable-wp",
2175 .id = DW_MCI_SLOT_QUIRK_NO_WRITE_PROTECT,
2176 },
2177 };
2178
dw_mci_of_get_slot_quirks(struct device * dev,u8 slot)2179 static int dw_mci_of_get_slot_quirks(struct device *dev, u8 slot)
2180 {
2181 struct device_node *np = dw_mci_of_find_slot_node(dev, slot);
2182 int quirks = 0;
2183 int idx;
2184
2185 /* get quirks */
2186 for (idx = 0; idx < ARRAY_SIZE(of_slot_quirks); idx++)
2187 if (of_get_property(np, of_slot_quirks[idx].quirk, NULL)) {
2188 dev_warn(dev, "Slot quirk %s is deprecated\n",
2189 of_slot_quirks[idx].quirk);
2190 quirks |= of_slot_quirks[idx].id;
2191 }
2192
2193 return quirks;
2194 }
2195 #else /* CONFIG_OF */
dw_mci_of_get_slot_quirks(struct device * dev,u8 slot)2196 static int dw_mci_of_get_slot_quirks(struct device *dev, u8 slot)
2197 {
2198 return 0;
2199 }
2200 #endif /* CONFIG_OF */
2201
dw_mci_init_slot(struct dw_mci * host,unsigned int id)2202 static int dw_mci_init_slot(struct dw_mci *host, unsigned int id)
2203 {
2204 struct mmc_host *mmc;
2205 struct dw_mci_slot *slot;
2206 const struct dw_mci_drv_data *drv_data = host->drv_data;
2207 int ctrl_id, ret;
2208 u32 freq[2];
2209
2210 mmc = mmc_alloc_host(sizeof(struct dw_mci_slot), host->dev);
2211 if (!mmc)
2212 return -ENOMEM;
2213
2214 slot = mmc_priv(mmc);
2215 slot->id = id;
2216 slot->mmc = mmc;
2217 slot->host = host;
2218 host->slot[id] = slot;
2219
2220 slot->quirks = dw_mci_of_get_slot_quirks(host->dev, slot->id);
2221
2222 mmc->ops = &dw_mci_ops;
2223 if (of_property_read_u32_array(host->dev->of_node,
2224 "clock-freq-min-max", freq, 2)) {
2225 mmc->f_min = DW_MCI_FREQ_MIN;
2226 mmc->f_max = DW_MCI_FREQ_MAX;
2227 } else {
2228 mmc->f_min = freq[0];
2229 mmc->f_max = freq[1];
2230 }
2231
2232 /*if there are external regulators, get them*/
2233 ret = mmc_regulator_get_supply(mmc);
2234 if (ret == -EPROBE_DEFER)
2235 goto err_host_allocated;
2236
2237 if (!mmc->ocr_avail)
2238 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
2239
2240 if (host->pdata->caps)
2241 mmc->caps = host->pdata->caps;
2242
2243 if (host->pdata->pm_caps)
2244 mmc->pm_caps = host->pdata->pm_caps;
2245
2246 if (host->dev->of_node) {
2247 ctrl_id = of_alias_get_id(host->dev->of_node, "mshc");
2248 if (ctrl_id < 0)
2249 ctrl_id = 0;
2250 } else {
2251 ctrl_id = to_platform_device(host->dev)->id;
2252 }
2253 if (drv_data && drv_data->caps)
2254 mmc->caps |= drv_data->caps[ctrl_id];
2255
2256 if (host->pdata->caps2)
2257 mmc->caps2 = host->pdata->caps2;
2258
2259 ret = mmc_of_parse(mmc);
2260 if (ret)
2261 goto err_host_allocated;
2262
2263 if (host->pdata->blk_settings) {
2264 mmc->max_segs = host->pdata->blk_settings->max_segs;
2265 mmc->max_blk_size = host->pdata->blk_settings->max_blk_size;
2266 mmc->max_blk_count = host->pdata->blk_settings->max_blk_count;
2267 mmc->max_req_size = host->pdata->blk_settings->max_req_size;
2268 mmc->max_seg_size = host->pdata->blk_settings->max_seg_size;
2269 } else {
2270 /* Useful defaults if platform data is unset. */
2271 #ifdef CONFIG_MMC_DW_IDMAC
2272 mmc->max_segs = host->ring_size;
2273 mmc->max_blk_size = 65536;
2274 mmc->max_blk_count = host->ring_size;
2275 mmc->max_seg_size = 0x1000;
2276 mmc->max_req_size = mmc->max_seg_size * mmc->max_blk_count;
2277 #else
2278 mmc->max_segs = 64;
2279 mmc->max_blk_size = 65536; /* BLKSIZ is 16 bits */
2280 mmc->max_blk_count = 512;
2281 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
2282 mmc->max_seg_size = mmc->max_req_size;
2283 #endif /* CONFIG_MMC_DW_IDMAC */
2284 }
2285
2286 if (dw_mci_get_cd(mmc))
2287 set_bit(DW_MMC_CARD_PRESENT, &slot->flags);
2288 else
2289 clear_bit(DW_MMC_CARD_PRESENT, &slot->flags);
2290
2291 ret = mmc_add_host(mmc);
2292 if (ret)
2293 goto err_host_allocated;
2294
2295 #if defined(CONFIG_DEBUG_FS)
2296 dw_mci_init_debugfs(slot);
2297 #endif
2298
2299 /* Card initially undetected */
2300 slot->last_detect_state = 0;
2301
2302 return 0;
2303
2304 err_host_allocated:
2305 mmc_free_host(mmc);
2306 return ret;
2307 }
2308
dw_mci_cleanup_slot(struct dw_mci_slot * slot,unsigned int id)2309 static void dw_mci_cleanup_slot(struct dw_mci_slot *slot, unsigned int id)
2310 {
2311 /* Debugfs stuff is cleaned up by mmc core */
2312 mmc_remove_host(slot->mmc);
2313 slot->host->slot[id] = NULL;
2314 mmc_free_host(slot->mmc);
2315 }
2316
dw_mci_init_dma(struct dw_mci * host)2317 static void dw_mci_init_dma(struct dw_mci *host)
2318 {
2319 /* Alloc memory for sg translation */
2320 host->sg_cpu = dmam_alloc_coherent(host->dev, PAGE_SIZE,
2321 &host->sg_dma, GFP_KERNEL);
2322 if (!host->sg_cpu) {
2323 dev_err(host->dev, "%s: could not alloc DMA memory\n",
2324 __func__);
2325 goto no_dma;
2326 }
2327
2328 /* Determine which DMA interface to use */
2329 #ifdef CONFIG_MMC_DW_IDMAC
2330 host->dma_ops = &dw_mci_idmac_ops;
2331 dev_info(host->dev, "Using internal DMA controller.\n");
2332 #endif
2333
2334 if (!host->dma_ops)
2335 goto no_dma;
2336
2337 if (host->dma_ops->init && host->dma_ops->start &&
2338 host->dma_ops->stop && host->dma_ops->cleanup) {
2339 if (host->dma_ops->init(host)) {
2340 dev_err(host->dev, "%s: Unable to initialize "
2341 "DMA Controller.\n", __func__);
2342 goto no_dma;
2343 }
2344 } else {
2345 dev_err(host->dev, "DMA initialization not found.\n");
2346 goto no_dma;
2347 }
2348
2349 host->use_dma = 1;
2350 return;
2351
2352 no_dma:
2353 dev_info(host->dev, "Using PIO mode.\n");
2354 host->use_dma = 0;
2355 return;
2356 }
2357
dw_mci_ctrl_reset(struct dw_mci * host,u32 reset)2358 static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset)
2359 {
2360 unsigned long timeout = jiffies + msecs_to_jiffies(500);
2361 u32 ctrl;
2362
2363 ctrl = mci_readl(host, CTRL);
2364 ctrl |= reset;
2365 mci_writel(host, CTRL, ctrl);
2366
2367 /* wait till resets clear */
2368 do {
2369 ctrl = mci_readl(host, CTRL);
2370 if (!(ctrl & reset))
2371 return true;
2372 } while (time_before(jiffies, timeout));
2373
2374 dev_err(host->dev,
2375 "Timeout resetting block (ctrl reset %#x)\n",
2376 ctrl & reset);
2377
2378 return false;
2379 }
2380
dw_mci_reset(struct dw_mci * host)2381 static bool dw_mci_reset(struct dw_mci *host)
2382 {
2383 u32 flags = SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET;
2384 bool ret = false;
2385
2386 /*
2387 * Reseting generates a block interrupt, hence setting
2388 * the scatter-gather pointer to NULL.
2389 */
2390 if (host->sg) {
2391 sg_miter_stop(&host->sg_miter);
2392 host->sg = NULL;
2393 }
2394
2395 if (host->use_dma)
2396 flags |= SDMMC_CTRL_DMA_RESET;
2397
2398 if (dw_mci_ctrl_reset(host, flags)) {
2399 /*
2400 * In all cases we clear the RAWINTS register to clear any
2401 * interrupts.
2402 */
2403 mci_writel(host, RINTSTS, 0xFFFFFFFF);
2404
2405 /* if using dma we wait for dma_req to clear */
2406 if (host->use_dma) {
2407 unsigned long timeout = jiffies + msecs_to_jiffies(500);
2408 u32 status;
2409 do {
2410 status = mci_readl(host, STATUS);
2411 if (!(status & SDMMC_STATUS_DMA_REQ))
2412 break;
2413 cpu_relax();
2414 } while (time_before(jiffies, timeout));
2415
2416 if (status & SDMMC_STATUS_DMA_REQ) {
2417 dev_err(host->dev,
2418 "%s: Timeout waiting for dma_req to "
2419 "clear during reset\n", __func__);
2420 goto ciu_out;
2421 }
2422
2423 /* when using DMA next we reset the fifo again */
2424 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_FIFO_RESET))
2425 goto ciu_out;
2426 }
2427 } else {
2428 /* if the controller reset bit did clear, then set clock regs */
2429 if (!(mci_readl(host, CTRL) & SDMMC_CTRL_RESET)) {
2430 dev_err(host->dev, "%s: fifo/dma reset bits didn't "
2431 "clear but ciu was reset, doing clock update\n",
2432 __func__);
2433 goto ciu_out;
2434 }
2435 }
2436
2437 #if IS_ENABLED(CONFIG_MMC_DW_IDMAC)
2438 /* It is also recommended that we reset and reprogram idmac */
2439 dw_mci_idmac_reset(host);
2440 #endif
2441
2442 ret = true;
2443
2444 ciu_out:
2445 /* After a CTRL reset we need to have CIU set clock registers */
2446 mci_send_cmd(host->cur_slot, SDMMC_CMD_UPD_CLK, 0);
2447
2448 return ret;
2449 }
2450
2451 #ifdef CONFIG_OF
2452 static struct dw_mci_of_quirks {
2453 char *quirk;
2454 int id;
2455 } of_quirks[] = {
2456 {
2457 .quirk = "broken-cd",
2458 .id = DW_MCI_QUIRK_BROKEN_CARD_DETECTION,
2459 }, {
2460 .quirk = "disable-wp",
2461 .id = DW_MCI_QUIRK_NO_WRITE_PROTECT,
2462 },
2463 };
2464
dw_mci_parse_dt(struct dw_mci * host)2465 static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
2466 {
2467 struct dw_mci_board *pdata;
2468 struct device *dev = host->dev;
2469 struct device_node *np = dev->of_node;
2470 const struct dw_mci_drv_data *drv_data = host->drv_data;
2471 int idx, ret;
2472 u32 clock_frequency;
2473
2474 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
2475 if (!pdata) {
2476 dev_err(dev, "could not allocate memory for pdata\n");
2477 return ERR_PTR(-ENOMEM);
2478 }
2479
2480 /* find out number of slots supported */
2481 if (of_property_read_u32(dev->of_node, "num-slots",
2482 &pdata->num_slots)) {
2483 dev_info(dev, "num-slots property not found, "
2484 "assuming 1 slot is available\n");
2485 pdata->num_slots = 1;
2486 }
2487
2488 /* get quirks */
2489 for (idx = 0; idx < ARRAY_SIZE(of_quirks); idx++)
2490 if (of_get_property(np, of_quirks[idx].quirk, NULL))
2491 pdata->quirks |= of_quirks[idx].id;
2492
2493 if (of_property_read_u32(np, "fifo-depth", &pdata->fifo_depth))
2494 dev_info(dev, "fifo-depth property not found, using "
2495 "value of FIFOTH register as default\n");
2496
2497 of_property_read_u32(np, "card-detect-delay", &pdata->detect_delay_ms);
2498
2499 if (!of_property_read_u32(np, "clock-frequency", &clock_frequency))
2500 pdata->bus_hz = clock_frequency;
2501
2502 if (drv_data && drv_data->parse_dt) {
2503 ret = drv_data->parse_dt(host);
2504 if (ret)
2505 return ERR_PTR(ret);
2506 }
2507
2508 if (of_find_property(np, "supports-highspeed", NULL))
2509 pdata->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
2510
2511 return pdata;
2512 }
2513
2514 #else /* CONFIG_OF */
dw_mci_parse_dt(struct dw_mci * host)2515 static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
2516 {
2517 return ERR_PTR(-EINVAL);
2518 }
2519 #endif /* CONFIG_OF */
2520
dw_mci_probe(struct dw_mci * host)2521 int dw_mci_probe(struct dw_mci *host)
2522 {
2523 const struct dw_mci_drv_data *drv_data = host->drv_data;
2524 int width, i, ret = 0;
2525 u32 fifo_size;
2526 int init_slots = 0;
2527
2528 if (!host->pdata) {
2529 host->pdata = dw_mci_parse_dt(host);
2530 if (IS_ERR(host->pdata)) {
2531 dev_err(host->dev, "platform data not available\n");
2532 return -EINVAL;
2533 }
2534 }
2535
2536 if (host->pdata->num_slots > 1) {
2537 dev_err(host->dev,
2538 "Platform data must supply num_slots.\n");
2539 return -ENODEV;
2540 }
2541
2542 host->biu_clk = devm_clk_get(host->dev, "biu");
2543 if (IS_ERR(host->biu_clk)) {
2544 dev_dbg(host->dev, "biu clock not available\n");
2545 } else {
2546 ret = clk_prepare_enable(host->biu_clk);
2547 if (ret) {
2548 dev_err(host->dev, "failed to enable biu clock\n");
2549 return ret;
2550 }
2551 }
2552
2553 host->ciu_clk = devm_clk_get(host->dev, "ciu");
2554 if (IS_ERR(host->ciu_clk)) {
2555 dev_dbg(host->dev, "ciu clock not available\n");
2556 host->bus_hz = host->pdata->bus_hz;
2557 } else {
2558 ret = clk_prepare_enable(host->ciu_clk);
2559 if (ret) {
2560 dev_err(host->dev, "failed to enable ciu clock\n");
2561 goto err_clk_biu;
2562 }
2563
2564 if (host->pdata->bus_hz) {
2565 ret = clk_set_rate(host->ciu_clk, host->pdata->bus_hz);
2566 if (ret)
2567 dev_warn(host->dev,
2568 "Unable to set bus rate to %uHz\n",
2569 host->pdata->bus_hz);
2570 }
2571 host->bus_hz = clk_get_rate(host->ciu_clk);
2572 }
2573
2574 if (!host->bus_hz) {
2575 dev_err(host->dev,
2576 "Platform data must supply bus speed\n");
2577 ret = -ENODEV;
2578 goto err_clk_ciu;
2579 }
2580
2581 if (drv_data && drv_data->init) {
2582 ret = drv_data->init(host);
2583 if (ret) {
2584 dev_err(host->dev,
2585 "implementation specific init failed\n");
2586 goto err_clk_ciu;
2587 }
2588 }
2589
2590 if (drv_data && drv_data->setup_clock) {
2591 ret = drv_data->setup_clock(host);
2592 if (ret) {
2593 dev_err(host->dev,
2594 "implementation specific clock setup failed\n");
2595 goto err_clk_ciu;
2596 }
2597 }
2598
2599 host->quirks = host->pdata->quirks;
2600
2601 spin_lock_init(&host->lock);
2602 INIT_LIST_HEAD(&host->queue);
2603
2604 /*
2605 * Get the host data width - this assumes that HCON has been set with
2606 * the correct values.
2607 */
2608 i = (mci_readl(host, HCON) >> 7) & 0x7;
2609 if (!i) {
2610 host->push_data = dw_mci_push_data16;
2611 host->pull_data = dw_mci_pull_data16;
2612 width = 16;
2613 host->data_shift = 1;
2614 } else if (i == 2) {
2615 host->push_data = dw_mci_push_data64;
2616 host->pull_data = dw_mci_pull_data64;
2617 width = 64;
2618 host->data_shift = 3;
2619 } else {
2620 /* Check for a reserved value, and warn if it is */
2621 WARN((i != 1),
2622 "HCON reports a reserved host data width!\n"
2623 "Defaulting to 32-bit access.\n");
2624 host->push_data = dw_mci_push_data32;
2625 host->pull_data = dw_mci_pull_data32;
2626 width = 32;
2627 host->data_shift = 2;
2628 }
2629
2630 /* Reset all blocks */
2631 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS))
2632 return -ENODEV;
2633
2634 host->dma_ops = host->pdata->dma_ops;
2635 dw_mci_init_dma(host);
2636
2637 /* Clear the interrupts for the host controller */
2638 mci_writel(host, RINTSTS, 0xFFFFFFFF);
2639 mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
2640
2641 /* Put in max timeout */
2642 mci_writel(host, TMOUT, 0xFFFFFFFF);
2643
2644 /*
2645 * FIFO threshold settings RxMark = fifo_size / 2 - 1,
2646 * Tx Mark = fifo_size / 2 DMA Size = 8
2647 */
2648 if (!host->pdata->fifo_depth) {
2649 /*
2650 * Power-on value of RX_WMark is FIFO_DEPTH-1, but this may
2651 * have been overwritten by the bootloader, just like we're
2652 * about to do, so if you know the value for your hardware, you
2653 * should put it in the platform data.
2654 */
2655 fifo_size = mci_readl(host, FIFOTH);
2656 fifo_size = 1 + ((fifo_size >> 16) & 0xfff);
2657 } else {
2658 fifo_size = host->pdata->fifo_depth;
2659 }
2660 host->fifo_depth = fifo_size;
2661 host->fifoth_val =
2662 SDMMC_SET_FIFOTH(0x2, fifo_size / 2 - 1, fifo_size / 2);
2663 mci_writel(host, FIFOTH, host->fifoth_val);
2664
2665 /* disable clock to CIU */
2666 mci_writel(host, CLKENA, 0);
2667 mci_writel(host, CLKSRC, 0);
2668
2669 /*
2670 * In 2.40a spec, Data offset is changed.
2671 * Need to check the version-id and set data-offset for DATA register.
2672 */
2673 host->verid = SDMMC_GET_VERID(mci_readl(host, VERID));
2674 dev_info(host->dev, "Version ID is %04x\n", host->verid);
2675
2676 if (host->verid < DW_MMC_240A)
2677 host->data_offset = DATA_OFFSET;
2678 else
2679 host->data_offset = DATA_240A_OFFSET;
2680
2681 tasklet_init(&host->tasklet, dw_mci_tasklet_func, (unsigned long)host);
2682 host->card_workqueue = alloc_workqueue("dw-mci-card",
2683 WQ_MEM_RECLAIM, 1);
2684 if (!host->card_workqueue) {
2685 ret = -ENOMEM;
2686 goto err_dmaunmap;
2687 }
2688 INIT_WORK(&host->card_work, dw_mci_work_routine_card);
2689 ret = devm_request_irq(host->dev, host->irq, dw_mci_interrupt,
2690 host->irq_flags, "dw-mci", host);
2691 if (ret)
2692 goto err_workqueue;
2693
2694 if (host->pdata->num_slots)
2695 host->num_slots = host->pdata->num_slots;
2696 else
2697 host->num_slots = ((mci_readl(host, HCON) >> 1) & 0x1F) + 1;
2698
2699 /*
2700 * Enable interrupts for command done, data over, data empty, card det,
2701 * receive ready and error such as transmit, receive timeout, crc error
2702 */
2703 mci_writel(host, RINTSTS, 0xFFFFFFFF);
2704 mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
2705 SDMMC_INT_TXDR | SDMMC_INT_RXDR |
2706 DW_MCI_ERROR_FLAGS | SDMMC_INT_CD);
2707 mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE); /* Enable mci interrupt */
2708
2709 dev_info(host->dev, "DW MMC controller at irq %d, "
2710 "%d bit host data width, "
2711 "%u deep fifo\n",
2712 host->irq, width, fifo_size);
2713
2714 /* We need at least one slot to succeed */
2715 for (i = 0; i < host->num_slots; i++) {
2716 ret = dw_mci_init_slot(host, i);
2717 if (ret)
2718 dev_dbg(host->dev, "slot %d init failed\n", i);
2719 else
2720 init_slots++;
2721 }
2722
2723 if (init_slots) {
2724 dev_info(host->dev, "%d slots initialized\n", init_slots);
2725 } else {
2726 dev_dbg(host->dev, "attempted to initialize %d slots, "
2727 "but failed on all\n", host->num_slots);
2728 goto err_workqueue;
2729 }
2730
2731 if (host->quirks & DW_MCI_QUIRK_IDMAC_DTO)
2732 dev_info(host->dev, "Internal DMAC interrupt fix enabled.\n");
2733
2734 return 0;
2735
2736 err_workqueue:
2737 destroy_workqueue(host->card_workqueue);
2738
2739 err_dmaunmap:
2740 if (host->use_dma && host->dma_ops->exit)
2741 host->dma_ops->exit(host);
2742
2743 err_clk_ciu:
2744 if (!IS_ERR(host->ciu_clk))
2745 clk_disable_unprepare(host->ciu_clk);
2746
2747 err_clk_biu:
2748 if (!IS_ERR(host->biu_clk))
2749 clk_disable_unprepare(host->biu_clk);
2750
2751 return ret;
2752 }
2753 EXPORT_SYMBOL(dw_mci_probe);
2754
dw_mci_remove(struct dw_mci * host)2755 void dw_mci_remove(struct dw_mci *host)
2756 {
2757 int i;
2758
2759 mci_writel(host, RINTSTS, 0xFFFFFFFF);
2760 mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
2761
2762 for (i = 0; i < host->num_slots; i++) {
2763 dev_dbg(host->dev, "remove slot %d\n", i);
2764 if (host->slot[i])
2765 dw_mci_cleanup_slot(host->slot[i], i);
2766 }
2767
2768 /* disable clock to CIU */
2769 mci_writel(host, CLKENA, 0);
2770 mci_writel(host, CLKSRC, 0);
2771
2772 destroy_workqueue(host->card_workqueue);
2773
2774 if (host->use_dma && host->dma_ops->exit)
2775 host->dma_ops->exit(host);
2776
2777 if (!IS_ERR(host->ciu_clk))
2778 clk_disable_unprepare(host->ciu_clk);
2779
2780 if (!IS_ERR(host->biu_clk))
2781 clk_disable_unprepare(host->biu_clk);
2782 }
2783 EXPORT_SYMBOL(dw_mci_remove);
2784
2785
2786
2787 #ifdef CONFIG_PM_SLEEP
2788 /*
2789 * TODO: we should probably disable the clock to the card in the suspend path.
2790 */
dw_mci_suspend(struct dw_mci * host)2791 int dw_mci_suspend(struct dw_mci *host)
2792 {
2793 return 0;
2794 }
2795 EXPORT_SYMBOL(dw_mci_suspend);
2796
dw_mci_resume(struct dw_mci * host)2797 int dw_mci_resume(struct dw_mci *host)
2798 {
2799 int i, ret;
2800
2801 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS)) {
2802 ret = -ENODEV;
2803 return ret;
2804 }
2805
2806 if (host->use_dma && host->dma_ops->init)
2807 host->dma_ops->init(host);
2808
2809 /*
2810 * Restore the initial value at FIFOTH register
2811 * And Invalidate the prev_blksz with zero
2812 */
2813 mci_writel(host, FIFOTH, host->fifoth_val);
2814 host->prev_blksz = 0;
2815
2816 /* Put in max timeout */
2817 mci_writel(host, TMOUT, 0xFFFFFFFF);
2818
2819 mci_writel(host, RINTSTS, 0xFFFFFFFF);
2820 mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
2821 SDMMC_INT_TXDR | SDMMC_INT_RXDR |
2822 DW_MCI_ERROR_FLAGS | SDMMC_INT_CD);
2823 mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE);
2824
2825 for (i = 0; i < host->num_slots; i++) {
2826 struct dw_mci_slot *slot = host->slot[i];
2827 if (!slot)
2828 continue;
2829 if (slot->mmc->pm_flags & MMC_PM_KEEP_POWER) {
2830 dw_mci_set_ios(slot->mmc, &slot->mmc->ios);
2831 dw_mci_setup_bus(slot, true);
2832 }
2833 }
2834 return 0;
2835 }
2836 EXPORT_SYMBOL(dw_mci_resume);
2837 #endif /* CONFIG_PM_SLEEP */
2838
dw_mci_init(void)2839 static int __init dw_mci_init(void)
2840 {
2841 pr_info("Synopsys Designware Multimedia Card Interface Driver\n");
2842 return 0;
2843 }
2844
dw_mci_exit(void)2845 static void __exit dw_mci_exit(void)
2846 {
2847 }
2848
2849 module_init(dw_mci_init);
2850 module_exit(dw_mci_exit);
2851
2852 MODULE_DESCRIPTION("DW Multimedia Card Interface driver");
2853 MODULE_AUTHOR("NXP Semiconductor VietNam");
2854 MODULE_AUTHOR("Imagination Technologies Ltd");
2855 MODULE_LICENSE("GPL v2");
2856