1 /*
2 * linux/drivers/mmc/s3cmci.h - Samsung S3C MCI driver
3 *
4 * Copyright (C) 2004-2006 maintech GmbH, Thomas Kleffel <tk@maintech.de>
5 *
6 * Current driver maintained by Ben Dooks and Simtec Electronics
7 * Copyright (C) 2008 Simtec Electronics <ben-linux@fluff.org>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14 #include <linux/module.h>
15 #include <linux/dmaengine.h>
16 #include <linux/dma-mapping.h>
17 #include <linux/clk.h>
18 #include <linux/mmc/host.h>
19 #include <linux/platform_device.h>
20 #include <linux/cpufreq.h>
21 #include <linux/debugfs.h>
22 #include <linux/seq_file.h>
23 #include <linux/gpio.h>
24 #include <linux/interrupt.h>
25 #include <linux/irq.h>
26 #include <linux/io.h>
27
28 #include <plat/gpio-cfg.h>
29 #include <mach/dma.h>
30 #include <mach/gpio-samsung.h>
31
32 #include <linux/platform_data/dma-s3c24xx.h>
33 #include <linux/platform_data/mmc-s3cmci.h>
34
35 #include "s3cmci.h"
36
37 #define DRIVER_NAME "s3c-mci"
38
39 #define S3C2410_SDICON (0x00)
40 #define S3C2410_SDIPRE (0x04)
41 #define S3C2410_SDICMDARG (0x08)
42 #define S3C2410_SDICMDCON (0x0C)
43 #define S3C2410_SDICMDSTAT (0x10)
44 #define S3C2410_SDIRSP0 (0x14)
45 #define S3C2410_SDIRSP1 (0x18)
46 #define S3C2410_SDIRSP2 (0x1C)
47 #define S3C2410_SDIRSP3 (0x20)
48 #define S3C2410_SDITIMER (0x24)
49 #define S3C2410_SDIBSIZE (0x28)
50 #define S3C2410_SDIDCON (0x2C)
51 #define S3C2410_SDIDCNT (0x30)
52 #define S3C2410_SDIDSTA (0x34)
53 #define S3C2410_SDIFSTA (0x38)
54
55 #define S3C2410_SDIDATA (0x3C)
56 #define S3C2410_SDIIMSK (0x40)
57
58 #define S3C2440_SDIDATA (0x40)
59 #define S3C2440_SDIIMSK (0x3C)
60
61 #define S3C2440_SDICON_SDRESET (1 << 8)
62 #define S3C2410_SDICON_SDIOIRQ (1 << 3)
63 #define S3C2410_SDICON_FIFORESET (1 << 1)
64 #define S3C2410_SDICON_CLOCKTYPE (1 << 0)
65
66 #define S3C2410_SDICMDCON_LONGRSP (1 << 10)
67 #define S3C2410_SDICMDCON_WAITRSP (1 << 9)
68 #define S3C2410_SDICMDCON_CMDSTART (1 << 8)
69 #define S3C2410_SDICMDCON_SENDERHOST (1 << 6)
70 #define S3C2410_SDICMDCON_INDEX (0x3f)
71
72 #define S3C2410_SDICMDSTAT_CRCFAIL (1 << 12)
73 #define S3C2410_SDICMDSTAT_CMDSENT (1 << 11)
74 #define S3C2410_SDICMDSTAT_CMDTIMEOUT (1 << 10)
75 #define S3C2410_SDICMDSTAT_RSPFIN (1 << 9)
76
77 #define S3C2440_SDIDCON_DS_WORD (2 << 22)
78 #define S3C2410_SDIDCON_TXAFTERRESP (1 << 20)
79 #define S3C2410_SDIDCON_RXAFTERCMD (1 << 19)
80 #define S3C2410_SDIDCON_BLOCKMODE (1 << 17)
81 #define S3C2410_SDIDCON_WIDEBUS (1 << 16)
82 #define S3C2410_SDIDCON_DMAEN (1 << 15)
83 #define S3C2410_SDIDCON_STOP (1 << 14)
84 #define S3C2440_SDIDCON_DATSTART (1 << 14)
85
86 #define S3C2410_SDIDCON_XFER_RXSTART (2 << 12)
87 #define S3C2410_SDIDCON_XFER_TXSTART (3 << 12)
88
89 #define S3C2410_SDIDCON_BLKNUM_MASK (0xFFF)
90
91 #define S3C2410_SDIDSTA_SDIOIRQDETECT (1 << 9)
92 #define S3C2410_SDIDSTA_FIFOFAIL (1 << 8)
93 #define S3C2410_SDIDSTA_CRCFAIL (1 << 7)
94 #define S3C2410_SDIDSTA_RXCRCFAIL (1 << 6)
95 #define S3C2410_SDIDSTA_DATATIMEOUT (1 << 5)
96 #define S3C2410_SDIDSTA_XFERFINISH (1 << 4)
97 #define S3C2410_SDIDSTA_TXDATAON (1 << 1)
98 #define S3C2410_SDIDSTA_RXDATAON (1 << 0)
99
100 #define S3C2440_SDIFSTA_FIFORESET (1 << 16)
101 #define S3C2440_SDIFSTA_FIFOFAIL (3 << 14)
102 #define S3C2410_SDIFSTA_TFDET (1 << 13)
103 #define S3C2410_SDIFSTA_RFDET (1 << 12)
104 #define S3C2410_SDIFSTA_COUNTMASK (0x7f)
105
106 #define S3C2410_SDIIMSK_RESPONSECRC (1 << 17)
107 #define S3C2410_SDIIMSK_CMDSENT (1 << 16)
108 #define S3C2410_SDIIMSK_CMDTIMEOUT (1 << 15)
109 #define S3C2410_SDIIMSK_RESPONSEND (1 << 14)
110 #define S3C2410_SDIIMSK_SDIOIRQ (1 << 12)
111 #define S3C2410_SDIIMSK_FIFOFAIL (1 << 11)
112 #define S3C2410_SDIIMSK_CRCSTATUS (1 << 10)
113 #define S3C2410_SDIIMSK_DATACRC (1 << 9)
114 #define S3C2410_SDIIMSK_DATATIMEOUT (1 << 8)
115 #define S3C2410_SDIIMSK_DATAFINISH (1 << 7)
116 #define S3C2410_SDIIMSK_TXFIFOHALF (1 << 4)
117 #define S3C2410_SDIIMSK_RXFIFOLAST (1 << 2)
118 #define S3C2410_SDIIMSK_RXFIFOHALF (1 << 0)
119
120 enum dbg_channels {
121 dbg_err = (1 << 0),
122 dbg_debug = (1 << 1),
123 dbg_info = (1 << 2),
124 dbg_irq = (1 << 3),
125 dbg_sg = (1 << 4),
126 dbg_dma = (1 << 5),
127 dbg_pio = (1 << 6),
128 dbg_fail = (1 << 7),
129 dbg_conf = (1 << 8),
130 };
131
132 static const int dbgmap_err = dbg_fail;
133 static const int dbgmap_info = dbg_info | dbg_conf;
134 static const int dbgmap_debug = dbg_err | dbg_debug;
135
136 #define dbg(host, channels, args...) \
137 do { \
138 if (dbgmap_err & channels) \
139 dev_err(&host->pdev->dev, args); \
140 else if (dbgmap_info & channels) \
141 dev_info(&host->pdev->dev, args); \
142 else if (dbgmap_debug & channels) \
143 dev_dbg(&host->pdev->dev, args); \
144 } while (0)
145
146 static void finalize_request(struct s3cmci_host *host);
147 static void s3cmci_send_request(struct mmc_host *mmc);
148 static void s3cmci_reset(struct s3cmci_host *host);
149
150 #ifdef CONFIG_MMC_DEBUG
151
dbg_dumpregs(struct s3cmci_host * host,char * prefix)152 static void dbg_dumpregs(struct s3cmci_host *host, char *prefix)
153 {
154 u32 con, pre, cmdarg, cmdcon, cmdsta, r0, r1, r2, r3, timer, bsize;
155 u32 datcon, datcnt, datsta, fsta, imask;
156
157 con = readl(host->base + S3C2410_SDICON);
158 pre = readl(host->base + S3C2410_SDIPRE);
159 cmdarg = readl(host->base + S3C2410_SDICMDARG);
160 cmdcon = readl(host->base + S3C2410_SDICMDCON);
161 cmdsta = readl(host->base + S3C2410_SDICMDSTAT);
162 r0 = readl(host->base + S3C2410_SDIRSP0);
163 r1 = readl(host->base + S3C2410_SDIRSP1);
164 r2 = readl(host->base + S3C2410_SDIRSP2);
165 r3 = readl(host->base + S3C2410_SDIRSP3);
166 timer = readl(host->base + S3C2410_SDITIMER);
167 bsize = readl(host->base + S3C2410_SDIBSIZE);
168 datcon = readl(host->base + S3C2410_SDIDCON);
169 datcnt = readl(host->base + S3C2410_SDIDCNT);
170 datsta = readl(host->base + S3C2410_SDIDSTA);
171 fsta = readl(host->base + S3C2410_SDIFSTA);
172 imask = readl(host->base + host->sdiimsk);
173
174 dbg(host, dbg_debug, "%s CON:[%08x] PRE:[%08x] TMR:[%08x]\n",
175 prefix, con, pre, timer);
176
177 dbg(host, dbg_debug, "%s CCON:[%08x] CARG:[%08x] CSTA:[%08x]\n",
178 prefix, cmdcon, cmdarg, cmdsta);
179
180 dbg(host, dbg_debug, "%s DCON:[%08x] FSTA:[%08x]"
181 " DSTA:[%08x] DCNT:[%08x]\n",
182 prefix, datcon, fsta, datsta, datcnt);
183
184 dbg(host, dbg_debug, "%s R0:[%08x] R1:[%08x]"
185 " R2:[%08x] R3:[%08x]\n",
186 prefix, r0, r1, r2, r3);
187 }
188
prepare_dbgmsg(struct s3cmci_host * host,struct mmc_command * cmd,int stop)189 static void prepare_dbgmsg(struct s3cmci_host *host, struct mmc_command *cmd,
190 int stop)
191 {
192 snprintf(host->dbgmsg_cmd, 300,
193 "#%u%s op:%i arg:0x%08x flags:0x08%x retries:%u",
194 host->ccnt, (stop ? " (STOP)" : ""),
195 cmd->opcode, cmd->arg, cmd->flags, cmd->retries);
196
197 if (cmd->data) {
198 snprintf(host->dbgmsg_dat, 300,
199 "#%u bsize:%u blocks:%u bytes:%u",
200 host->dcnt, cmd->data->blksz,
201 cmd->data->blocks,
202 cmd->data->blocks * cmd->data->blksz);
203 } else {
204 host->dbgmsg_dat[0] = '\0';
205 }
206 }
207
dbg_dumpcmd(struct s3cmci_host * host,struct mmc_command * cmd,int fail)208 static void dbg_dumpcmd(struct s3cmci_host *host, struct mmc_command *cmd,
209 int fail)
210 {
211 unsigned int dbglvl = fail ? dbg_fail : dbg_debug;
212
213 if (!cmd)
214 return;
215
216 if (cmd->error == 0) {
217 dbg(host, dbglvl, "CMD[OK] %s R0:0x%08x\n",
218 host->dbgmsg_cmd, cmd->resp[0]);
219 } else {
220 dbg(host, dbglvl, "CMD[ERR %i] %s Status:%s\n",
221 cmd->error, host->dbgmsg_cmd, host->status);
222 }
223
224 if (!cmd->data)
225 return;
226
227 if (cmd->data->error == 0) {
228 dbg(host, dbglvl, "DAT[OK] %s\n", host->dbgmsg_dat);
229 } else {
230 dbg(host, dbglvl, "DAT[ERR %i] %s DCNT:0x%08x\n",
231 cmd->data->error, host->dbgmsg_dat,
232 readl(host->base + S3C2410_SDIDCNT));
233 }
234 }
235 #else
dbg_dumpcmd(struct s3cmci_host * host,struct mmc_command * cmd,int fail)236 static void dbg_dumpcmd(struct s3cmci_host *host,
237 struct mmc_command *cmd, int fail) { }
238
prepare_dbgmsg(struct s3cmci_host * host,struct mmc_command * cmd,int stop)239 static void prepare_dbgmsg(struct s3cmci_host *host, struct mmc_command *cmd,
240 int stop) { }
241
dbg_dumpregs(struct s3cmci_host * host,char * prefix)242 static void dbg_dumpregs(struct s3cmci_host *host, char *prefix) { }
243
244 #endif /* CONFIG_MMC_DEBUG */
245
246 /**
247 * s3cmci_host_usedma - return whether the host is using dma or pio
248 * @host: The host state
249 *
250 * Return true if the host is using DMA to transfer data, else false
251 * to use PIO mode. Will return static data depending on the driver
252 * configuration.
253 */
s3cmci_host_usedma(struct s3cmci_host * host)254 static inline bool s3cmci_host_usedma(struct s3cmci_host *host)
255 {
256 #ifdef CONFIG_MMC_S3C_PIO
257 return false;
258 #else /* CONFIG_MMC_S3C_DMA */
259 return true;
260 #endif
261 }
262
enable_imask(struct s3cmci_host * host,u32 imask)263 static inline u32 enable_imask(struct s3cmci_host *host, u32 imask)
264 {
265 u32 newmask;
266
267 newmask = readl(host->base + host->sdiimsk);
268 newmask |= imask;
269
270 writel(newmask, host->base + host->sdiimsk);
271
272 return newmask;
273 }
274
disable_imask(struct s3cmci_host * host,u32 imask)275 static inline u32 disable_imask(struct s3cmci_host *host, u32 imask)
276 {
277 u32 newmask;
278
279 newmask = readl(host->base + host->sdiimsk);
280 newmask &= ~imask;
281
282 writel(newmask, host->base + host->sdiimsk);
283
284 return newmask;
285 }
286
clear_imask(struct s3cmci_host * host)287 static inline void clear_imask(struct s3cmci_host *host)
288 {
289 u32 mask = readl(host->base + host->sdiimsk);
290
291 /* preserve the SDIO IRQ mask state */
292 mask &= S3C2410_SDIIMSK_SDIOIRQ;
293 writel(mask, host->base + host->sdiimsk);
294 }
295
296 /**
297 * s3cmci_check_sdio_irq - test whether the SDIO IRQ is being signalled
298 * @host: The host to check.
299 *
300 * Test to see if the SDIO interrupt is being signalled in case the
301 * controller has failed to re-detect a card interrupt. Read GPE8 and
302 * see if it is low and if so, signal a SDIO interrupt.
303 *
304 * This is currently called if a request is finished (we assume that the
305 * bus is now idle) and when the SDIO IRQ is enabled in case the IRQ is
306 * already being indicated.
307 */
s3cmci_check_sdio_irq(struct s3cmci_host * host)308 static void s3cmci_check_sdio_irq(struct s3cmci_host *host)
309 {
310 if (host->sdio_irqen) {
311 if (gpio_get_value(S3C2410_GPE(8)) == 0) {
312 pr_debug("%s: signalling irq\n", __func__);
313 mmc_signal_sdio_irq(host->mmc);
314 }
315 }
316 }
317
get_data_buffer(struct s3cmci_host * host,u32 * bytes,u32 ** pointer)318 static inline int get_data_buffer(struct s3cmci_host *host,
319 u32 *bytes, u32 **pointer)
320 {
321 struct scatterlist *sg;
322
323 if (host->pio_active == XFER_NONE)
324 return -EINVAL;
325
326 if ((!host->mrq) || (!host->mrq->data))
327 return -EINVAL;
328
329 if (host->pio_sgptr >= host->mrq->data->sg_len) {
330 dbg(host, dbg_debug, "no more buffers (%i/%i)\n",
331 host->pio_sgptr, host->mrq->data->sg_len);
332 return -EBUSY;
333 }
334 sg = &host->mrq->data->sg[host->pio_sgptr];
335
336 *bytes = sg->length;
337 *pointer = sg_virt(sg);
338
339 host->pio_sgptr++;
340
341 dbg(host, dbg_sg, "new buffer (%i/%i)\n",
342 host->pio_sgptr, host->mrq->data->sg_len);
343
344 return 0;
345 }
346
fifo_count(struct s3cmci_host * host)347 static inline u32 fifo_count(struct s3cmci_host *host)
348 {
349 u32 fifostat = readl(host->base + S3C2410_SDIFSTA);
350
351 fifostat &= S3C2410_SDIFSTA_COUNTMASK;
352 return fifostat;
353 }
354
fifo_free(struct s3cmci_host * host)355 static inline u32 fifo_free(struct s3cmci_host *host)
356 {
357 u32 fifostat = readl(host->base + S3C2410_SDIFSTA);
358
359 fifostat &= S3C2410_SDIFSTA_COUNTMASK;
360 return 63 - fifostat;
361 }
362
363 /**
364 * s3cmci_enable_irq - enable IRQ, after having disabled it.
365 * @host: The device state.
366 * @more: True if more IRQs are expected from transfer.
367 *
368 * Enable the main IRQ if needed after it has been disabled.
369 *
370 * The IRQ can be one of the following states:
371 * - disabled during IDLE
372 * - disabled whilst processing data
373 * - enabled during transfer
374 * - enabled whilst awaiting SDIO interrupt detection
375 */
s3cmci_enable_irq(struct s3cmci_host * host,bool more)376 static void s3cmci_enable_irq(struct s3cmci_host *host, bool more)
377 {
378 unsigned long flags;
379 bool enable = false;
380
381 local_irq_save(flags);
382
383 host->irq_enabled = more;
384 host->irq_disabled = false;
385
386 enable = more | host->sdio_irqen;
387
388 if (host->irq_state != enable) {
389 host->irq_state = enable;
390
391 if (enable)
392 enable_irq(host->irq);
393 else
394 disable_irq(host->irq);
395 }
396
397 local_irq_restore(flags);
398 }
399
400 /**
401 *
402 */
s3cmci_disable_irq(struct s3cmci_host * host,bool transfer)403 static void s3cmci_disable_irq(struct s3cmci_host *host, bool transfer)
404 {
405 unsigned long flags;
406
407 local_irq_save(flags);
408
409 /* pr_debug("%s: transfer %d\n", __func__, transfer); */
410
411 host->irq_disabled = transfer;
412
413 if (transfer && host->irq_state) {
414 host->irq_state = false;
415 disable_irq(host->irq);
416 }
417
418 local_irq_restore(flags);
419 }
420
do_pio_read(struct s3cmci_host * host)421 static void do_pio_read(struct s3cmci_host *host)
422 {
423 int res;
424 u32 fifo;
425 u32 *ptr;
426 u32 fifo_words;
427 void __iomem *from_ptr;
428
429 /* write real prescaler to host, it might be set slow to fix */
430 writel(host->prescaler, host->base + S3C2410_SDIPRE);
431
432 from_ptr = host->base + host->sdidata;
433
434 while ((fifo = fifo_count(host))) {
435 if (!host->pio_bytes) {
436 res = get_data_buffer(host, &host->pio_bytes,
437 &host->pio_ptr);
438 if (res) {
439 host->pio_active = XFER_NONE;
440 host->complete_what = COMPLETION_FINALIZE;
441
442 dbg(host, dbg_pio, "pio_read(): "
443 "complete (no more data).\n");
444 return;
445 }
446
447 dbg(host, dbg_pio,
448 "pio_read(): new target: [%i]@[%p]\n",
449 host->pio_bytes, host->pio_ptr);
450 }
451
452 dbg(host, dbg_pio,
453 "pio_read(): fifo:[%02i] buffer:[%03i] dcnt:[%08X]\n",
454 fifo, host->pio_bytes,
455 readl(host->base + S3C2410_SDIDCNT));
456
457 /* If we have reached the end of the block, we can
458 * read a word and get 1 to 3 bytes. If we in the
459 * middle of the block, we have to read full words,
460 * otherwise we will write garbage, so round down to
461 * an even multiple of 4. */
462 if (fifo >= host->pio_bytes)
463 fifo = host->pio_bytes;
464 else
465 fifo -= fifo & 3;
466
467 host->pio_bytes -= fifo;
468 host->pio_count += fifo;
469
470 fifo_words = fifo >> 2;
471 ptr = host->pio_ptr;
472 while (fifo_words--)
473 *ptr++ = readl(from_ptr);
474 host->pio_ptr = ptr;
475
476 if (fifo & 3) {
477 u32 n = fifo & 3;
478 u32 data = readl(from_ptr);
479 u8 *p = (u8 *)host->pio_ptr;
480
481 while (n--) {
482 *p++ = data;
483 data >>= 8;
484 }
485 }
486 }
487
488 if (!host->pio_bytes) {
489 res = get_data_buffer(host, &host->pio_bytes, &host->pio_ptr);
490 if (res) {
491 dbg(host, dbg_pio,
492 "pio_read(): complete (no more buffers).\n");
493 host->pio_active = XFER_NONE;
494 host->complete_what = COMPLETION_FINALIZE;
495
496 return;
497 }
498 }
499
500 enable_imask(host,
501 S3C2410_SDIIMSK_RXFIFOHALF | S3C2410_SDIIMSK_RXFIFOLAST);
502 }
503
do_pio_write(struct s3cmci_host * host)504 static void do_pio_write(struct s3cmci_host *host)
505 {
506 void __iomem *to_ptr;
507 int res;
508 u32 fifo;
509 u32 *ptr;
510
511 to_ptr = host->base + host->sdidata;
512
513 while ((fifo = fifo_free(host)) > 3) {
514 if (!host->pio_bytes) {
515 res = get_data_buffer(host, &host->pio_bytes,
516 &host->pio_ptr);
517 if (res) {
518 dbg(host, dbg_pio,
519 "pio_write(): complete (no more data).\n");
520 host->pio_active = XFER_NONE;
521
522 return;
523 }
524
525 dbg(host, dbg_pio,
526 "pio_write(): new source: [%i]@[%p]\n",
527 host->pio_bytes, host->pio_ptr);
528
529 }
530
531 /* If we have reached the end of the block, we have to
532 * write exactly the remaining number of bytes. If we
533 * in the middle of the block, we have to write full
534 * words, so round down to an even multiple of 4. */
535 if (fifo >= host->pio_bytes)
536 fifo = host->pio_bytes;
537 else
538 fifo -= fifo & 3;
539
540 host->pio_bytes -= fifo;
541 host->pio_count += fifo;
542
543 fifo = (fifo + 3) >> 2;
544 ptr = host->pio_ptr;
545 while (fifo--)
546 writel(*ptr++, to_ptr);
547 host->pio_ptr = ptr;
548 }
549
550 enable_imask(host, S3C2410_SDIIMSK_TXFIFOHALF);
551 }
552
pio_tasklet(unsigned long data)553 static void pio_tasklet(unsigned long data)
554 {
555 struct s3cmci_host *host = (struct s3cmci_host *) data;
556
557 s3cmci_disable_irq(host, true);
558
559 if (host->pio_active == XFER_WRITE)
560 do_pio_write(host);
561
562 if (host->pio_active == XFER_READ)
563 do_pio_read(host);
564
565 if (host->complete_what == COMPLETION_FINALIZE) {
566 clear_imask(host);
567 if (host->pio_active != XFER_NONE) {
568 dbg(host, dbg_err, "unfinished %s "
569 "- pio_count:[%u] pio_bytes:[%u]\n",
570 (host->pio_active == XFER_READ) ? "read" : "write",
571 host->pio_count, host->pio_bytes);
572
573 if (host->mrq->data)
574 host->mrq->data->error = -EINVAL;
575 }
576
577 s3cmci_enable_irq(host, false);
578 finalize_request(host);
579 } else
580 s3cmci_enable_irq(host, true);
581 }
582
583 /*
584 * ISR for SDI Interface IRQ
585 * Communication between driver and ISR works as follows:
586 * host->mrq points to current request
587 * host->complete_what Indicates when the request is considered done
588 * COMPLETION_CMDSENT when the command was sent
589 * COMPLETION_RSPFIN when a response was received
590 * COMPLETION_XFERFINISH when the data transfer is finished
591 * COMPLETION_XFERFINISH_RSPFIN both of the above.
592 * host->complete_request is the completion-object the driver waits for
593 *
594 * 1) Driver sets up host->mrq and host->complete_what
595 * 2) Driver prepares the transfer
596 * 3) Driver enables interrupts
597 * 4) Driver starts transfer
598 * 5) Driver waits for host->complete_rquest
599 * 6) ISR checks for request status (errors and success)
600 * 6) ISR sets host->mrq->cmd->error and host->mrq->data->error
601 * 7) ISR completes host->complete_request
602 * 8) ISR disables interrupts
603 * 9) Driver wakes up and takes care of the request
604 *
605 * Note: "->error"-fields are expected to be set to 0 before the request
606 * was issued by mmc.c - therefore they are only set, when an error
607 * contition comes up
608 */
609
s3cmci_irq(int irq,void * dev_id)610 static irqreturn_t s3cmci_irq(int irq, void *dev_id)
611 {
612 struct s3cmci_host *host = dev_id;
613 struct mmc_command *cmd;
614 u32 mci_csta, mci_dsta, mci_fsta, mci_dcnt, mci_imsk;
615 u32 mci_cclear = 0, mci_dclear;
616 unsigned long iflags;
617
618 mci_dsta = readl(host->base + S3C2410_SDIDSTA);
619 mci_imsk = readl(host->base + host->sdiimsk);
620
621 if (mci_dsta & S3C2410_SDIDSTA_SDIOIRQDETECT) {
622 if (mci_imsk & S3C2410_SDIIMSK_SDIOIRQ) {
623 mci_dclear = S3C2410_SDIDSTA_SDIOIRQDETECT;
624 writel(mci_dclear, host->base + S3C2410_SDIDSTA);
625
626 mmc_signal_sdio_irq(host->mmc);
627 return IRQ_HANDLED;
628 }
629 }
630
631 spin_lock_irqsave(&host->complete_lock, iflags);
632
633 mci_csta = readl(host->base + S3C2410_SDICMDSTAT);
634 mci_dcnt = readl(host->base + S3C2410_SDIDCNT);
635 mci_fsta = readl(host->base + S3C2410_SDIFSTA);
636 mci_dclear = 0;
637
638 if ((host->complete_what == COMPLETION_NONE) ||
639 (host->complete_what == COMPLETION_FINALIZE)) {
640 host->status = "nothing to complete";
641 clear_imask(host);
642 goto irq_out;
643 }
644
645 if (!host->mrq) {
646 host->status = "no active mrq";
647 clear_imask(host);
648 goto irq_out;
649 }
650
651 cmd = host->cmd_is_stop ? host->mrq->stop : host->mrq->cmd;
652
653 if (!cmd) {
654 host->status = "no active cmd";
655 clear_imask(host);
656 goto irq_out;
657 }
658
659 if (!s3cmci_host_usedma(host)) {
660 if ((host->pio_active == XFER_WRITE) &&
661 (mci_fsta & S3C2410_SDIFSTA_TFDET)) {
662
663 disable_imask(host, S3C2410_SDIIMSK_TXFIFOHALF);
664 tasklet_schedule(&host->pio_tasklet);
665 host->status = "pio tx";
666 }
667
668 if ((host->pio_active == XFER_READ) &&
669 (mci_fsta & S3C2410_SDIFSTA_RFDET)) {
670
671 disable_imask(host,
672 S3C2410_SDIIMSK_RXFIFOHALF |
673 S3C2410_SDIIMSK_RXFIFOLAST);
674
675 tasklet_schedule(&host->pio_tasklet);
676 host->status = "pio rx";
677 }
678 }
679
680 if (mci_csta & S3C2410_SDICMDSTAT_CMDTIMEOUT) {
681 dbg(host, dbg_err, "CMDSTAT: error CMDTIMEOUT\n");
682 cmd->error = -ETIMEDOUT;
683 host->status = "error: command timeout";
684 goto fail_transfer;
685 }
686
687 if (mci_csta & S3C2410_SDICMDSTAT_CMDSENT) {
688 if (host->complete_what == COMPLETION_CMDSENT) {
689 host->status = "ok: command sent";
690 goto close_transfer;
691 }
692
693 mci_cclear |= S3C2410_SDICMDSTAT_CMDSENT;
694 }
695
696 if (mci_csta & S3C2410_SDICMDSTAT_CRCFAIL) {
697 if (cmd->flags & MMC_RSP_CRC) {
698 if (host->mrq->cmd->flags & MMC_RSP_136) {
699 dbg(host, dbg_irq,
700 "fixup: ignore CRC fail with long rsp\n");
701 } else {
702 /* note, we used to fail the transfer
703 * here, but it seems that this is just
704 * the hardware getting it wrong.
705 *
706 * cmd->error = -EILSEQ;
707 * host->status = "error: bad command crc";
708 * goto fail_transfer;
709 */
710 }
711 }
712
713 mci_cclear |= S3C2410_SDICMDSTAT_CRCFAIL;
714 }
715
716 if (mci_csta & S3C2410_SDICMDSTAT_RSPFIN) {
717 if (host->complete_what == COMPLETION_RSPFIN) {
718 host->status = "ok: command response received";
719 goto close_transfer;
720 }
721
722 if (host->complete_what == COMPLETION_XFERFINISH_RSPFIN)
723 host->complete_what = COMPLETION_XFERFINISH;
724
725 mci_cclear |= S3C2410_SDICMDSTAT_RSPFIN;
726 }
727
728 /* errors handled after this point are only relevant
729 when a data transfer is in progress */
730
731 if (!cmd->data)
732 goto clear_status_bits;
733
734 /* Check for FIFO failure */
735 if (host->is2440) {
736 if (mci_fsta & S3C2440_SDIFSTA_FIFOFAIL) {
737 dbg(host, dbg_err, "FIFO failure\n");
738 host->mrq->data->error = -EILSEQ;
739 host->status = "error: 2440 fifo failure";
740 goto fail_transfer;
741 }
742 } else {
743 if (mci_dsta & S3C2410_SDIDSTA_FIFOFAIL) {
744 dbg(host, dbg_err, "FIFO failure\n");
745 cmd->data->error = -EILSEQ;
746 host->status = "error: fifo failure";
747 goto fail_transfer;
748 }
749 }
750
751 if (mci_dsta & S3C2410_SDIDSTA_RXCRCFAIL) {
752 dbg(host, dbg_err, "bad data crc (outgoing)\n");
753 cmd->data->error = -EILSEQ;
754 host->status = "error: bad data crc (outgoing)";
755 goto fail_transfer;
756 }
757
758 if (mci_dsta & S3C2410_SDIDSTA_CRCFAIL) {
759 dbg(host, dbg_err, "bad data crc (incoming)\n");
760 cmd->data->error = -EILSEQ;
761 host->status = "error: bad data crc (incoming)";
762 goto fail_transfer;
763 }
764
765 if (mci_dsta & S3C2410_SDIDSTA_DATATIMEOUT) {
766 dbg(host, dbg_err, "data timeout\n");
767 cmd->data->error = -ETIMEDOUT;
768 host->status = "error: data timeout";
769 goto fail_transfer;
770 }
771
772 if (mci_dsta & S3C2410_SDIDSTA_XFERFINISH) {
773 if (host->complete_what == COMPLETION_XFERFINISH) {
774 host->status = "ok: data transfer completed";
775 goto close_transfer;
776 }
777
778 if (host->complete_what == COMPLETION_XFERFINISH_RSPFIN)
779 host->complete_what = COMPLETION_RSPFIN;
780
781 mci_dclear |= S3C2410_SDIDSTA_XFERFINISH;
782 }
783
784 clear_status_bits:
785 writel(mci_cclear, host->base + S3C2410_SDICMDSTAT);
786 writel(mci_dclear, host->base + S3C2410_SDIDSTA);
787
788 goto irq_out;
789
790 fail_transfer:
791 host->pio_active = XFER_NONE;
792
793 close_transfer:
794 host->complete_what = COMPLETION_FINALIZE;
795
796 clear_imask(host);
797 tasklet_schedule(&host->pio_tasklet);
798
799 goto irq_out;
800
801 irq_out:
802 dbg(host, dbg_irq,
803 "csta:0x%08x dsta:0x%08x fsta:0x%08x dcnt:0x%08x status:%s.\n",
804 mci_csta, mci_dsta, mci_fsta, mci_dcnt, host->status);
805
806 spin_unlock_irqrestore(&host->complete_lock, iflags);
807 return IRQ_HANDLED;
808
809 }
810
811 /*
812 * ISR for the CardDetect Pin
813 */
814
s3cmci_irq_cd(int irq,void * dev_id)815 static irqreturn_t s3cmci_irq_cd(int irq, void *dev_id)
816 {
817 struct s3cmci_host *host = (struct s3cmci_host *)dev_id;
818
819 dbg(host, dbg_irq, "card detect\n");
820
821 mmc_detect_change(host->mmc, msecs_to_jiffies(500));
822
823 return IRQ_HANDLED;
824 }
825
s3cmci_dma_done_callback(void * arg)826 static void s3cmci_dma_done_callback(void *arg)
827 {
828 struct s3cmci_host *host = arg;
829 unsigned long iflags;
830
831 BUG_ON(!host->mrq);
832 BUG_ON(!host->mrq->data);
833
834 spin_lock_irqsave(&host->complete_lock, iflags);
835
836 dbg(host, dbg_dma, "DMA FINISHED\n");
837
838 host->dma_complete = 1;
839 host->complete_what = COMPLETION_FINALIZE;
840
841 tasklet_schedule(&host->pio_tasklet);
842 spin_unlock_irqrestore(&host->complete_lock, iflags);
843
844 }
845
finalize_request(struct s3cmci_host * host)846 static void finalize_request(struct s3cmci_host *host)
847 {
848 struct mmc_request *mrq = host->mrq;
849 struct mmc_command *cmd;
850 int debug_as_failure = 0;
851
852 if (host->complete_what != COMPLETION_FINALIZE)
853 return;
854
855 if (!mrq)
856 return;
857 cmd = host->cmd_is_stop ? mrq->stop : mrq->cmd;
858
859 if (cmd->data && (cmd->error == 0) &&
860 (cmd->data->error == 0)) {
861 if (s3cmci_host_usedma(host) && (!host->dma_complete)) {
862 dbg(host, dbg_dma, "DMA Missing (%d)!\n",
863 host->dma_complete);
864 return;
865 }
866 }
867
868 /* Read response from controller. */
869 cmd->resp[0] = readl(host->base + S3C2410_SDIRSP0);
870 cmd->resp[1] = readl(host->base + S3C2410_SDIRSP1);
871 cmd->resp[2] = readl(host->base + S3C2410_SDIRSP2);
872 cmd->resp[3] = readl(host->base + S3C2410_SDIRSP3);
873
874 writel(host->prescaler, host->base + S3C2410_SDIPRE);
875
876 if (cmd->error)
877 debug_as_failure = 1;
878
879 if (cmd->data && cmd->data->error)
880 debug_as_failure = 1;
881
882 dbg_dumpcmd(host, cmd, debug_as_failure);
883
884 /* Cleanup controller */
885 writel(0, host->base + S3C2410_SDICMDARG);
886 writel(S3C2410_SDIDCON_STOP, host->base + S3C2410_SDIDCON);
887 writel(0, host->base + S3C2410_SDICMDCON);
888 clear_imask(host);
889
890 if (cmd->data && cmd->error)
891 cmd->data->error = cmd->error;
892
893 if (cmd->data && cmd->data->stop && (!host->cmd_is_stop)) {
894 host->cmd_is_stop = 1;
895 s3cmci_send_request(host->mmc);
896 return;
897 }
898
899 /* If we have no data transfer we are finished here */
900 if (!mrq->data)
901 goto request_done;
902
903 /* Calculate the amout of bytes transfer if there was no error */
904 if (mrq->data->error == 0) {
905 mrq->data->bytes_xfered =
906 (mrq->data->blocks * mrq->data->blksz);
907 } else {
908 mrq->data->bytes_xfered = 0;
909 }
910
911 /* If we had an error while transferring data we flush the
912 * DMA channel and the fifo to clear out any garbage. */
913 if (mrq->data->error != 0) {
914 if (s3cmci_host_usedma(host))
915 dmaengine_terminate_all(host->dma);
916
917 if (host->is2440) {
918 /* Clear failure register and reset fifo. */
919 writel(S3C2440_SDIFSTA_FIFORESET |
920 S3C2440_SDIFSTA_FIFOFAIL,
921 host->base + S3C2410_SDIFSTA);
922 } else {
923 u32 mci_con;
924
925 /* reset fifo */
926 mci_con = readl(host->base + S3C2410_SDICON);
927 mci_con |= S3C2410_SDICON_FIFORESET;
928
929 writel(mci_con, host->base + S3C2410_SDICON);
930 }
931 }
932
933 request_done:
934 host->complete_what = COMPLETION_NONE;
935 host->mrq = NULL;
936
937 s3cmci_check_sdio_irq(host);
938 mmc_request_done(host->mmc, mrq);
939 }
940
s3cmci_send_command(struct s3cmci_host * host,struct mmc_command * cmd)941 static void s3cmci_send_command(struct s3cmci_host *host,
942 struct mmc_command *cmd)
943 {
944 u32 ccon, imsk;
945
946 imsk = S3C2410_SDIIMSK_CRCSTATUS | S3C2410_SDIIMSK_CMDTIMEOUT |
947 S3C2410_SDIIMSK_RESPONSEND | S3C2410_SDIIMSK_CMDSENT |
948 S3C2410_SDIIMSK_RESPONSECRC;
949
950 enable_imask(host, imsk);
951
952 if (cmd->data)
953 host->complete_what = COMPLETION_XFERFINISH_RSPFIN;
954 else if (cmd->flags & MMC_RSP_PRESENT)
955 host->complete_what = COMPLETION_RSPFIN;
956 else
957 host->complete_what = COMPLETION_CMDSENT;
958
959 writel(cmd->arg, host->base + S3C2410_SDICMDARG);
960
961 ccon = cmd->opcode & S3C2410_SDICMDCON_INDEX;
962 ccon |= S3C2410_SDICMDCON_SENDERHOST | S3C2410_SDICMDCON_CMDSTART;
963
964 if (cmd->flags & MMC_RSP_PRESENT)
965 ccon |= S3C2410_SDICMDCON_WAITRSP;
966
967 if (cmd->flags & MMC_RSP_136)
968 ccon |= S3C2410_SDICMDCON_LONGRSP;
969
970 writel(ccon, host->base + S3C2410_SDICMDCON);
971 }
972
s3cmci_setup_data(struct s3cmci_host * host,struct mmc_data * data)973 static int s3cmci_setup_data(struct s3cmci_host *host, struct mmc_data *data)
974 {
975 u32 dcon, imsk, stoptries = 3;
976
977 /* write DCON register */
978
979 if (!data) {
980 writel(0, host->base + S3C2410_SDIDCON);
981 return 0;
982 }
983
984 if ((data->blksz & 3) != 0) {
985 /* We cannot deal with unaligned blocks with more than
986 * one block being transferred. */
987
988 if (data->blocks > 1) {
989 pr_warn("%s: can't do non-word sized block transfers (blksz %d)\n",
990 __func__, data->blksz);
991 return -EINVAL;
992 }
993 }
994
995 while (readl(host->base + S3C2410_SDIDSTA) &
996 (S3C2410_SDIDSTA_TXDATAON | S3C2410_SDIDSTA_RXDATAON)) {
997
998 dbg(host, dbg_err,
999 "mci_setup_data() transfer stillin progress.\n");
1000
1001 writel(S3C2410_SDIDCON_STOP, host->base + S3C2410_SDIDCON);
1002 s3cmci_reset(host);
1003
1004 if ((stoptries--) == 0) {
1005 dbg_dumpregs(host, "DRF");
1006 return -EINVAL;
1007 }
1008 }
1009
1010 dcon = data->blocks & S3C2410_SDIDCON_BLKNUM_MASK;
1011
1012 if (s3cmci_host_usedma(host))
1013 dcon |= S3C2410_SDIDCON_DMAEN;
1014
1015 if (host->bus_width == MMC_BUS_WIDTH_4)
1016 dcon |= S3C2410_SDIDCON_WIDEBUS;
1017
1018 if (!(data->flags & MMC_DATA_STREAM))
1019 dcon |= S3C2410_SDIDCON_BLOCKMODE;
1020
1021 if (data->flags & MMC_DATA_WRITE) {
1022 dcon |= S3C2410_SDIDCON_TXAFTERRESP;
1023 dcon |= S3C2410_SDIDCON_XFER_TXSTART;
1024 }
1025
1026 if (data->flags & MMC_DATA_READ) {
1027 dcon |= S3C2410_SDIDCON_RXAFTERCMD;
1028 dcon |= S3C2410_SDIDCON_XFER_RXSTART;
1029 }
1030
1031 if (host->is2440) {
1032 dcon |= S3C2440_SDIDCON_DS_WORD;
1033 dcon |= S3C2440_SDIDCON_DATSTART;
1034 }
1035
1036 writel(dcon, host->base + S3C2410_SDIDCON);
1037
1038 /* write BSIZE register */
1039
1040 writel(data->blksz, host->base + S3C2410_SDIBSIZE);
1041
1042 /* add to IMASK register */
1043 imsk = S3C2410_SDIIMSK_FIFOFAIL | S3C2410_SDIIMSK_DATACRC |
1044 S3C2410_SDIIMSK_DATATIMEOUT | S3C2410_SDIIMSK_DATAFINISH;
1045
1046 enable_imask(host, imsk);
1047
1048 /* write TIMER register */
1049
1050 if (host->is2440) {
1051 writel(0x007FFFFF, host->base + S3C2410_SDITIMER);
1052 } else {
1053 writel(0x0000FFFF, host->base + S3C2410_SDITIMER);
1054
1055 /* FIX: set slow clock to prevent timeouts on read */
1056 if (data->flags & MMC_DATA_READ)
1057 writel(0xFF, host->base + S3C2410_SDIPRE);
1058 }
1059
1060 return 0;
1061 }
1062
1063 #define BOTH_DIR (MMC_DATA_WRITE | MMC_DATA_READ)
1064
s3cmci_prepare_pio(struct s3cmci_host * host,struct mmc_data * data)1065 static int s3cmci_prepare_pio(struct s3cmci_host *host, struct mmc_data *data)
1066 {
1067 int rw = (data->flags & MMC_DATA_WRITE) ? 1 : 0;
1068
1069 BUG_ON((data->flags & BOTH_DIR) == BOTH_DIR);
1070
1071 host->pio_sgptr = 0;
1072 host->pio_bytes = 0;
1073 host->pio_count = 0;
1074 host->pio_active = rw ? XFER_WRITE : XFER_READ;
1075
1076 if (rw) {
1077 do_pio_write(host);
1078 enable_imask(host, S3C2410_SDIIMSK_TXFIFOHALF);
1079 } else {
1080 enable_imask(host, S3C2410_SDIIMSK_RXFIFOHALF
1081 | S3C2410_SDIIMSK_RXFIFOLAST);
1082 }
1083
1084 return 0;
1085 }
1086
s3cmci_prepare_dma(struct s3cmci_host * host,struct mmc_data * data)1087 static int s3cmci_prepare_dma(struct s3cmci_host *host, struct mmc_data *data)
1088 {
1089 int rw = data->flags & MMC_DATA_WRITE;
1090 struct dma_async_tx_descriptor *desc;
1091 struct dma_slave_config conf = {
1092 .src_addr = host->mem->start + host->sdidata,
1093 .dst_addr = host->mem->start + host->sdidata,
1094 .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
1095 .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
1096 };
1097
1098 BUG_ON((data->flags & BOTH_DIR) == BOTH_DIR);
1099
1100 /* Restore prescaler value */
1101 writel(host->prescaler, host->base + S3C2410_SDIPRE);
1102
1103 if (!rw)
1104 conf.direction = DMA_DEV_TO_MEM;
1105 else
1106 conf.direction = DMA_MEM_TO_DEV;
1107
1108 dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
1109 rw ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
1110
1111 dmaengine_slave_config(host->dma, &conf);
1112 desc = dmaengine_prep_slave_sg(host->dma, data->sg, data->sg_len,
1113 conf.direction,
1114 DMA_CTRL_ACK | DMA_PREP_INTERRUPT);
1115 if (!desc)
1116 goto unmap_exit;
1117 desc->callback = s3cmci_dma_done_callback;
1118 desc->callback_param = host;
1119 dmaengine_submit(desc);
1120 dma_async_issue_pending(host->dma);
1121
1122 return 0;
1123
1124 unmap_exit:
1125 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
1126 rw ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
1127 return -ENOMEM;
1128 }
1129
s3cmci_send_request(struct mmc_host * mmc)1130 static void s3cmci_send_request(struct mmc_host *mmc)
1131 {
1132 struct s3cmci_host *host = mmc_priv(mmc);
1133 struct mmc_request *mrq = host->mrq;
1134 struct mmc_command *cmd = host->cmd_is_stop ? mrq->stop : mrq->cmd;
1135
1136 host->ccnt++;
1137 prepare_dbgmsg(host, cmd, host->cmd_is_stop);
1138
1139 /* Clear command, data and fifo status registers
1140 Fifo clear only necessary on 2440, but doesn't hurt on 2410
1141 */
1142 writel(0xFFFFFFFF, host->base + S3C2410_SDICMDSTAT);
1143 writel(0xFFFFFFFF, host->base + S3C2410_SDIDSTA);
1144 writel(0xFFFFFFFF, host->base + S3C2410_SDIFSTA);
1145
1146 if (cmd->data) {
1147 int res = s3cmci_setup_data(host, cmd->data);
1148
1149 host->dcnt++;
1150
1151 if (res) {
1152 dbg(host, dbg_err, "setup data error %d\n", res);
1153 cmd->error = res;
1154 cmd->data->error = res;
1155
1156 mmc_request_done(mmc, mrq);
1157 return;
1158 }
1159
1160 if (s3cmci_host_usedma(host))
1161 res = s3cmci_prepare_dma(host, cmd->data);
1162 else
1163 res = s3cmci_prepare_pio(host, cmd->data);
1164
1165 if (res) {
1166 dbg(host, dbg_err, "data prepare error %d\n", res);
1167 cmd->error = res;
1168 cmd->data->error = res;
1169
1170 mmc_request_done(mmc, mrq);
1171 return;
1172 }
1173 }
1174
1175 /* Send command */
1176 s3cmci_send_command(host, cmd);
1177
1178 /* Enable Interrupt */
1179 s3cmci_enable_irq(host, true);
1180 }
1181
s3cmci_card_present(struct mmc_host * mmc)1182 static int s3cmci_card_present(struct mmc_host *mmc)
1183 {
1184 struct s3cmci_host *host = mmc_priv(mmc);
1185 struct s3c24xx_mci_pdata *pdata = host->pdata;
1186 int ret;
1187
1188 if (pdata->no_detect)
1189 return -ENOSYS;
1190
1191 ret = gpio_get_value(pdata->gpio_detect) ? 0 : 1;
1192 return ret ^ pdata->detect_invert;
1193 }
1194
s3cmci_request(struct mmc_host * mmc,struct mmc_request * mrq)1195 static void s3cmci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1196 {
1197 struct s3cmci_host *host = mmc_priv(mmc);
1198
1199 host->status = "mmc request";
1200 host->cmd_is_stop = 0;
1201 host->mrq = mrq;
1202
1203 if (s3cmci_card_present(mmc) == 0) {
1204 dbg(host, dbg_err, "%s: no medium present\n", __func__);
1205 host->mrq->cmd->error = -ENOMEDIUM;
1206 mmc_request_done(mmc, mrq);
1207 } else
1208 s3cmci_send_request(mmc);
1209 }
1210
s3cmci_set_clk(struct s3cmci_host * host,struct mmc_ios * ios)1211 static void s3cmci_set_clk(struct s3cmci_host *host, struct mmc_ios *ios)
1212 {
1213 u32 mci_psc;
1214
1215 /* Set clock */
1216 for (mci_psc = 0; mci_psc < 255; mci_psc++) {
1217 host->real_rate = host->clk_rate / (host->clk_div*(mci_psc+1));
1218
1219 if (host->real_rate <= ios->clock)
1220 break;
1221 }
1222
1223 if (mci_psc > 255)
1224 mci_psc = 255;
1225
1226 host->prescaler = mci_psc;
1227 writel(host->prescaler, host->base + S3C2410_SDIPRE);
1228
1229 /* If requested clock is 0, real_rate will be 0, too */
1230 if (ios->clock == 0)
1231 host->real_rate = 0;
1232 }
1233
s3cmci_set_ios(struct mmc_host * mmc,struct mmc_ios * ios)1234 static void s3cmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1235 {
1236 struct s3cmci_host *host = mmc_priv(mmc);
1237 u32 mci_con;
1238
1239 /* Set the power state */
1240
1241 mci_con = readl(host->base + S3C2410_SDICON);
1242
1243 switch (ios->power_mode) {
1244 case MMC_POWER_ON:
1245 case MMC_POWER_UP:
1246 /* Configure GPE5...GPE10 pins in SD mode */
1247 s3c_gpio_cfgall_range(S3C2410_GPE(5), 6, S3C_GPIO_SFN(2),
1248 S3C_GPIO_PULL_NONE);
1249
1250 if (host->pdata->set_power)
1251 host->pdata->set_power(ios->power_mode, ios->vdd);
1252
1253 if (!host->is2440)
1254 mci_con |= S3C2410_SDICON_FIFORESET;
1255
1256 break;
1257
1258 case MMC_POWER_OFF:
1259 default:
1260 gpio_direction_output(S3C2410_GPE(5), 0);
1261
1262 if (host->is2440)
1263 mci_con |= S3C2440_SDICON_SDRESET;
1264
1265 if (host->pdata->set_power)
1266 host->pdata->set_power(ios->power_mode, ios->vdd);
1267
1268 break;
1269 }
1270
1271 s3cmci_set_clk(host, ios);
1272
1273 /* Set CLOCK_ENABLE */
1274 if (ios->clock)
1275 mci_con |= S3C2410_SDICON_CLOCKTYPE;
1276 else
1277 mci_con &= ~S3C2410_SDICON_CLOCKTYPE;
1278
1279 writel(mci_con, host->base + S3C2410_SDICON);
1280
1281 if ((ios->power_mode == MMC_POWER_ON) ||
1282 (ios->power_mode == MMC_POWER_UP)) {
1283 dbg(host, dbg_conf, "running at %lukHz (requested: %ukHz).\n",
1284 host->real_rate/1000, ios->clock/1000);
1285 } else {
1286 dbg(host, dbg_conf, "powered down.\n");
1287 }
1288
1289 host->bus_width = ios->bus_width;
1290 }
1291
s3cmci_reset(struct s3cmci_host * host)1292 static void s3cmci_reset(struct s3cmci_host *host)
1293 {
1294 u32 con = readl(host->base + S3C2410_SDICON);
1295
1296 con |= S3C2440_SDICON_SDRESET;
1297 writel(con, host->base + S3C2410_SDICON);
1298 }
1299
s3cmci_get_ro(struct mmc_host * mmc)1300 static int s3cmci_get_ro(struct mmc_host *mmc)
1301 {
1302 struct s3cmci_host *host = mmc_priv(mmc);
1303 struct s3c24xx_mci_pdata *pdata = host->pdata;
1304 int ret;
1305
1306 if (pdata->no_wprotect)
1307 return 0;
1308
1309 ret = gpio_get_value(pdata->gpio_wprotect) ? 1 : 0;
1310 ret ^= pdata->wprotect_invert;
1311
1312 return ret;
1313 }
1314
s3cmci_enable_sdio_irq(struct mmc_host * mmc,int enable)1315 static void s3cmci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1316 {
1317 struct s3cmci_host *host = mmc_priv(mmc);
1318 unsigned long flags;
1319 u32 con;
1320
1321 local_irq_save(flags);
1322
1323 con = readl(host->base + S3C2410_SDICON);
1324 host->sdio_irqen = enable;
1325
1326 if (enable == host->sdio_irqen)
1327 goto same_state;
1328
1329 if (enable) {
1330 con |= S3C2410_SDICON_SDIOIRQ;
1331 enable_imask(host, S3C2410_SDIIMSK_SDIOIRQ);
1332
1333 if (!host->irq_state && !host->irq_disabled) {
1334 host->irq_state = true;
1335 enable_irq(host->irq);
1336 }
1337 } else {
1338 disable_imask(host, S3C2410_SDIIMSK_SDIOIRQ);
1339 con &= ~S3C2410_SDICON_SDIOIRQ;
1340
1341 if (!host->irq_enabled && host->irq_state) {
1342 disable_irq_nosync(host->irq);
1343 host->irq_state = false;
1344 }
1345 }
1346
1347 writel(con, host->base + S3C2410_SDICON);
1348
1349 same_state:
1350 local_irq_restore(flags);
1351
1352 s3cmci_check_sdio_irq(host);
1353 }
1354
1355 static struct mmc_host_ops s3cmci_ops = {
1356 .request = s3cmci_request,
1357 .set_ios = s3cmci_set_ios,
1358 .get_ro = s3cmci_get_ro,
1359 .get_cd = s3cmci_card_present,
1360 .enable_sdio_irq = s3cmci_enable_sdio_irq,
1361 };
1362
1363 static struct s3c24xx_mci_pdata s3cmci_def_pdata = {
1364 /* This is currently here to avoid a number of if (host->pdata)
1365 * checks. Any zero fields to ensure reasonable defaults are picked. */
1366 .no_wprotect = 1,
1367 .no_detect = 1,
1368 };
1369
1370 #ifdef CONFIG_CPU_FREQ
1371
s3cmci_cpufreq_transition(struct notifier_block * nb,unsigned long val,void * data)1372 static int s3cmci_cpufreq_transition(struct notifier_block *nb,
1373 unsigned long val, void *data)
1374 {
1375 struct s3cmci_host *host;
1376 struct mmc_host *mmc;
1377 unsigned long newclk;
1378 unsigned long flags;
1379
1380 host = container_of(nb, struct s3cmci_host, freq_transition);
1381 newclk = clk_get_rate(host->clk);
1382 mmc = host->mmc;
1383
1384 if ((val == CPUFREQ_PRECHANGE && newclk > host->clk_rate) ||
1385 (val == CPUFREQ_POSTCHANGE && newclk < host->clk_rate)) {
1386 spin_lock_irqsave(&mmc->lock, flags);
1387
1388 host->clk_rate = newclk;
1389
1390 if (mmc->ios.power_mode != MMC_POWER_OFF &&
1391 mmc->ios.clock != 0)
1392 s3cmci_set_clk(host, &mmc->ios);
1393
1394 spin_unlock_irqrestore(&mmc->lock, flags);
1395 }
1396
1397 return 0;
1398 }
1399
s3cmci_cpufreq_register(struct s3cmci_host * host)1400 static inline int s3cmci_cpufreq_register(struct s3cmci_host *host)
1401 {
1402 host->freq_transition.notifier_call = s3cmci_cpufreq_transition;
1403
1404 return cpufreq_register_notifier(&host->freq_transition,
1405 CPUFREQ_TRANSITION_NOTIFIER);
1406 }
1407
s3cmci_cpufreq_deregister(struct s3cmci_host * host)1408 static inline void s3cmci_cpufreq_deregister(struct s3cmci_host *host)
1409 {
1410 cpufreq_unregister_notifier(&host->freq_transition,
1411 CPUFREQ_TRANSITION_NOTIFIER);
1412 }
1413
1414 #else
s3cmci_cpufreq_register(struct s3cmci_host * host)1415 static inline int s3cmci_cpufreq_register(struct s3cmci_host *host)
1416 {
1417 return 0;
1418 }
1419
s3cmci_cpufreq_deregister(struct s3cmci_host * host)1420 static inline void s3cmci_cpufreq_deregister(struct s3cmci_host *host)
1421 {
1422 }
1423 #endif
1424
1425
1426 #ifdef CONFIG_DEBUG_FS
1427
s3cmci_state_show(struct seq_file * seq,void * v)1428 static int s3cmci_state_show(struct seq_file *seq, void *v)
1429 {
1430 struct s3cmci_host *host = seq->private;
1431
1432 seq_printf(seq, "Register base = 0x%08x\n", (u32)host->base);
1433 seq_printf(seq, "Clock rate = %ld\n", host->clk_rate);
1434 seq_printf(seq, "Prescale = %d\n", host->prescaler);
1435 seq_printf(seq, "is2440 = %d\n", host->is2440);
1436 seq_printf(seq, "IRQ = %d\n", host->irq);
1437 seq_printf(seq, "IRQ enabled = %d\n", host->irq_enabled);
1438 seq_printf(seq, "IRQ disabled = %d\n", host->irq_disabled);
1439 seq_printf(seq, "IRQ state = %d\n", host->irq_state);
1440 seq_printf(seq, "CD IRQ = %d\n", host->irq_cd);
1441 seq_printf(seq, "Do DMA = %d\n", s3cmci_host_usedma(host));
1442 seq_printf(seq, "SDIIMSK at %d\n", host->sdiimsk);
1443 seq_printf(seq, "SDIDATA at %d\n", host->sdidata);
1444
1445 return 0;
1446 }
1447
s3cmci_state_open(struct inode * inode,struct file * file)1448 static int s3cmci_state_open(struct inode *inode, struct file *file)
1449 {
1450 return single_open(file, s3cmci_state_show, inode->i_private);
1451 }
1452
1453 static const struct file_operations s3cmci_fops_state = {
1454 .owner = THIS_MODULE,
1455 .open = s3cmci_state_open,
1456 .read = seq_read,
1457 .llseek = seq_lseek,
1458 .release = single_release,
1459 };
1460
1461 #define DBG_REG(_r) { .addr = S3C2410_SDI##_r, .name = #_r }
1462
1463 struct s3cmci_reg {
1464 unsigned short addr;
1465 unsigned char *name;
1466 } debug_regs[] = {
1467 DBG_REG(CON),
1468 DBG_REG(PRE),
1469 DBG_REG(CMDARG),
1470 DBG_REG(CMDCON),
1471 DBG_REG(CMDSTAT),
1472 DBG_REG(RSP0),
1473 DBG_REG(RSP1),
1474 DBG_REG(RSP2),
1475 DBG_REG(RSP3),
1476 DBG_REG(TIMER),
1477 DBG_REG(BSIZE),
1478 DBG_REG(DCON),
1479 DBG_REG(DCNT),
1480 DBG_REG(DSTA),
1481 DBG_REG(FSTA),
1482 {}
1483 };
1484
s3cmci_regs_show(struct seq_file * seq,void * v)1485 static int s3cmci_regs_show(struct seq_file *seq, void *v)
1486 {
1487 struct s3cmci_host *host = seq->private;
1488 struct s3cmci_reg *rptr = debug_regs;
1489
1490 for (; rptr->name; rptr++)
1491 seq_printf(seq, "SDI%s\t=0x%08x\n", rptr->name,
1492 readl(host->base + rptr->addr));
1493
1494 seq_printf(seq, "SDIIMSK\t=0x%08x\n", readl(host->base + host->sdiimsk));
1495
1496 return 0;
1497 }
1498
s3cmci_regs_open(struct inode * inode,struct file * file)1499 static int s3cmci_regs_open(struct inode *inode, struct file *file)
1500 {
1501 return single_open(file, s3cmci_regs_show, inode->i_private);
1502 }
1503
1504 static const struct file_operations s3cmci_fops_regs = {
1505 .owner = THIS_MODULE,
1506 .open = s3cmci_regs_open,
1507 .read = seq_read,
1508 .llseek = seq_lseek,
1509 .release = single_release,
1510 };
1511
s3cmci_debugfs_attach(struct s3cmci_host * host)1512 static void s3cmci_debugfs_attach(struct s3cmci_host *host)
1513 {
1514 struct device *dev = &host->pdev->dev;
1515
1516 host->debug_root = debugfs_create_dir(dev_name(dev), NULL);
1517 if (IS_ERR(host->debug_root)) {
1518 dev_err(dev, "failed to create debugfs root\n");
1519 return;
1520 }
1521
1522 host->debug_state = debugfs_create_file("state", 0444,
1523 host->debug_root, host,
1524 &s3cmci_fops_state);
1525
1526 if (IS_ERR(host->debug_state))
1527 dev_err(dev, "failed to create debug state file\n");
1528
1529 host->debug_regs = debugfs_create_file("regs", 0444,
1530 host->debug_root, host,
1531 &s3cmci_fops_regs);
1532
1533 if (IS_ERR(host->debug_regs))
1534 dev_err(dev, "failed to create debug regs file\n");
1535 }
1536
s3cmci_debugfs_remove(struct s3cmci_host * host)1537 static void s3cmci_debugfs_remove(struct s3cmci_host *host)
1538 {
1539 debugfs_remove(host->debug_regs);
1540 debugfs_remove(host->debug_state);
1541 debugfs_remove(host->debug_root);
1542 }
1543
1544 #else
s3cmci_debugfs_attach(struct s3cmci_host * host)1545 static inline void s3cmci_debugfs_attach(struct s3cmci_host *host) { }
s3cmci_debugfs_remove(struct s3cmci_host * host)1546 static inline void s3cmci_debugfs_remove(struct s3cmci_host *host) { }
1547
1548 #endif /* CONFIG_DEBUG_FS */
1549
s3cmci_probe(struct platform_device * pdev)1550 static int s3cmci_probe(struct platform_device *pdev)
1551 {
1552 struct s3cmci_host *host;
1553 struct mmc_host *mmc;
1554 int ret;
1555 int is2440;
1556 int i;
1557
1558 is2440 = platform_get_device_id(pdev)->driver_data;
1559
1560 mmc = mmc_alloc_host(sizeof(struct s3cmci_host), &pdev->dev);
1561 if (!mmc) {
1562 ret = -ENOMEM;
1563 goto probe_out;
1564 }
1565
1566 for (i = S3C2410_GPE(5); i <= S3C2410_GPE(10); i++) {
1567 ret = gpio_request(i, dev_name(&pdev->dev));
1568 if (ret) {
1569 dev_err(&pdev->dev, "failed to get gpio %d\n", i);
1570
1571 for (i--; i >= S3C2410_GPE(5); i--)
1572 gpio_free(i);
1573
1574 goto probe_free_host;
1575 }
1576 }
1577
1578 host = mmc_priv(mmc);
1579 host->mmc = mmc;
1580 host->pdev = pdev;
1581 host->is2440 = is2440;
1582
1583 host->pdata = pdev->dev.platform_data;
1584 if (!host->pdata) {
1585 pdev->dev.platform_data = &s3cmci_def_pdata;
1586 host->pdata = &s3cmci_def_pdata;
1587 }
1588
1589 spin_lock_init(&host->complete_lock);
1590 tasklet_init(&host->pio_tasklet, pio_tasklet, (unsigned long) host);
1591
1592 if (is2440) {
1593 host->sdiimsk = S3C2440_SDIIMSK;
1594 host->sdidata = S3C2440_SDIDATA;
1595 host->clk_div = 1;
1596 } else {
1597 host->sdiimsk = S3C2410_SDIIMSK;
1598 host->sdidata = S3C2410_SDIDATA;
1599 host->clk_div = 2;
1600 }
1601
1602 host->complete_what = COMPLETION_NONE;
1603 host->pio_active = XFER_NONE;
1604
1605 host->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1606 if (!host->mem) {
1607 dev_err(&pdev->dev,
1608 "failed to get io memory region resource.\n");
1609
1610 ret = -ENOENT;
1611 goto probe_free_gpio;
1612 }
1613
1614 host->mem = request_mem_region(host->mem->start,
1615 resource_size(host->mem), pdev->name);
1616
1617 if (!host->mem) {
1618 dev_err(&pdev->dev, "failed to request io memory region.\n");
1619 ret = -ENOENT;
1620 goto probe_free_gpio;
1621 }
1622
1623 host->base = ioremap(host->mem->start, resource_size(host->mem));
1624 if (!host->base) {
1625 dev_err(&pdev->dev, "failed to ioremap() io memory region.\n");
1626 ret = -EINVAL;
1627 goto probe_free_mem_region;
1628 }
1629
1630 host->irq = platform_get_irq(pdev, 0);
1631 if (host->irq == 0) {
1632 dev_err(&pdev->dev, "failed to get interrupt resource.\n");
1633 ret = -EINVAL;
1634 goto probe_iounmap;
1635 }
1636
1637 if (request_irq(host->irq, s3cmci_irq, 0, DRIVER_NAME, host)) {
1638 dev_err(&pdev->dev, "failed to request mci interrupt.\n");
1639 ret = -ENOENT;
1640 goto probe_iounmap;
1641 }
1642
1643 /* We get spurious interrupts even when we have set the IMSK
1644 * register to ignore everything, so use disable_irq() to make
1645 * ensure we don't lock the system with un-serviceable requests. */
1646
1647 disable_irq(host->irq);
1648 host->irq_state = false;
1649
1650 if (!host->pdata->no_detect) {
1651 ret = gpio_request(host->pdata->gpio_detect, "s3cmci detect");
1652 if (ret) {
1653 dev_err(&pdev->dev, "failed to get detect gpio\n");
1654 goto probe_free_irq;
1655 }
1656
1657 host->irq_cd = gpio_to_irq(host->pdata->gpio_detect);
1658
1659 if (host->irq_cd >= 0) {
1660 if (request_irq(host->irq_cd, s3cmci_irq_cd,
1661 IRQF_TRIGGER_RISING |
1662 IRQF_TRIGGER_FALLING,
1663 DRIVER_NAME, host)) {
1664 dev_err(&pdev->dev,
1665 "can't get card detect irq.\n");
1666 ret = -ENOENT;
1667 goto probe_free_gpio_cd;
1668 }
1669 } else {
1670 dev_warn(&pdev->dev,
1671 "host detect has no irq available\n");
1672 gpio_direction_input(host->pdata->gpio_detect);
1673 }
1674 } else
1675 host->irq_cd = -1;
1676
1677 if (!host->pdata->no_wprotect) {
1678 ret = gpio_request(host->pdata->gpio_wprotect, "s3cmci wp");
1679 if (ret) {
1680 dev_err(&pdev->dev, "failed to get writeprotect\n");
1681 goto probe_free_irq_cd;
1682 }
1683
1684 gpio_direction_input(host->pdata->gpio_wprotect);
1685 }
1686
1687 /* depending on the dma state, get a dma channel to use. */
1688
1689 if (s3cmci_host_usedma(host)) {
1690 dma_cap_mask_t mask;
1691
1692 dma_cap_zero(mask);
1693 dma_cap_set(DMA_SLAVE, mask);
1694
1695 host->dma = dma_request_slave_channel_compat(mask,
1696 s3c24xx_dma_filter, (void *)DMACH_SDI, &pdev->dev, "rx-tx");
1697 if (!host->dma) {
1698 dev_err(&pdev->dev, "cannot get DMA channel.\n");
1699 ret = -EBUSY;
1700 goto probe_free_gpio_wp;
1701 }
1702 }
1703
1704 host->clk = clk_get(&pdev->dev, "sdi");
1705 if (IS_ERR(host->clk)) {
1706 dev_err(&pdev->dev, "failed to find clock source.\n");
1707 ret = PTR_ERR(host->clk);
1708 host->clk = NULL;
1709 goto probe_free_dma;
1710 }
1711
1712 ret = clk_prepare_enable(host->clk);
1713 if (ret) {
1714 dev_err(&pdev->dev, "failed to enable clock source.\n");
1715 goto clk_free;
1716 }
1717
1718 host->clk_rate = clk_get_rate(host->clk);
1719
1720 mmc->ops = &s3cmci_ops;
1721 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
1722 #ifdef CONFIG_MMC_S3C_HW_SDIO_IRQ
1723 mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ;
1724 #else
1725 mmc->caps = MMC_CAP_4_BIT_DATA;
1726 #endif
1727 mmc->f_min = host->clk_rate / (host->clk_div * 256);
1728 mmc->f_max = host->clk_rate / host->clk_div;
1729
1730 if (host->pdata->ocr_avail)
1731 mmc->ocr_avail = host->pdata->ocr_avail;
1732
1733 mmc->max_blk_count = 4095;
1734 mmc->max_blk_size = 4095;
1735 mmc->max_req_size = 4095 * 512;
1736 mmc->max_seg_size = mmc->max_req_size;
1737
1738 mmc->max_segs = 128;
1739
1740 dbg(host, dbg_debug,
1741 "probe: mode:%s mapped mci_base:%p irq:%u irq_cd:%u dma:%p.\n",
1742 (host->is2440?"2440":""),
1743 host->base, host->irq, host->irq_cd, host->dma);
1744
1745 ret = s3cmci_cpufreq_register(host);
1746 if (ret) {
1747 dev_err(&pdev->dev, "failed to register cpufreq\n");
1748 goto free_dmabuf;
1749 }
1750
1751 ret = mmc_add_host(mmc);
1752 if (ret) {
1753 dev_err(&pdev->dev, "failed to add mmc host.\n");
1754 goto free_cpufreq;
1755 }
1756
1757 s3cmci_debugfs_attach(host);
1758
1759 platform_set_drvdata(pdev, mmc);
1760 dev_info(&pdev->dev, "%s - using %s, %s SDIO IRQ\n", mmc_hostname(mmc),
1761 s3cmci_host_usedma(host) ? "dma" : "pio",
1762 mmc->caps & MMC_CAP_SDIO_IRQ ? "hw" : "sw");
1763
1764 return 0;
1765
1766 free_cpufreq:
1767 s3cmci_cpufreq_deregister(host);
1768
1769 free_dmabuf:
1770 clk_disable_unprepare(host->clk);
1771
1772 clk_free:
1773 clk_put(host->clk);
1774
1775 probe_free_dma:
1776 if (s3cmci_host_usedma(host))
1777 dma_release_channel(host->dma);
1778
1779 probe_free_gpio_wp:
1780 if (!host->pdata->no_wprotect)
1781 gpio_free(host->pdata->gpio_wprotect);
1782
1783 probe_free_gpio_cd:
1784 if (!host->pdata->no_detect)
1785 gpio_free(host->pdata->gpio_detect);
1786
1787 probe_free_irq_cd:
1788 if (host->irq_cd >= 0)
1789 free_irq(host->irq_cd, host);
1790
1791 probe_free_irq:
1792 free_irq(host->irq, host);
1793
1794 probe_iounmap:
1795 iounmap(host->base);
1796
1797 probe_free_mem_region:
1798 release_mem_region(host->mem->start, resource_size(host->mem));
1799
1800 probe_free_gpio:
1801 for (i = S3C2410_GPE(5); i <= S3C2410_GPE(10); i++)
1802 gpio_free(i);
1803
1804 probe_free_host:
1805 mmc_free_host(mmc);
1806
1807 probe_out:
1808 return ret;
1809 }
1810
s3cmci_shutdown(struct platform_device * pdev)1811 static void s3cmci_shutdown(struct platform_device *pdev)
1812 {
1813 struct mmc_host *mmc = platform_get_drvdata(pdev);
1814 struct s3cmci_host *host = mmc_priv(mmc);
1815
1816 if (host->irq_cd >= 0)
1817 free_irq(host->irq_cd, host);
1818
1819 s3cmci_debugfs_remove(host);
1820 s3cmci_cpufreq_deregister(host);
1821 mmc_remove_host(mmc);
1822 clk_disable_unprepare(host->clk);
1823 }
1824
s3cmci_remove(struct platform_device * pdev)1825 static int s3cmci_remove(struct platform_device *pdev)
1826 {
1827 struct mmc_host *mmc = platform_get_drvdata(pdev);
1828 struct s3cmci_host *host = mmc_priv(mmc);
1829 struct s3c24xx_mci_pdata *pd = host->pdata;
1830 int i;
1831
1832 s3cmci_shutdown(pdev);
1833
1834 clk_put(host->clk);
1835
1836 tasklet_disable(&host->pio_tasklet);
1837
1838 if (s3cmci_host_usedma(host))
1839 dma_release_channel(host->dma);
1840
1841 free_irq(host->irq, host);
1842
1843 if (!pd->no_wprotect)
1844 gpio_free(pd->gpio_wprotect);
1845
1846 if (!pd->no_detect)
1847 gpio_free(pd->gpio_detect);
1848
1849 for (i = S3C2410_GPE(5); i <= S3C2410_GPE(10); i++)
1850 gpio_free(i);
1851
1852
1853 iounmap(host->base);
1854 release_mem_region(host->mem->start, resource_size(host->mem));
1855
1856 mmc_free_host(mmc);
1857 return 0;
1858 }
1859
1860 static struct platform_device_id s3cmci_driver_ids[] = {
1861 {
1862 .name = "s3c2410-sdi",
1863 .driver_data = 0,
1864 }, {
1865 .name = "s3c2412-sdi",
1866 .driver_data = 1,
1867 }, {
1868 .name = "s3c2440-sdi",
1869 .driver_data = 1,
1870 },
1871 { }
1872 };
1873
1874 MODULE_DEVICE_TABLE(platform, s3cmci_driver_ids);
1875
1876 static struct platform_driver s3cmci_driver = {
1877 .driver = {
1878 .name = "s3c-sdi",
1879 },
1880 .id_table = s3cmci_driver_ids,
1881 .probe = s3cmci_probe,
1882 .remove = s3cmci_remove,
1883 .shutdown = s3cmci_shutdown,
1884 };
1885
1886 module_platform_driver(s3cmci_driver);
1887
1888 MODULE_DESCRIPTION("Samsung S3C MMC/SD Card Interface driver");
1889 MODULE_LICENSE("GPL v2");
1890 MODULE_AUTHOR("Thomas Kleffel <tk@maintech.de>, Ben Dooks <ben-linux@fluff.org>");
1891