1 /* Freescale Enhanced Local Bus Controller NAND driver
2 *
3 * Copyright © 2006-2007, 2010 Freescale Semiconductor
4 *
5 * Authors: Nick Spence <nick.spence@freescale.com>,
6 * Scott Wood <scottwood@freescale.com>
7 * Jack Lan <jack.lan@freescale.com>
8 * Roy Zang <tie-fei.zang@freescale.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 */
24
25 #include <linux/module.h>
26 #include <linux/types.h>
27 #include <linux/kernel.h>
28 #include <linux/string.h>
29 #include <linux/ioport.h>
30 #include <linux/of_address.h>
31 #include <linux/of_platform.h>
32 #include <linux/platform_device.h>
33 #include <linux/slab.h>
34 #include <linux/interrupt.h>
35
36 #include <linux/mtd/mtd.h>
37 #include <linux/mtd/nand.h>
38 #include <linux/mtd/nand_ecc.h>
39 #include <linux/mtd/partitions.h>
40
41 #include <asm/io.h>
42 #include <asm/fsl_lbc.h>
43
44 #define MAX_BANKS 8
45 #define ERR_BYTE 0xFF /* Value returned for read bytes when read failed */
46 #define FCM_TIMEOUT_MSECS 500 /* Maximum number of mSecs to wait for FCM */
47
48 /* mtd information per set */
49
50 struct fsl_elbc_mtd {
51 struct mtd_info mtd;
52 struct nand_chip chip;
53 struct fsl_lbc_ctrl *ctrl;
54
55 struct device *dev;
56 int bank; /* Chip select bank number */
57 u8 __iomem *vbase; /* Chip select base virtual address */
58 int page_size; /* NAND page size (0=512, 1=2048) */
59 unsigned int fmr; /* FCM Flash Mode Register value */
60 };
61
62 /* Freescale eLBC FCM controller information */
63
64 struct fsl_elbc_fcm_ctrl {
65 struct nand_hw_control controller;
66 struct fsl_elbc_mtd *chips[MAX_BANKS];
67
68 u8 __iomem *addr; /* Address of assigned FCM buffer */
69 unsigned int page; /* Last page written to / read from */
70 unsigned int read_bytes; /* Number of bytes read during command */
71 unsigned int column; /* Saved column from SEQIN */
72 unsigned int index; /* Pointer to next byte to 'read' */
73 unsigned int status; /* status read from LTESR after last op */
74 unsigned int mdr; /* UPM/FCM Data Register value */
75 unsigned int use_mdr; /* Non zero if the MDR is to be set */
76 unsigned int oob; /* Non zero if operating on OOB data */
77 unsigned int counter; /* counter for the initializations */
78 unsigned int max_bitflips; /* Saved during READ0 cmd */
79 };
80
81 /* These map to the positions used by the FCM hardware ECC generator */
82
83 /* Small Page FLASH with FMR[ECCM] = 0 */
84 static struct nand_ecclayout fsl_elbc_oob_sp_eccm0 = {
85 .eccbytes = 3,
86 .eccpos = {6, 7, 8},
87 .oobfree = { {0, 5}, {9, 7} },
88 };
89
90 /* Small Page FLASH with FMR[ECCM] = 1 */
91 static struct nand_ecclayout fsl_elbc_oob_sp_eccm1 = {
92 .eccbytes = 3,
93 .eccpos = {8, 9, 10},
94 .oobfree = { {0, 5}, {6, 2}, {11, 5} },
95 };
96
97 /* Large Page FLASH with FMR[ECCM] = 0 */
98 static struct nand_ecclayout fsl_elbc_oob_lp_eccm0 = {
99 .eccbytes = 12,
100 .eccpos = {6, 7, 8, 22, 23, 24, 38, 39, 40, 54, 55, 56},
101 .oobfree = { {1, 5}, {9, 13}, {25, 13}, {41, 13}, {57, 7} },
102 };
103
104 /* Large Page FLASH with FMR[ECCM] = 1 */
105 static struct nand_ecclayout fsl_elbc_oob_lp_eccm1 = {
106 .eccbytes = 12,
107 .eccpos = {8, 9, 10, 24, 25, 26, 40, 41, 42, 56, 57, 58},
108 .oobfree = { {1, 7}, {11, 13}, {27, 13}, {43, 13}, {59, 5} },
109 };
110
111 /*
112 * ELBC may use HW ECC, so that OOB offsets, that NAND core uses for bbt,
113 * interfere with ECC positions, that's why we implement our own descriptors.
114 * OOB {11, 5}, works for both SP and LP chips, with ECCM = 1 and ECCM = 0.
115 */
116 static u8 bbt_pattern[] = {'B', 'b', 't', '0' };
117 static u8 mirror_pattern[] = {'1', 't', 'b', 'B' };
118
119 static struct nand_bbt_descr bbt_main_descr = {
120 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
121 NAND_BBT_2BIT | NAND_BBT_VERSION,
122 .offs = 11,
123 .len = 4,
124 .veroffs = 15,
125 .maxblocks = 4,
126 .pattern = bbt_pattern,
127 };
128
129 static struct nand_bbt_descr bbt_mirror_descr = {
130 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
131 NAND_BBT_2BIT | NAND_BBT_VERSION,
132 .offs = 11,
133 .len = 4,
134 .veroffs = 15,
135 .maxblocks = 4,
136 .pattern = mirror_pattern,
137 };
138
139 /*=================================*/
140
141 /*
142 * Set up the FCM hardware block and page address fields, and the fcm
143 * structure addr field to point to the correct FCM buffer in memory
144 */
set_addr(struct mtd_info * mtd,int column,int page_addr,int oob)145 static void set_addr(struct mtd_info *mtd, int column, int page_addr, int oob)
146 {
147 struct nand_chip *chip = mtd->priv;
148 struct fsl_elbc_mtd *priv = chip->priv;
149 struct fsl_lbc_ctrl *ctrl = priv->ctrl;
150 struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
151 struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = ctrl->nand;
152 int buf_num;
153
154 elbc_fcm_ctrl->page = page_addr;
155
156 if (priv->page_size) {
157 /*
158 * large page size chip : FPAR[PI] save the lowest 6 bits,
159 * FBAR[BLK] save the other bits.
160 */
161 out_be32(&lbc->fbar, page_addr >> 6);
162 out_be32(&lbc->fpar,
163 ((page_addr << FPAR_LP_PI_SHIFT) & FPAR_LP_PI) |
164 (oob ? FPAR_LP_MS : 0) | column);
165 buf_num = (page_addr & 1) << 2;
166 } else {
167 /*
168 * small page size chip : FPAR[PI] save the lowest 5 bits,
169 * FBAR[BLK] save the other bits.
170 */
171 out_be32(&lbc->fbar, page_addr >> 5);
172 out_be32(&lbc->fpar,
173 ((page_addr << FPAR_SP_PI_SHIFT) & FPAR_SP_PI) |
174 (oob ? FPAR_SP_MS : 0) | column);
175 buf_num = page_addr & 7;
176 }
177
178 elbc_fcm_ctrl->addr = priv->vbase + buf_num * 1024;
179 elbc_fcm_ctrl->index = column;
180
181 /* for OOB data point to the second half of the buffer */
182 if (oob)
183 elbc_fcm_ctrl->index += priv->page_size ? 2048 : 512;
184
185 dev_vdbg(priv->dev, "set_addr: bank=%d, "
186 "elbc_fcm_ctrl->addr=0x%p (0x%p), "
187 "index %x, pes %d ps %d\n",
188 buf_num, elbc_fcm_ctrl->addr, priv->vbase,
189 elbc_fcm_ctrl->index,
190 chip->phys_erase_shift, chip->page_shift);
191 }
192
193 /*
194 * execute FCM command and wait for it to complete
195 */
fsl_elbc_run_command(struct mtd_info * mtd)196 static int fsl_elbc_run_command(struct mtd_info *mtd)
197 {
198 struct nand_chip *chip = mtd->priv;
199 struct fsl_elbc_mtd *priv = chip->priv;
200 struct fsl_lbc_ctrl *ctrl = priv->ctrl;
201 struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = ctrl->nand;
202 struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
203
204 /* Setup the FMR[OP] to execute without write protection */
205 out_be32(&lbc->fmr, priv->fmr | 3);
206 if (elbc_fcm_ctrl->use_mdr)
207 out_be32(&lbc->mdr, elbc_fcm_ctrl->mdr);
208
209 dev_vdbg(priv->dev,
210 "fsl_elbc_run_command: fmr=%08x fir=%08x fcr=%08x\n",
211 in_be32(&lbc->fmr), in_be32(&lbc->fir), in_be32(&lbc->fcr));
212 dev_vdbg(priv->dev,
213 "fsl_elbc_run_command: fbar=%08x fpar=%08x "
214 "fbcr=%08x bank=%d\n",
215 in_be32(&lbc->fbar), in_be32(&lbc->fpar),
216 in_be32(&lbc->fbcr), priv->bank);
217
218 ctrl->irq_status = 0;
219 /* execute special operation */
220 out_be32(&lbc->lsor, priv->bank);
221
222 /* wait for FCM complete flag or timeout */
223 wait_event_timeout(ctrl->irq_wait, ctrl->irq_status,
224 FCM_TIMEOUT_MSECS * HZ/1000);
225 elbc_fcm_ctrl->status = ctrl->irq_status;
226 /* store mdr value in case it was needed */
227 if (elbc_fcm_ctrl->use_mdr)
228 elbc_fcm_ctrl->mdr = in_be32(&lbc->mdr);
229
230 elbc_fcm_ctrl->use_mdr = 0;
231
232 if (elbc_fcm_ctrl->status != LTESR_CC) {
233 dev_info(priv->dev,
234 "command failed: fir %x fcr %x status %x mdr %x\n",
235 in_be32(&lbc->fir), in_be32(&lbc->fcr),
236 elbc_fcm_ctrl->status, elbc_fcm_ctrl->mdr);
237 return -EIO;
238 }
239
240 if (chip->ecc.mode != NAND_ECC_HW)
241 return 0;
242
243 elbc_fcm_ctrl->max_bitflips = 0;
244
245 if (elbc_fcm_ctrl->read_bytes == mtd->writesize + mtd->oobsize) {
246 uint32_t lteccr = in_be32(&lbc->lteccr);
247 /*
248 * if command was a full page read and the ELBC
249 * has the LTECCR register, then bits 12-15 (ppc order) of
250 * LTECCR indicates which 512 byte sub-pages had fixed errors.
251 * bits 28-31 are uncorrectable errors, marked elsewhere.
252 * for small page nand only 1 bit is used.
253 * if the ELBC doesn't have the lteccr register it reads 0
254 * FIXME: 4 bits can be corrected on NANDs with 2k pages, so
255 * count the number of sub-pages with bitflips and update
256 * ecc_stats.corrected accordingly.
257 */
258 if (lteccr & 0x000F000F)
259 out_be32(&lbc->lteccr, 0x000F000F); /* clear lteccr */
260 if (lteccr & 0x000F0000) {
261 mtd->ecc_stats.corrected++;
262 elbc_fcm_ctrl->max_bitflips = 1;
263 }
264 }
265
266 return 0;
267 }
268
fsl_elbc_do_read(struct nand_chip * chip,int oob)269 static void fsl_elbc_do_read(struct nand_chip *chip, int oob)
270 {
271 struct fsl_elbc_mtd *priv = chip->priv;
272 struct fsl_lbc_ctrl *ctrl = priv->ctrl;
273 struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
274
275 if (priv->page_size) {
276 out_be32(&lbc->fir,
277 (FIR_OP_CM0 << FIR_OP0_SHIFT) |
278 (FIR_OP_CA << FIR_OP1_SHIFT) |
279 (FIR_OP_PA << FIR_OP2_SHIFT) |
280 (FIR_OP_CM1 << FIR_OP3_SHIFT) |
281 (FIR_OP_RBW << FIR_OP4_SHIFT));
282
283 out_be32(&lbc->fcr, (NAND_CMD_READ0 << FCR_CMD0_SHIFT) |
284 (NAND_CMD_READSTART << FCR_CMD1_SHIFT));
285 } else {
286 out_be32(&lbc->fir,
287 (FIR_OP_CM0 << FIR_OP0_SHIFT) |
288 (FIR_OP_CA << FIR_OP1_SHIFT) |
289 (FIR_OP_PA << FIR_OP2_SHIFT) |
290 (FIR_OP_RBW << FIR_OP3_SHIFT));
291
292 if (oob)
293 out_be32(&lbc->fcr, NAND_CMD_READOOB << FCR_CMD0_SHIFT);
294 else
295 out_be32(&lbc->fcr, NAND_CMD_READ0 << FCR_CMD0_SHIFT);
296 }
297 }
298
299 /* cmdfunc send commands to the FCM */
fsl_elbc_cmdfunc(struct mtd_info * mtd,unsigned int command,int column,int page_addr)300 static void fsl_elbc_cmdfunc(struct mtd_info *mtd, unsigned int command,
301 int column, int page_addr)
302 {
303 struct nand_chip *chip = mtd->priv;
304 struct fsl_elbc_mtd *priv = chip->priv;
305 struct fsl_lbc_ctrl *ctrl = priv->ctrl;
306 struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = ctrl->nand;
307 struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
308
309 elbc_fcm_ctrl->use_mdr = 0;
310
311 /* clear the read buffer */
312 elbc_fcm_ctrl->read_bytes = 0;
313 if (command != NAND_CMD_PAGEPROG)
314 elbc_fcm_ctrl->index = 0;
315
316 switch (command) {
317 /* READ0 and READ1 read the entire buffer to use hardware ECC. */
318 case NAND_CMD_READ1:
319 column += 256;
320
321 /* fall-through */
322 case NAND_CMD_READ0:
323 dev_dbg(priv->dev,
324 "fsl_elbc_cmdfunc: NAND_CMD_READ0, page_addr:"
325 " 0x%x, column: 0x%x.\n", page_addr, column);
326
327
328 out_be32(&lbc->fbcr, 0); /* read entire page to enable ECC */
329 set_addr(mtd, 0, page_addr, 0);
330
331 elbc_fcm_ctrl->read_bytes = mtd->writesize + mtd->oobsize;
332 elbc_fcm_ctrl->index += column;
333
334 fsl_elbc_do_read(chip, 0);
335 fsl_elbc_run_command(mtd);
336 return;
337
338 /* READOOB reads only the OOB because no ECC is performed. */
339 case NAND_CMD_READOOB:
340 dev_vdbg(priv->dev,
341 "fsl_elbc_cmdfunc: NAND_CMD_READOOB, page_addr:"
342 " 0x%x, column: 0x%x.\n", page_addr, column);
343
344 out_be32(&lbc->fbcr, mtd->oobsize - column);
345 set_addr(mtd, column, page_addr, 1);
346
347 elbc_fcm_ctrl->read_bytes = mtd->writesize + mtd->oobsize;
348
349 fsl_elbc_do_read(chip, 1);
350 fsl_elbc_run_command(mtd);
351 return;
352
353 case NAND_CMD_READID:
354 case NAND_CMD_PARAM:
355 dev_vdbg(priv->dev, "fsl_elbc_cmdfunc: NAND_CMD %x\n", command);
356
357 out_be32(&lbc->fir, (FIR_OP_CM0 << FIR_OP0_SHIFT) |
358 (FIR_OP_UA << FIR_OP1_SHIFT) |
359 (FIR_OP_RBW << FIR_OP2_SHIFT));
360 out_be32(&lbc->fcr, command << FCR_CMD0_SHIFT);
361 /*
362 * although currently it's 8 bytes for READID, we always read
363 * the maximum 256 bytes(for PARAM)
364 */
365 out_be32(&lbc->fbcr, 256);
366 elbc_fcm_ctrl->read_bytes = 256;
367 elbc_fcm_ctrl->use_mdr = 1;
368 elbc_fcm_ctrl->mdr = column;
369 set_addr(mtd, 0, 0, 0);
370 fsl_elbc_run_command(mtd);
371 return;
372
373 /* ERASE1 stores the block and page address */
374 case NAND_CMD_ERASE1:
375 dev_vdbg(priv->dev,
376 "fsl_elbc_cmdfunc: NAND_CMD_ERASE1, "
377 "page_addr: 0x%x.\n", page_addr);
378 set_addr(mtd, 0, page_addr, 0);
379 return;
380
381 /* ERASE2 uses the block and page address from ERASE1 */
382 case NAND_CMD_ERASE2:
383 dev_vdbg(priv->dev, "fsl_elbc_cmdfunc: NAND_CMD_ERASE2.\n");
384
385 out_be32(&lbc->fir,
386 (FIR_OP_CM0 << FIR_OP0_SHIFT) |
387 (FIR_OP_PA << FIR_OP1_SHIFT) |
388 (FIR_OP_CM2 << FIR_OP2_SHIFT) |
389 (FIR_OP_CW1 << FIR_OP3_SHIFT) |
390 (FIR_OP_RS << FIR_OP4_SHIFT));
391
392 out_be32(&lbc->fcr,
393 (NAND_CMD_ERASE1 << FCR_CMD0_SHIFT) |
394 (NAND_CMD_STATUS << FCR_CMD1_SHIFT) |
395 (NAND_CMD_ERASE2 << FCR_CMD2_SHIFT));
396
397 out_be32(&lbc->fbcr, 0);
398 elbc_fcm_ctrl->read_bytes = 0;
399 elbc_fcm_ctrl->use_mdr = 1;
400
401 fsl_elbc_run_command(mtd);
402 return;
403
404 /* SEQIN sets up the addr buffer and all registers except the length */
405 case NAND_CMD_SEQIN: {
406 __be32 fcr;
407 dev_vdbg(priv->dev,
408 "fsl_elbc_cmdfunc: NAND_CMD_SEQIN/PAGE_PROG, "
409 "page_addr: 0x%x, column: 0x%x.\n",
410 page_addr, column);
411
412 elbc_fcm_ctrl->column = column;
413 elbc_fcm_ctrl->use_mdr = 1;
414
415 if (column >= mtd->writesize) {
416 /* OOB area */
417 column -= mtd->writesize;
418 elbc_fcm_ctrl->oob = 1;
419 } else {
420 WARN_ON(column != 0);
421 elbc_fcm_ctrl->oob = 0;
422 }
423
424 fcr = (NAND_CMD_STATUS << FCR_CMD1_SHIFT) |
425 (NAND_CMD_SEQIN << FCR_CMD2_SHIFT) |
426 (NAND_CMD_PAGEPROG << FCR_CMD3_SHIFT);
427
428 if (priv->page_size) {
429 out_be32(&lbc->fir,
430 (FIR_OP_CM2 << FIR_OP0_SHIFT) |
431 (FIR_OP_CA << FIR_OP1_SHIFT) |
432 (FIR_OP_PA << FIR_OP2_SHIFT) |
433 (FIR_OP_WB << FIR_OP3_SHIFT) |
434 (FIR_OP_CM3 << FIR_OP4_SHIFT) |
435 (FIR_OP_CW1 << FIR_OP5_SHIFT) |
436 (FIR_OP_RS << FIR_OP6_SHIFT));
437 } else {
438 out_be32(&lbc->fir,
439 (FIR_OP_CM0 << FIR_OP0_SHIFT) |
440 (FIR_OP_CM2 << FIR_OP1_SHIFT) |
441 (FIR_OP_CA << FIR_OP2_SHIFT) |
442 (FIR_OP_PA << FIR_OP3_SHIFT) |
443 (FIR_OP_WB << FIR_OP4_SHIFT) |
444 (FIR_OP_CM3 << FIR_OP5_SHIFT) |
445 (FIR_OP_CW1 << FIR_OP6_SHIFT) |
446 (FIR_OP_RS << FIR_OP7_SHIFT));
447
448 if (elbc_fcm_ctrl->oob)
449 /* OOB area --> READOOB */
450 fcr |= NAND_CMD_READOOB << FCR_CMD0_SHIFT;
451 else
452 /* First 256 bytes --> READ0 */
453 fcr |= NAND_CMD_READ0 << FCR_CMD0_SHIFT;
454 }
455
456 out_be32(&lbc->fcr, fcr);
457 set_addr(mtd, column, page_addr, elbc_fcm_ctrl->oob);
458 return;
459 }
460
461 /* PAGEPROG reuses all of the setup from SEQIN and adds the length */
462 case NAND_CMD_PAGEPROG: {
463 dev_vdbg(priv->dev,
464 "fsl_elbc_cmdfunc: NAND_CMD_PAGEPROG "
465 "writing %d bytes.\n", elbc_fcm_ctrl->index);
466
467 /* if the write did not start at 0 or is not a full page
468 * then set the exact length, otherwise use a full page
469 * write so the HW generates the ECC.
470 */
471 if (elbc_fcm_ctrl->oob || elbc_fcm_ctrl->column != 0 ||
472 elbc_fcm_ctrl->index != mtd->writesize + mtd->oobsize)
473 out_be32(&lbc->fbcr,
474 elbc_fcm_ctrl->index - elbc_fcm_ctrl->column);
475 else
476 out_be32(&lbc->fbcr, 0);
477
478 fsl_elbc_run_command(mtd);
479 return;
480 }
481
482 /* CMD_STATUS must read the status byte while CEB is active */
483 /* Note - it does not wait for the ready line */
484 case NAND_CMD_STATUS:
485 out_be32(&lbc->fir,
486 (FIR_OP_CM0 << FIR_OP0_SHIFT) |
487 (FIR_OP_RBW << FIR_OP1_SHIFT));
488 out_be32(&lbc->fcr, NAND_CMD_STATUS << FCR_CMD0_SHIFT);
489 out_be32(&lbc->fbcr, 1);
490 set_addr(mtd, 0, 0, 0);
491 elbc_fcm_ctrl->read_bytes = 1;
492
493 fsl_elbc_run_command(mtd);
494
495 /* The chip always seems to report that it is
496 * write-protected, even when it is not.
497 */
498 setbits8(elbc_fcm_ctrl->addr, NAND_STATUS_WP);
499 return;
500
501 /* RESET without waiting for the ready line */
502 case NAND_CMD_RESET:
503 dev_dbg(priv->dev, "fsl_elbc_cmdfunc: NAND_CMD_RESET.\n");
504 out_be32(&lbc->fir, FIR_OP_CM0 << FIR_OP0_SHIFT);
505 out_be32(&lbc->fcr, NAND_CMD_RESET << FCR_CMD0_SHIFT);
506 fsl_elbc_run_command(mtd);
507 return;
508
509 default:
510 dev_err(priv->dev,
511 "fsl_elbc_cmdfunc: error, unsupported command 0x%x.\n",
512 command);
513 }
514 }
515
fsl_elbc_select_chip(struct mtd_info * mtd,int chip)516 static void fsl_elbc_select_chip(struct mtd_info *mtd, int chip)
517 {
518 /* The hardware does not seem to support multiple
519 * chips per bank.
520 */
521 }
522
523 /*
524 * Write buf to the FCM Controller Data Buffer
525 */
fsl_elbc_write_buf(struct mtd_info * mtd,const u8 * buf,int len)526 static void fsl_elbc_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
527 {
528 struct nand_chip *chip = mtd->priv;
529 struct fsl_elbc_mtd *priv = chip->priv;
530 struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = priv->ctrl->nand;
531 unsigned int bufsize = mtd->writesize + mtd->oobsize;
532
533 if (len <= 0) {
534 dev_err(priv->dev, "write_buf of %d bytes", len);
535 elbc_fcm_ctrl->status = 0;
536 return;
537 }
538
539 if ((unsigned int)len > bufsize - elbc_fcm_ctrl->index) {
540 dev_err(priv->dev,
541 "write_buf beyond end of buffer "
542 "(%d requested, %u available)\n",
543 len, bufsize - elbc_fcm_ctrl->index);
544 len = bufsize - elbc_fcm_ctrl->index;
545 }
546
547 memcpy_toio(&elbc_fcm_ctrl->addr[elbc_fcm_ctrl->index], buf, len);
548 /*
549 * This is workaround for the weird elbc hangs during nand write,
550 * Scott Wood says: "...perhaps difference in how long it takes a
551 * write to make it through the localbus compared to a write to IMMR
552 * is causing problems, and sync isn't helping for some reason."
553 * Reading back the last byte helps though.
554 */
555 in_8(&elbc_fcm_ctrl->addr[elbc_fcm_ctrl->index] + len - 1);
556
557 elbc_fcm_ctrl->index += len;
558 }
559
560 /*
561 * read a byte from either the FCM hardware buffer if it has any data left
562 * otherwise issue a command to read a single byte.
563 */
fsl_elbc_read_byte(struct mtd_info * mtd)564 static u8 fsl_elbc_read_byte(struct mtd_info *mtd)
565 {
566 struct nand_chip *chip = mtd->priv;
567 struct fsl_elbc_mtd *priv = chip->priv;
568 struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = priv->ctrl->nand;
569
570 /* If there are still bytes in the FCM, then use the next byte. */
571 if (elbc_fcm_ctrl->index < elbc_fcm_ctrl->read_bytes)
572 return in_8(&elbc_fcm_ctrl->addr[elbc_fcm_ctrl->index++]);
573
574 dev_err(priv->dev, "read_byte beyond end of buffer\n");
575 return ERR_BYTE;
576 }
577
578 /*
579 * Read from the FCM Controller Data Buffer
580 */
fsl_elbc_read_buf(struct mtd_info * mtd,u8 * buf,int len)581 static void fsl_elbc_read_buf(struct mtd_info *mtd, u8 *buf, int len)
582 {
583 struct nand_chip *chip = mtd->priv;
584 struct fsl_elbc_mtd *priv = chip->priv;
585 struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = priv->ctrl->nand;
586 int avail;
587
588 if (len < 0)
589 return;
590
591 avail = min((unsigned int)len,
592 elbc_fcm_ctrl->read_bytes - elbc_fcm_ctrl->index);
593 memcpy_fromio(buf, &elbc_fcm_ctrl->addr[elbc_fcm_ctrl->index], avail);
594 elbc_fcm_ctrl->index += avail;
595
596 if (len > avail)
597 dev_err(priv->dev,
598 "read_buf beyond end of buffer "
599 "(%d requested, %d available)\n",
600 len, avail);
601 }
602
603 /* This function is called after Program and Erase Operations to
604 * check for success or failure.
605 */
fsl_elbc_wait(struct mtd_info * mtd,struct nand_chip * chip)606 static int fsl_elbc_wait(struct mtd_info *mtd, struct nand_chip *chip)
607 {
608 struct fsl_elbc_mtd *priv = chip->priv;
609 struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = priv->ctrl->nand;
610
611 if (elbc_fcm_ctrl->status != LTESR_CC)
612 return NAND_STATUS_FAIL;
613
614 /* The chip always seems to report that it is
615 * write-protected, even when it is not.
616 */
617 return (elbc_fcm_ctrl->mdr & 0xff) | NAND_STATUS_WP;
618 }
619
fsl_elbc_chip_init_tail(struct mtd_info * mtd)620 static int fsl_elbc_chip_init_tail(struct mtd_info *mtd)
621 {
622 struct nand_chip *chip = mtd->priv;
623 struct fsl_elbc_mtd *priv = chip->priv;
624 struct fsl_lbc_ctrl *ctrl = priv->ctrl;
625 struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
626 unsigned int al;
627
628 /* calculate FMR Address Length field */
629 al = 0;
630 if (chip->pagemask & 0xffff0000)
631 al++;
632 if (chip->pagemask & 0xff000000)
633 al++;
634
635 priv->fmr |= al << FMR_AL_SHIFT;
636
637 dev_dbg(priv->dev, "fsl_elbc_init: nand->numchips = %d\n",
638 chip->numchips);
639 dev_dbg(priv->dev, "fsl_elbc_init: nand->chipsize = %lld\n",
640 chip->chipsize);
641 dev_dbg(priv->dev, "fsl_elbc_init: nand->pagemask = %8x\n",
642 chip->pagemask);
643 dev_dbg(priv->dev, "fsl_elbc_init: nand->chip_delay = %d\n",
644 chip->chip_delay);
645 dev_dbg(priv->dev, "fsl_elbc_init: nand->badblockpos = %d\n",
646 chip->badblockpos);
647 dev_dbg(priv->dev, "fsl_elbc_init: nand->chip_shift = %d\n",
648 chip->chip_shift);
649 dev_dbg(priv->dev, "fsl_elbc_init: nand->page_shift = %d\n",
650 chip->page_shift);
651 dev_dbg(priv->dev, "fsl_elbc_init: nand->phys_erase_shift = %d\n",
652 chip->phys_erase_shift);
653 dev_dbg(priv->dev, "fsl_elbc_init: nand->ecc.mode = %d\n",
654 chip->ecc.mode);
655 dev_dbg(priv->dev, "fsl_elbc_init: nand->ecc.steps = %d\n",
656 chip->ecc.steps);
657 dev_dbg(priv->dev, "fsl_elbc_init: nand->ecc.bytes = %d\n",
658 chip->ecc.bytes);
659 dev_dbg(priv->dev, "fsl_elbc_init: nand->ecc.total = %d\n",
660 chip->ecc.total);
661 dev_dbg(priv->dev, "fsl_elbc_init: nand->ecc.layout = %p\n",
662 chip->ecc.layout);
663 dev_dbg(priv->dev, "fsl_elbc_init: mtd->flags = %08x\n", mtd->flags);
664 dev_dbg(priv->dev, "fsl_elbc_init: mtd->size = %lld\n", mtd->size);
665 dev_dbg(priv->dev, "fsl_elbc_init: mtd->erasesize = %d\n",
666 mtd->erasesize);
667 dev_dbg(priv->dev, "fsl_elbc_init: mtd->writesize = %d\n",
668 mtd->writesize);
669 dev_dbg(priv->dev, "fsl_elbc_init: mtd->oobsize = %d\n",
670 mtd->oobsize);
671
672 /* adjust Option Register and ECC to match Flash page size */
673 if (mtd->writesize == 512) {
674 priv->page_size = 0;
675 clrbits32(&lbc->bank[priv->bank].or, OR_FCM_PGS);
676 } else if (mtd->writesize == 2048) {
677 priv->page_size = 1;
678 setbits32(&lbc->bank[priv->bank].or, OR_FCM_PGS);
679 /* adjust ecc setup if needed */
680 if ((in_be32(&lbc->bank[priv->bank].br) & BR_DECC) ==
681 BR_DECC_CHK_GEN) {
682 chip->ecc.size = 512;
683 chip->ecc.layout = (priv->fmr & FMR_ECCM) ?
684 &fsl_elbc_oob_lp_eccm1 :
685 &fsl_elbc_oob_lp_eccm0;
686 }
687 } else {
688 dev_err(priv->dev,
689 "fsl_elbc_init: page size %d is not supported\n",
690 mtd->writesize);
691 return -1;
692 }
693
694 return 0;
695 }
696
fsl_elbc_read_page(struct mtd_info * mtd,struct nand_chip * chip,uint8_t * buf,int oob_required,int page)697 static int fsl_elbc_read_page(struct mtd_info *mtd, struct nand_chip *chip,
698 uint8_t *buf, int oob_required, int page)
699 {
700 struct fsl_elbc_mtd *priv = chip->priv;
701 struct fsl_lbc_ctrl *ctrl = priv->ctrl;
702 struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = ctrl->nand;
703
704 fsl_elbc_read_buf(mtd, buf, mtd->writesize);
705 if (oob_required)
706 fsl_elbc_read_buf(mtd, chip->oob_poi, mtd->oobsize);
707
708 if (fsl_elbc_wait(mtd, chip) & NAND_STATUS_FAIL)
709 mtd->ecc_stats.failed++;
710
711 return elbc_fcm_ctrl->max_bitflips;
712 }
713
714 /* ECC will be calculated automatically, and errors will be detected in
715 * waitfunc.
716 */
fsl_elbc_write_page(struct mtd_info * mtd,struct nand_chip * chip,const uint8_t * buf,int oob_required)717 static int fsl_elbc_write_page(struct mtd_info *mtd, struct nand_chip *chip,
718 const uint8_t *buf, int oob_required)
719 {
720 fsl_elbc_write_buf(mtd, buf, mtd->writesize);
721 fsl_elbc_write_buf(mtd, chip->oob_poi, mtd->oobsize);
722
723 return 0;
724 }
725
726 /* ECC will be calculated automatically, and errors will be detected in
727 * waitfunc.
728 */
fsl_elbc_write_subpage(struct mtd_info * mtd,struct nand_chip * chip,uint32_t offset,uint32_t data_len,const uint8_t * buf,int oob_required)729 static int fsl_elbc_write_subpage(struct mtd_info *mtd, struct nand_chip *chip,
730 uint32_t offset, uint32_t data_len,
731 const uint8_t *buf, int oob_required)
732 {
733 fsl_elbc_write_buf(mtd, buf, mtd->writesize);
734 fsl_elbc_write_buf(mtd, chip->oob_poi, mtd->oobsize);
735
736 return 0;
737 }
738
fsl_elbc_chip_init(struct fsl_elbc_mtd * priv)739 static int fsl_elbc_chip_init(struct fsl_elbc_mtd *priv)
740 {
741 struct fsl_lbc_ctrl *ctrl = priv->ctrl;
742 struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
743 struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = ctrl->nand;
744 struct nand_chip *chip = &priv->chip;
745
746 dev_dbg(priv->dev, "eLBC Set Information for bank %d\n", priv->bank);
747
748 /* Fill in fsl_elbc_mtd structure */
749 priv->mtd.priv = chip;
750 priv->mtd.owner = THIS_MODULE;
751
752 /* set timeout to maximum */
753 priv->fmr = 15 << FMR_CWTO_SHIFT;
754 if (in_be32(&lbc->bank[priv->bank].or) & OR_FCM_PGS)
755 priv->fmr |= FMR_ECCM;
756
757 /* fill in nand_chip structure */
758 /* set up function call table */
759 chip->read_byte = fsl_elbc_read_byte;
760 chip->write_buf = fsl_elbc_write_buf;
761 chip->read_buf = fsl_elbc_read_buf;
762 chip->select_chip = fsl_elbc_select_chip;
763 chip->cmdfunc = fsl_elbc_cmdfunc;
764 chip->waitfunc = fsl_elbc_wait;
765
766 chip->bbt_td = &bbt_main_descr;
767 chip->bbt_md = &bbt_mirror_descr;
768
769 /* set up nand options */
770 chip->bbt_options = NAND_BBT_USE_FLASH;
771
772 chip->controller = &elbc_fcm_ctrl->controller;
773 chip->priv = priv;
774
775 chip->ecc.read_page = fsl_elbc_read_page;
776 chip->ecc.write_page = fsl_elbc_write_page;
777 chip->ecc.write_subpage = fsl_elbc_write_subpage;
778
779 /* If CS Base Register selects full hardware ECC then use it */
780 if ((in_be32(&lbc->bank[priv->bank].br) & BR_DECC) ==
781 BR_DECC_CHK_GEN) {
782 chip->ecc.mode = NAND_ECC_HW;
783 /* put in small page settings and adjust later if needed */
784 chip->ecc.layout = (priv->fmr & FMR_ECCM) ?
785 &fsl_elbc_oob_sp_eccm1 : &fsl_elbc_oob_sp_eccm0;
786 chip->ecc.size = 512;
787 chip->ecc.bytes = 3;
788 chip->ecc.strength = 1;
789 } else {
790 /* otherwise fall back to default software ECC */
791 chip->ecc.mode = NAND_ECC_SOFT;
792 }
793
794 return 0;
795 }
796
fsl_elbc_chip_remove(struct fsl_elbc_mtd * priv)797 static int fsl_elbc_chip_remove(struct fsl_elbc_mtd *priv)
798 {
799 struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = priv->ctrl->nand;
800 nand_release(&priv->mtd);
801
802 kfree(priv->mtd.name);
803
804 if (priv->vbase)
805 iounmap(priv->vbase);
806
807 elbc_fcm_ctrl->chips[priv->bank] = NULL;
808 kfree(priv);
809 return 0;
810 }
811
812 static DEFINE_MUTEX(fsl_elbc_nand_mutex);
813
fsl_elbc_nand_probe(struct platform_device * pdev)814 static int fsl_elbc_nand_probe(struct platform_device *pdev)
815 {
816 struct fsl_lbc_regs __iomem *lbc;
817 struct fsl_elbc_mtd *priv;
818 struct resource res;
819 struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl;
820 static const char *part_probe_types[]
821 = { "cmdlinepart", "RedBoot", "ofpart", NULL };
822 int ret;
823 int bank;
824 struct device *dev;
825 struct device_node *node = pdev->dev.of_node;
826 struct mtd_part_parser_data ppdata;
827
828 ppdata.of_node = pdev->dev.of_node;
829 if (!fsl_lbc_ctrl_dev || !fsl_lbc_ctrl_dev->regs)
830 return -ENODEV;
831 lbc = fsl_lbc_ctrl_dev->regs;
832 dev = fsl_lbc_ctrl_dev->dev;
833
834 /* get, allocate and map the memory resource */
835 ret = of_address_to_resource(node, 0, &res);
836 if (ret) {
837 dev_err(dev, "failed to get resource\n");
838 return ret;
839 }
840
841 /* find which chip select it is connected to */
842 for (bank = 0; bank < MAX_BANKS; bank++)
843 if ((in_be32(&lbc->bank[bank].br) & BR_V) &&
844 (in_be32(&lbc->bank[bank].br) & BR_MSEL) == BR_MS_FCM &&
845 (in_be32(&lbc->bank[bank].br) &
846 in_be32(&lbc->bank[bank].or) & BR_BA)
847 == fsl_lbc_addr(res.start))
848 break;
849
850 if (bank >= MAX_BANKS) {
851 dev_err(dev, "address did not match any chip selects\n");
852 return -ENODEV;
853 }
854
855 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
856 if (!priv)
857 return -ENOMEM;
858
859 mutex_lock(&fsl_elbc_nand_mutex);
860 if (!fsl_lbc_ctrl_dev->nand) {
861 elbc_fcm_ctrl = kzalloc(sizeof(*elbc_fcm_ctrl), GFP_KERNEL);
862 if (!elbc_fcm_ctrl) {
863 mutex_unlock(&fsl_elbc_nand_mutex);
864 ret = -ENOMEM;
865 goto err;
866 }
867 elbc_fcm_ctrl->counter++;
868
869 spin_lock_init(&elbc_fcm_ctrl->controller.lock);
870 init_waitqueue_head(&elbc_fcm_ctrl->controller.wq);
871 fsl_lbc_ctrl_dev->nand = elbc_fcm_ctrl;
872 } else {
873 elbc_fcm_ctrl = fsl_lbc_ctrl_dev->nand;
874 }
875 mutex_unlock(&fsl_elbc_nand_mutex);
876
877 elbc_fcm_ctrl->chips[bank] = priv;
878 priv->bank = bank;
879 priv->ctrl = fsl_lbc_ctrl_dev;
880 priv->dev = &pdev->dev;
881 dev_set_drvdata(priv->dev, priv);
882
883 priv->vbase = ioremap(res.start, resource_size(&res));
884 if (!priv->vbase) {
885 dev_err(dev, "failed to map chip region\n");
886 ret = -ENOMEM;
887 goto err;
888 }
889
890 priv->mtd.name = kasprintf(GFP_KERNEL, "%llx.flash", (u64)res.start);
891 if (!priv->mtd.name) {
892 ret = -ENOMEM;
893 goto err;
894 }
895
896 ret = fsl_elbc_chip_init(priv);
897 if (ret)
898 goto err;
899
900 ret = nand_scan_ident(&priv->mtd, 1, NULL);
901 if (ret)
902 goto err;
903
904 ret = fsl_elbc_chip_init_tail(&priv->mtd);
905 if (ret)
906 goto err;
907
908 ret = nand_scan_tail(&priv->mtd);
909 if (ret)
910 goto err;
911
912 /* First look for RedBoot table or partitions on the command
913 * line, these take precedence over device tree information */
914 mtd_device_parse_register(&priv->mtd, part_probe_types, &ppdata,
915 NULL, 0);
916
917 printk(KERN_INFO "eLBC NAND device at 0x%llx, bank %d\n",
918 (unsigned long long)res.start, priv->bank);
919 return 0;
920
921 err:
922 fsl_elbc_chip_remove(priv);
923 return ret;
924 }
925
fsl_elbc_nand_remove(struct platform_device * pdev)926 static int fsl_elbc_nand_remove(struct platform_device *pdev)
927 {
928 struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = fsl_lbc_ctrl_dev->nand;
929 struct fsl_elbc_mtd *priv = dev_get_drvdata(&pdev->dev);
930
931 fsl_elbc_chip_remove(priv);
932
933 mutex_lock(&fsl_elbc_nand_mutex);
934 elbc_fcm_ctrl->counter--;
935 if (!elbc_fcm_ctrl->counter) {
936 fsl_lbc_ctrl_dev->nand = NULL;
937 kfree(elbc_fcm_ctrl);
938 }
939 mutex_unlock(&fsl_elbc_nand_mutex);
940
941 return 0;
942
943 }
944
945 static const struct of_device_id fsl_elbc_nand_match[] = {
946 { .compatible = "fsl,elbc-fcm-nand", },
947 {}
948 };
949
950 static struct platform_driver fsl_elbc_nand_driver = {
951 .driver = {
952 .name = "fsl,elbc-fcm-nand",
953 .owner = THIS_MODULE,
954 .of_match_table = fsl_elbc_nand_match,
955 },
956 .probe = fsl_elbc_nand_probe,
957 .remove = fsl_elbc_nand_remove,
958 };
959
960 module_platform_driver(fsl_elbc_nand_driver);
961
962 MODULE_LICENSE("GPL");
963 MODULE_AUTHOR("Freescale");
964 MODULE_DESCRIPTION("Freescale Enhanced Local Bus Controller MTD NAND driver");
965