1 /* 2 * Copyright (c) 2014-2017 Broadcom 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 */ 8 9 #ifndef __BCMGENET_H__ 10 #define __BCMGENET_H__ 11 12 #include <linux/skbuff.h> 13 #include <linux/netdevice.h> 14 #include <linux/spinlock.h> 15 #include <linux/clk.h> 16 #include <linux/mii.h> 17 #include <linux/if_vlan.h> 18 #include <linux/phy.h> 19 20 /* total number of Buffer Descriptors, same for Rx/Tx */ 21 #define TOTAL_DESC 256 22 23 /* which ring is descriptor based */ 24 #define DESC_INDEX 16 25 26 /* Body(1500) + EH_SIZE(14) + VLANTAG(4) + BRCMTAG(6) + FCS(4) = 1528. 27 * 1536 is multiple of 256 bytes 28 */ 29 #define ENET_BRCM_TAG_LEN 6 30 #define ENET_PAD 8 31 #define ENET_MAX_MTU_SIZE (ETH_DATA_LEN + ETH_HLEN + VLAN_HLEN + \ 32 ENET_BRCM_TAG_LEN + ETH_FCS_LEN + ENET_PAD) 33 #define DMA_MAX_BURST_LENGTH 0x10 34 35 /* misc. configuration */ 36 #define CLEAR_ALL_HFB 0xFF 37 #define DMA_FC_THRESH_HI (TOTAL_DESC >> 4) 38 #define DMA_FC_THRESH_LO 5 39 40 /* 64B receive/transmit status block */ 41 struct status_64 { 42 u32 length_status; /* length and peripheral status */ 43 u32 ext_status; /* Extended status*/ 44 u32 rx_csum; /* partial rx checksum */ 45 u32 unused1[9]; /* unused */ 46 u32 tx_csum_info; /* Tx checksum info. */ 47 u32 unused2[3]; /* unused */ 48 }; 49 50 /* Rx status bits */ 51 #define STATUS_RX_EXT_MASK 0x1FFFFF 52 #define STATUS_RX_CSUM_MASK 0xFFFF 53 #define STATUS_RX_CSUM_OK 0x10000 54 #define STATUS_RX_CSUM_FR 0x20000 55 #define STATUS_RX_PROTO_TCP 0 56 #define STATUS_RX_PROTO_UDP 1 57 #define STATUS_RX_PROTO_ICMP 2 58 #define STATUS_RX_PROTO_OTHER 3 59 #define STATUS_RX_PROTO_MASK 3 60 #define STATUS_RX_PROTO_SHIFT 18 61 #define STATUS_FILTER_INDEX_MASK 0xFFFF 62 /* Tx status bits */ 63 #define STATUS_TX_CSUM_START_MASK 0X7FFF 64 #define STATUS_TX_CSUM_START_SHIFT 16 65 #define STATUS_TX_CSUM_PROTO_UDP 0x8000 66 #define STATUS_TX_CSUM_OFFSET_MASK 0x7FFF 67 #define STATUS_TX_CSUM_LV 0x80000000 68 69 /* DMA Descriptor */ 70 #define DMA_DESC_LENGTH_STATUS 0x00 /* in bytes of data in buffer */ 71 #define DMA_DESC_ADDRESS_LO 0x04 /* lower bits of PA */ 72 #define DMA_DESC_ADDRESS_HI 0x08 /* upper 32 bits of PA, GENETv4+ */ 73 74 /* Rx/Tx common counter group */ 75 struct bcmgenet_pkt_counters { 76 u32 cnt_64; /* RO Received/Transmited 64 bytes packet */ 77 u32 cnt_127; /* RO Rx/Tx 127 bytes packet */ 78 u32 cnt_255; /* RO Rx/Tx 65-255 bytes packet */ 79 u32 cnt_511; /* RO Rx/Tx 256-511 bytes packet */ 80 u32 cnt_1023; /* RO Rx/Tx 512-1023 bytes packet */ 81 u32 cnt_1518; /* RO Rx/Tx 1024-1518 bytes packet */ 82 u32 cnt_mgv; /* RO Rx/Tx 1519-1522 good VLAN packet */ 83 u32 cnt_2047; /* RO Rx/Tx 1522-2047 bytes packet*/ 84 u32 cnt_4095; /* RO Rx/Tx 2048-4095 bytes packet*/ 85 u32 cnt_9216; /* RO Rx/Tx 4096-9216 bytes packet*/ 86 }; 87 88 /* RSV, Receive Status Vector */ 89 struct bcmgenet_rx_counters { 90 struct bcmgenet_pkt_counters pkt_cnt; 91 u32 pkt; /* RO (0x428) Received pkt count*/ 92 u32 bytes; /* RO Received byte count */ 93 u32 mca; /* RO # of Received multicast pkt */ 94 u32 bca; /* RO # of Receive broadcast pkt */ 95 u32 fcs; /* RO # of Received FCS error */ 96 u32 cf; /* RO # of Received control frame pkt*/ 97 u32 pf; /* RO # of Received pause frame pkt */ 98 u32 uo; /* RO # of unknown op code pkt */ 99 u32 aln; /* RO # of alignment error count */ 100 u32 flr; /* RO # of frame length out of range count */ 101 u32 cde; /* RO # of code error pkt */ 102 u32 fcr; /* RO # of carrier sense error pkt */ 103 u32 ovr; /* RO # of oversize pkt*/ 104 u32 jbr; /* RO # of jabber count */ 105 u32 mtue; /* RO # of MTU error pkt*/ 106 u32 pok; /* RO # of Received good pkt */ 107 u32 uc; /* RO # of unicast pkt */ 108 u32 ppp; /* RO # of PPP pkt */ 109 u32 rcrc; /* RO (0x470),# of CRC match pkt */ 110 }; 111 112 /* TSV, Transmit Status Vector */ 113 struct bcmgenet_tx_counters { 114 struct bcmgenet_pkt_counters pkt_cnt; 115 u32 pkts; /* RO (0x4a8) Transmited pkt */ 116 u32 mca; /* RO # of xmited multicast pkt */ 117 u32 bca; /* RO # of xmited broadcast pkt */ 118 u32 pf; /* RO # of xmited pause frame count */ 119 u32 cf; /* RO # of xmited control frame count */ 120 u32 fcs; /* RO # of xmited FCS error count */ 121 u32 ovr; /* RO # of xmited oversize pkt */ 122 u32 drf; /* RO # of xmited deferral pkt */ 123 u32 edf; /* RO # of xmited Excessive deferral pkt*/ 124 u32 scl; /* RO # of xmited single collision pkt */ 125 u32 mcl; /* RO # of xmited multiple collision pkt*/ 126 u32 lcl; /* RO # of xmited late collision pkt */ 127 u32 ecl; /* RO # of xmited excessive collision pkt*/ 128 u32 frg; /* RO # of xmited fragments pkt*/ 129 u32 ncl; /* RO # of xmited total collision count */ 130 u32 jbr; /* RO # of xmited jabber count*/ 131 u32 bytes; /* RO # of xmited byte count */ 132 u32 pok; /* RO # of xmited good pkt */ 133 u32 uc; /* RO (0x0x4f0)# of xmited unitcast pkt */ 134 }; 135 136 struct bcmgenet_mib_counters { 137 struct bcmgenet_rx_counters rx; 138 struct bcmgenet_tx_counters tx; 139 u32 rx_runt_cnt; 140 u32 rx_runt_fcs; 141 u32 rx_runt_fcs_align; 142 u32 rx_runt_bytes; 143 u32 rbuf_ovflow_cnt; 144 u32 rbuf_err_cnt; 145 u32 mdf_err_cnt; 146 }; 147 148 #define UMAC_HD_BKP_CTRL 0x004 149 #define HD_FC_EN (1 << 0) 150 #define HD_FC_BKOFF_OK (1 << 1) 151 #define IPG_CONFIG_RX_SHIFT 2 152 #define IPG_CONFIG_RX_MASK 0x1F 153 154 #define UMAC_CMD 0x008 155 #define CMD_TX_EN (1 << 0) 156 #define CMD_RX_EN (1 << 1) 157 #define UMAC_SPEED_10 0 158 #define UMAC_SPEED_100 1 159 #define UMAC_SPEED_1000 2 160 #define UMAC_SPEED_2500 3 161 #define CMD_SPEED_SHIFT 2 162 #define CMD_SPEED_MASK 3 163 #define CMD_PROMISC (1 << 4) 164 #define CMD_PAD_EN (1 << 5) 165 #define CMD_CRC_FWD (1 << 6) 166 #define CMD_PAUSE_FWD (1 << 7) 167 #define CMD_RX_PAUSE_IGNORE (1 << 8) 168 #define CMD_TX_ADDR_INS (1 << 9) 169 #define CMD_HD_EN (1 << 10) 170 #define CMD_SW_RESET (1 << 13) 171 #define CMD_LCL_LOOP_EN (1 << 15) 172 #define CMD_AUTO_CONFIG (1 << 22) 173 #define CMD_CNTL_FRM_EN (1 << 23) 174 #define CMD_NO_LEN_CHK (1 << 24) 175 #define CMD_RMT_LOOP_EN (1 << 25) 176 #define CMD_PRBL_EN (1 << 27) 177 #define CMD_TX_PAUSE_IGNORE (1 << 28) 178 #define CMD_TX_RX_EN (1 << 29) 179 #define CMD_RUNT_FILTER_DIS (1 << 30) 180 181 #define UMAC_MAC0 0x00C 182 #define UMAC_MAC1 0x010 183 #define UMAC_MAX_FRAME_LEN 0x014 184 185 #define UMAC_TX_FLUSH 0x334 186 187 #define UMAC_MIB_START 0x400 188 189 #define UMAC_MDIO_CMD 0x614 190 #define MDIO_START_BUSY (1 << 29) 191 #define MDIO_READ_FAIL (1 << 28) 192 #define MDIO_RD (2 << 26) 193 #define MDIO_WR (1 << 26) 194 #define MDIO_PMD_SHIFT 21 195 #define MDIO_PMD_MASK 0x1F 196 #define MDIO_REG_SHIFT 16 197 #define MDIO_REG_MASK 0x1F 198 199 #define UMAC_RBUF_OVFL_CNT_V1 0x61C 200 #define RBUF_OVFL_CNT_V2 0x80 201 #define RBUF_OVFL_CNT_V3PLUS 0x94 202 203 #define UMAC_MPD_CTRL 0x620 204 #define MPD_EN (1 << 0) 205 #define MPD_PW_EN (1 << 27) 206 #define MPD_MSEQ_LEN_SHIFT 16 207 #define MPD_MSEQ_LEN_MASK 0xFF 208 209 #define UMAC_MPD_PW_MS 0x624 210 #define UMAC_MPD_PW_LS 0x628 211 #define UMAC_RBUF_ERR_CNT_V1 0x634 212 #define RBUF_ERR_CNT_V2 0x84 213 #define RBUF_ERR_CNT_V3PLUS 0x98 214 #define UMAC_MDF_ERR_CNT 0x638 215 #define UMAC_MDF_CTRL 0x650 216 #define UMAC_MDF_ADDR 0x654 217 #define UMAC_MIB_CTRL 0x580 218 #define MIB_RESET_RX (1 << 0) 219 #define MIB_RESET_RUNT (1 << 1) 220 #define MIB_RESET_TX (1 << 2) 221 222 #define RBUF_CTRL 0x00 223 #define RBUF_64B_EN (1 << 0) 224 #define RBUF_ALIGN_2B (1 << 1) 225 #define RBUF_BAD_DIS (1 << 2) 226 227 #define RBUF_STATUS 0x0C 228 #define RBUF_STATUS_WOL (1 << 0) 229 #define RBUF_STATUS_MPD_INTR_ACTIVE (1 << 1) 230 #define RBUF_STATUS_ACPI_INTR_ACTIVE (1 << 2) 231 232 #define RBUF_CHK_CTRL 0x14 233 #define RBUF_RXCHK_EN (1 << 0) 234 #define RBUF_SKIP_FCS (1 << 4) 235 236 #define RBUF_TBUF_SIZE_CTRL 0xb4 237 238 #define RBUF_HFB_CTRL_V1 0x38 239 #define RBUF_HFB_FILTER_EN_SHIFT 16 240 #define RBUF_HFB_FILTER_EN_MASK 0xffff0000 241 #define RBUF_HFB_EN (1 << 0) 242 #define RBUF_HFB_256B (1 << 1) 243 #define RBUF_ACPI_EN (1 << 2) 244 245 #define RBUF_HFB_LEN_V1 0x3C 246 #define RBUF_FLTR_LEN_MASK 0xFF 247 #define RBUF_FLTR_LEN_SHIFT 8 248 249 #define TBUF_CTRL 0x00 250 #define TBUF_BP_MC 0x0C 251 252 #define TBUF_CTRL_V1 0x80 253 #define TBUF_BP_MC_V1 0xA0 254 255 #define HFB_CTRL 0x00 256 #define HFB_FLT_ENABLE_V3PLUS 0x04 257 #define HFB_FLT_LEN_V2 0x04 258 #define HFB_FLT_LEN_V3PLUS 0x1C 259 260 /* uniMac intrl2 registers */ 261 #define INTRL2_CPU_STAT 0x00 262 #define INTRL2_CPU_SET 0x04 263 #define INTRL2_CPU_CLEAR 0x08 264 #define INTRL2_CPU_MASK_STATUS 0x0C 265 #define INTRL2_CPU_MASK_SET 0x10 266 #define INTRL2_CPU_MASK_CLEAR 0x14 267 268 /* INTRL2 instance 0 definitions */ 269 #define UMAC_IRQ_SCB (1 << 0) 270 #define UMAC_IRQ_EPHY (1 << 1) 271 #define UMAC_IRQ_PHY_DET_R (1 << 2) 272 #define UMAC_IRQ_PHY_DET_F (1 << 3) 273 #define UMAC_IRQ_LINK_UP (1 << 4) 274 #define UMAC_IRQ_LINK_DOWN (1 << 5) 275 #define UMAC_IRQ_UMAC (1 << 6) 276 #define UMAC_IRQ_UMAC_TSV (1 << 7) 277 #define UMAC_IRQ_TBUF_UNDERRUN (1 << 8) 278 #define UMAC_IRQ_RBUF_OVERFLOW (1 << 9) 279 #define UMAC_IRQ_HFB_SM (1 << 10) 280 #define UMAC_IRQ_HFB_MM (1 << 11) 281 #define UMAC_IRQ_MPD_R (1 << 12) 282 #define UMAC_IRQ_RXDMA_MBDONE (1 << 13) 283 #define UMAC_IRQ_RXDMA_PDONE (1 << 14) 284 #define UMAC_IRQ_RXDMA_BDONE (1 << 15) 285 #define UMAC_IRQ_TXDMA_MBDONE (1 << 16) 286 #define UMAC_IRQ_TXDMA_PDONE (1 << 17) 287 #define UMAC_IRQ_TXDMA_BDONE (1 << 18) 288 /* Only valid for GENETv3+ */ 289 #define UMAC_IRQ_MDIO_DONE (1 << 23) 290 #define UMAC_IRQ_MDIO_ERROR (1 << 24) 291 292 /* Register block offsets */ 293 #define GENET_SYS_OFF 0x0000 294 #define GENET_GR_BRIDGE_OFF 0x0040 295 #define GENET_EXT_OFF 0x0080 296 #define GENET_INTRL2_0_OFF 0x0200 297 #define GENET_INTRL2_1_OFF 0x0240 298 #define GENET_RBUF_OFF 0x0300 299 #define GENET_UMAC_OFF 0x0800 300 301 /* SYS block offsets and register definitions */ 302 #define SYS_REV_CTRL 0x00 303 #define SYS_PORT_CTRL 0x04 304 #define PORT_MODE_INT_EPHY 0 305 #define PORT_MODE_INT_GPHY 1 306 #define PORT_MODE_EXT_EPHY 2 307 #define PORT_MODE_EXT_GPHY 3 308 #define PORT_MODE_EXT_RVMII_25 (4 | BIT(4)) 309 #define PORT_MODE_EXT_RVMII_50 4 310 #define LED_ACT_SOURCE_MAC (1 << 9) 311 312 #define SYS_RBUF_FLUSH_CTRL 0x08 313 #define SYS_TBUF_FLUSH_CTRL 0x0C 314 #define RBUF_FLUSH_CTRL_V1 0x04 315 316 /* Ext block register offsets and definitions */ 317 #define EXT_EXT_PWR_MGMT 0x00 318 #define EXT_PWR_DOWN_BIAS (1 << 0) 319 #define EXT_PWR_DOWN_DLL (1 << 1) 320 #define EXT_PWR_DOWN_PHY (1 << 2) 321 #define EXT_PWR_DN_EN_LD (1 << 3) 322 #define EXT_ENERGY_DET (1 << 4) 323 #define EXT_IDDQ_FROM_PHY (1 << 5) 324 #define EXT_PHY_RESET (1 << 8) 325 #define EXT_ENERGY_DET_MASK (1 << 12) 326 327 #define EXT_RGMII_OOB_CTRL 0x0C 328 #define RGMII_LINK (1 << 4) 329 #define OOB_DISABLE (1 << 5) 330 #define RGMII_MODE_EN (1 << 6) 331 #define ID_MODE_DIS (1 << 16) 332 333 #define EXT_GPHY_CTRL 0x1C 334 #define EXT_CFG_IDDQ_BIAS (1 << 0) 335 #define EXT_CFG_PWR_DOWN (1 << 1) 336 #define EXT_GPHY_RESET (1 << 5) 337 338 /* DMA rings size */ 339 #define DMA_RING_SIZE (0x40) 340 #define DMA_RINGS_SIZE (DMA_RING_SIZE * (DESC_INDEX + 1)) 341 342 /* DMA registers common definitions */ 343 #define DMA_RW_POINTER_MASK 0x1FF 344 #define DMA_P_INDEX_DISCARD_CNT_MASK 0xFFFF 345 #define DMA_P_INDEX_DISCARD_CNT_SHIFT 16 346 #define DMA_BUFFER_DONE_CNT_MASK 0xFFFF 347 #define DMA_BUFFER_DONE_CNT_SHIFT 16 348 #define DMA_P_INDEX_MASK 0xFFFF 349 #define DMA_C_INDEX_MASK 0xFFFF 350 351 /* DMA ring size register */ 352 #define DMA_RING_SIZE_MASK 0xFFFF 353 #define DMA_RING_SIZE_SHIFT 16 354 #define DMA_RING_BUFFER_SIZE_MASK 0xFFFF 355 356 /* DMA interrupt threshold register */ 357 #define DMA_INTR_THRESHOLD_MASK 0x00FF 358 359 /* DMA XON/XOFF register */ 360 #define DMA_XON_THREHOLD_MASK 0xFFFF 361 #define DMA_XOFF_THRESHOLD_MASK 0xFFFF 362 #define DMA_XOFF_THRESHOLD_SHIFT 16 363 364 /* DMA flow period register */ 365 #define DMA_FLOW_PERIOD_MASK 0xFFFF 366 #define DMA_MAX_PKT_SIZE_MASK 0xFFFF 367 #define DMA_MAX_PKT_SIZE_SHIFT 16 368 369 370 /* DMA control register */ 371 #define DMA_EN (1 << 0) 372 #define DMA_RING_BUF_EN_SHIFT 0x01 373 #define DMA_RING_BUF_EN_MASK 0xFFFF 374 #define DMA_TSB_SWAP_EN (1 << 20) 375 376 /* DMA status register */ 377 #define DMA_DISABLED (1 << 0) 378 #define DMA_DESC_RAM_INIT_BUSY (1 << 1) 379 380 /* DMA SCB burst size register */ 381 #define DMA_SCB_BURST_SIZE_MASK 0x1F 382 383 /* DMA activity vector register */ 384 #define DMA_ACTIVITY_VECTOR_MASK 0x1FFFF 385 386 /* DMA backpressure mask register */ 387 #define DMA_BACKPRESSURE_MASK 0x1FFFF 388 #define DMA_PFC_ENABLE (1 << 31) 389 390 /* DMA backpressure status register */ 391 #define DMA_BACKPRESSURE_STATUS_MASK 0x1FFFF 392 393 /* DMA override register */ 394 #define DMA_LITTLE_ENDIAN_MODE (1 << 0) 395 #define DMA_REGISTER_MODE (1 << 1) 396 397 /* DMA timeout register */ 398 #define DMA_TIMEOUT_MASK 0xFFFF 399 #define DMA_TIMEOUT_VAL 5000 /* micro seconds */ 400 401 /* TDMA rate limiting control register */ 402 #define DMA_RATE_LIMIT_EN_MASK 0xFFFF 403 404 /* TDMA arbitration control register */ 405 #define DMA_ARBITER_MODE_MASK 0x03 406 #define DMA_RING_BUF_PRIORITY_MASK 0x1F 407 #define DMA_RING_BUF_PRIORITY_SHIFT 5 408 #define DMA_PRIO_REG_INDEX(q) ((q) / 6) 409 #define DMA_PRIO_REG_SHIFT(q) (((q) % 6) * DMA_RING_BUF_PRIORITY_SHIFT) 410 #define DMA_RATE_ADJ_MASK 0xFF 411 412 /* Tx/Rx Dma Descriptor common bits*/ 413 #define DMA_BUFLENGTH_MASK 0x0fff 414 #define DMA_BUFLENGTH_SHIFT 16 415 #define DMA_OWN 0x8000 416 #define DMA_EOP 0x4000 417 #define DMA_SOP 0x2000 418 #define DMA_WRAP 0x1000 419 /* Tx specific Dma descriptor bits */ 420 #define DMA_TX_UNDERRUN 0x0200 421 #define DMA_TX_APPEND_CRC 0x0040 422 #define DMA_TX_OW_CRC 0x0020 423 #define DMA_TX_DO_CSUM 0x0010 424 #define DMA_TX_QTAG_SHIFT 7 425 426 /* Rx Specific Dma descriptor bits */ 427 #define DMA_RX_CHK_V3PLUS 0x8000 428 #define DMA_RX_CHK_V12 0x1000 429 #define DMA_RX_BRDCAST 0x0040 430 #define DMA_RX_MULT 0x0020 431 #define DMA_RX_LG 0x0010 432 #define DMA_RX_NO 0x0008 433 #define DMA_RX_RXER 0x0004 434 #define DMA_RX_CRC_ERROR 0x0002 435 #define DMA_RX_OV 0x0001 436 #define DMA_RX_FI_MASK 0x001F 437 #define DMA_RX_FI_SHIFT 0x0007 438 #define DMA_DESC_ALLOC_MASK 0x00FF 439 440 #define DMA_ARBITER_RR 0x00 441 #define DMA_ARBITER_WRR 0x01 442 #define DMA_ARBITER_SP 0x02 443 444 struct enet_cb { 445 struct sk_buff *skb; 446 void __iomem *bd_addr; 447 DEFINE_DMA_UNMAP_ADDR(dma_addr); 448 DEFINE_DMA_UNMAP_LEN(dma_len); 449 }; 450 451 /* power management mode */ 452 enum bcmgenet_power_mode { 453 GENET_POWER_CABLE_SENSE = 0, 454 GENET_POWER_PASSIVE, 455 GENET_POWER_WOL_MAGIC, 456 }; 457 458 struct bcmgenet_priv; 459 460 /* We support both runtime GENET detection and compile-time 461 * to optimize code-paths for a given hardware 462 */ 463 enum bcmgenet_version { 464 GENET_V1 = 1, 465 GENET_V2, 466 GENET_V3, 467 GENET_V4 468 }; 469 470 #define GENET_IS_V1(p) ((p)->version == GENET_V1) 471 #define GENET_IS_V2(p) ((p)->version == GENET_V2) 472 #define GENET_IS_V3(p) ((p)->version == GENET_V3) 473 #define GENET_IS_V4(p) ((p)->version == GENET_V4) 474 475 /* Hardware flags */ 476 #define GENET_HAS_40BITS (1 << 0) 477 #define GENET_HAS_EXT (1 << 1) 478 #define GENET_HAS_MDIO_INTR (1 << 2) 479 480 /* BCMGENET hardware parameters, keep this structure nicely aligned 481 * since it is going to be used in hot paths 482 */ 483 struct bcmgenet_hw_params { 484 u8 tx_queues; 485 u8 rx_queues; 486 u8 bds_cnt; 487 u8 bp_in_en_shift; 488 u32 bp_in_mask; 489 u8 hfb_filter_cnt; 490 u8 qtag_mask; 491 u16 tbuf_offset; 492 u32 hfb_offset; 493 u32 hfb_reg_offset; 494 u32 rdma_offset; 495 u32 tdma_offset; 496 u32 words_per_bd; 497 u32 flags; 498 }; 499 500 struct bcmgenet_tx_ring { 501 spinlock_t lock; /* ring lock */ 502 struct napi_struct napi; /* NAPI per tx queue */ 503 unsigned int index; /* ring index */ 504 unsigned int queue; /* queue index */ 505 struct enet_cb *cbs; /* tx ring buffer control block*/ 506 unsigned int size; /* size of each tx ring */ 507 unsigned int c_index; /* last consumer index of each ring*/ 508 unsigned int free_bds; /* # of free bds for each ring */ 509 unsigned int write_ptr; /* Tx ring write pointer SW copy */ 510 unsigned int prod_index; /* Tx ring producer index SW copy */ 511 unsigned int cb_ptr; /* Tx ring initial CB ptr */ 512 unsigned int end_ptr; /* Tx ring end CB ptr */ 513 void (*int_enable)(struct bcmgenet_priv *priv, 514 struct bcmgenet_tx_ring *); 515 void (*int_disable)(struct bcmgenet_priv *priv, 516 struct bcmgenet_tx_ring *); 517 struct bcmgenet_priv *priv; 518 }; 519 520 /* device context */ 521 struct bcmgenet_priv { 522 void __iomem *base; 523 enum bcmgenet_version version; 524 struct net_device *dev; 525 u32 int0_mask; 526 u32 int1_mask; 527 528 /* NAPI for descriptor based rx */ 529 struct napi_struct napi ____cacheline_aligned; 530 531 /* transmit variables */ 532 void __iomem *tx_bds; 533 struct enet_cb *tx_cbs; 534 unsigned int num_tx_bds; 535 536 struct bcmgenet_tx_ring tx_rings[DESC_INDEX + 1]; 537 538 /* receive variables */ 539 void __iomem *rx_bds; 540 void __iomem *rx_bd_assign_ptr; 541 int rx_bd_assign_index; 542 struct enet_cb *rx_cbs; 543 unsigned int num_rx_bds; 544 unsigned int rx_buf_len; 545 unsigned int rx_read_ptr; 546 unsigned int rx_c_index; 547 548 /* other misc variables */ 549 struct bcmgenet_hw_params *hw_params; 550 551 /* MDIO bus variables */ 552 wait_queue_head_t wq; 553 struct phy_device *phydev; 554 struct device_node *phy_dn; 555 struct mii_bus *mii_bus; 556 u16 gphy_rev; 557 558 /* PHY device variables */ 559 int old_link; 560 int old_speed; 561 int old_duplex; 562 int old_pause; 563 phy_interface_t phy_interface; 564 int phy_addr; 565 int ext_phy; 566 567 /* Interrupt variables */ 568 struct work_struct bcmgenet_irq_work; 569 int irq0; 570 int irq1; 571 unsigned int irq0_stat; 572 unsigned int irq1_stat; 573 int wol_irq; 574 bool wol_irq_disabled; 575 576 /* HW descriptors/checksum variables */ 577 bool desc_64b_en; 578 bool desc_rxchk_en; 579 bool crc_fwd_en; 580 581 unsigned int dma_rx_chk_bit; 582 583 u32 msg_enable; 584 585 struct clk *clk; 586 struct platform_device *pdev; 587 588 /* WOL */ 589 struct clk *clk_wol; 590 u32 wolopts; 591 592 struct bcmgenet_mib_counters mib; 593 }; 594 595 #define GENET_IO_MACRO(name, offset) \ 596 static inline u32 bcmgenet_##name##_readl(struct bcmgenet_priv *priv, \ 597 u32 off) \ 598 { \ 599 return __raw_readl(priv->base + offset + off); \ 600 } \ 601 static inline void bcmgenet_##name##_writel(struct bcmgenet_priv *priv, \ 602 u32 val, u32 off) \ 603 { \ 604 __raw_writel(val, priv->base + offset + off); \ 605 } 606 607 GENET_IO_MACRO(ext, GENET_EXT_OFF); 608 GENET_IO_MACRO(umac, GENET_UMAC_OFF); 609 GENET_IO_MACRO(sys, GENET_SYS_OFF); 610 611 /* interrupt l2 registers accessors */ 612 GENET_IO_MACRO(intrl2_0, GENET_INTRL2_0_OFF); 613 GENET_IO_MACRO(intrl2_1, GENET_INTRL2_1_OFF); 614 615 /* HFB register accessors */ 616 GENET_IO_MACRO(hfb, priv->hw_params->hfb_offset); 617 618 /* GENET v2+ HFB control and filter len helpers */ 619 GENET_IO_MACRO(hfb_reg, priv->hw_params->hfb_reg_offset); 620 621 /* RBUF register accessors */ 622 GENET_IO_MACRO(rbuf, GENET_RBUF_OFF); 623 624 /* MDIO routines */ 625 int bcmgenet_mii_init(struct net_device *dev); 626 int bcmgenet_mii_config(struct net_device *dev, bool init); 627 void bcmgenet_mii_exit(struct net_device *dev); 628 void bcmgenet_mii_reset(struct net_device *dev); 629 void bcmgenet_mii_setup(struct net_device *dev); 630 631 /* Wake-on-LAN routines */ 632 void bcmgenet_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol); 633 int bcmgenet_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol); 634 int bcmgenet_wol_power_down_cfg(struct bcmgenet_priv *priv, 635 enum bcmgenet_power_mode mode); 636 void bcmgenet_wol_power_up_cfg(struct bcmgenet_priv *priv, 637 enum bcmgenet_power_mode mode); 638 639 #endif /* __BCMGENET_H__ */ 640