1 /*
2 * linux/drivers/net/ethernet/ethoc.c
3 *
4 * Copyright (C) 2007-2008 Avionic Design Development GmbH
5 * Copyright (C) 2008-2009 Avionic Design GmbH
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * Written by Thierry Reding <thierry.reding@avionic-design.de>
12 */
13
14 #include <linux/dma-mapping.h>
15 #include <linux/etherdevice.h>
16 #include <linux/clk.h>
17 #include <linux/crc32.h>
18 #include <linux/interrupt.h>
19 #include <linux/io.h>
20 #include <linux/mii.h>
21 #include <linux/phy.h>
22 #include <linux/platform_device.h>
23 #include <linux/sched.h>
24 #include <linux/slab.h>
25 #include <linux/of.h>
26 #include <linux/module.h>
27 #include <net/ethoc.h>
28
29 static int buffer_size = 0x8000; /* 32 KBytes */
30 module_param(buffer_size, int, 0);
31 MODULE_PARM_DESC(buffer_size, "DMA buffer allocation size");
32
33 /* register offsets */
34 #define MODER 0x00
35 #define INT_SOURCE 0x04
36 #define INT_MASK 0x08
37 #define IPGT 0x0c
38 #define IPGR1 0x10
39 #define IPGR2 0x14
40 #define PACKETLEN 0x18
41 #define COLLCONF 0x1c
42 #define TX_BD_NUM 0x20
43 #define CTRLMODER 0x24
44 #define MIIMODER 0x28
45 #define MIICOMMAND 0x2c
46 #define MIIADDRESS 0x30
47 #define MIITX_DATA 0x34
48 #define MIIRX_DATA 0x38
49 #define MIISTATUS 0x3c
50 #define MAC_ADDR0 0x40
51 #define MAC_ADDR1 0x44
52 #define ETH_HASH0 0x48
53 #define ETH_HASH1 0x4c
54 #define ETH_TXCTRL 0x50
55 #define ETH_END 0x54
56
57 /* mode register */
58 #define MODER_RXEN (1 << 0) /* receive enable */
59 #define MODER_TXEN (1 << 1) /* transmit enable */
60 #define MODER_NOPRE (1 << 2) /* no preamble */
61 #define MODER_BRO (1 << 3) /* broadcast address */
62 #define MODER_IAM (1 << 4) /* individual address mode */
63 #define MODER_PRO (1 << 5) /* promiscuous mode */
64 #define MODER_IFG (1 << 6) /* interframe gap for incoming frames */
65 #define MODER_LOOP (1 << 7) /* loopback */
66 #define MODER_NBO (1 << 8) /* no back-off */
67 #define MODER_EDE (1 << 9) /* excess defer enable */
68 #define MODER_FULLD (1 << 10) /* full duplex */
69 #define MODER_RESET (1 << 11) /* FIXME: reset (undocumented) */
70 #define MODER_DCRC (1 << 12) /* delayed CRC enable */
71 #define MODER_CRC (1 << 13) /* CRC enable */
72 #define MODER_HUGE (1 << 14) /* huge packets enable */
73 #define MODER_PAD (1 << 15) /* padding enabled */
74 #define MODER_RSM (1 << 16) /* receive small packets */
75
76 /* interrupt source and mask registers */
77 #define INT_MASK_TXF (1 << 0) /* transmit frame */
78 #define INT_MASK_TXE (1 << 1) /* transmit error */
79 #define INT_MASK_RXF (1 << 2) /* receive frame */
80 #define INT_MASK_RXE (1 << 3) /* receive error */
81 #define INT_MASK_BUSY (1 << 4)
82 #define INT_MASK_TXC (1 << 5) /* transmit control frame */
83 #define INT_MASK_RXC (1 << 6) /* receive control frame */
84
85 #define INT_MASK_TX (INT_MASK_TXF | INT_MASK_TXE)
86 #define INT_MASK_RX (INT_MASK_RXF | INT_MASK_RXE)
87
88 #define INT_MASK_ALL ( \
89 INT_MASK_TXF | INT_MASK_TXE | \
90 INT_MASK_RXF | INT_MASK_RXE | \
91 INT_MASK_TXC | INT_MASK_RXC | \
92 INT_MASK_BUSY \
93 )
94
95 /* packet length register */
96 #define PACKETLEN_MIN(min) (((min) & 0xffff) << 16)
97 #define PACKETLEN_MAX(max) (((max) & 0xffff) << 0)
98 #define PACKETLEN_MIN_MAX(min, max) (PACKETLEN_MIN(min) | \
99 PACKETLEN_MAX(max))
100
101 /* transmit buffer number register */
102 #define TX_BD_NUM_VAL(x) (((x) <= 0x80) ? (x) : 0x80)
103
104 /* control module mode register */
105 #define CTRLMODER_PASSALL (1 << 0) /* pass all receive frames */
106 #define CTRLMODER_RXFLOW (1 << 1) /* receive control flow */
107 #define CTRLMODER_TXFLOW (1 << 2) /* transmit control flow */
108
109 /* MII mode register */
110 #define MIIMODER_CLKDIV(x) ((x) & 0xfe) /* needs to be an even number */
111 #define MIIMODER_NOPRE (1 << 8) /* no preamble */
112
113 /* MII command register */
114 #define MIICOMMAND_SCAN (1 << 0) /* scan status */
115 #define MIICOMMAND_READ (1 << 1) /* read status */
116 #define MIICOMMAND_WRITE (1 << 2) /* write control data */
117
118 /* MII address register */
119 #define MIIADDRESS_FIAD(x) (((x) & 0x1f) << 0)
120 #define MIIADDRESS_RGAD(x) (((x) & 0x1f) << 8)
121 #define MIIADDRESS_ADDR(phy, reg) (MIIADDRESS_FIAD(phy) | \
122 MIIADDRESS_RGAD(reg))
123
124 /* MII transmit data register */
125 #define MIITX_DATA_VAL(x) ((x) & 0xffff)
126
127 /* MII receive data register */
128 #define MIIRX_DATA_VAL(x) ((x) & 0xffff)
129
130 /* MII status register */
131 #define MIISTATUS_LINKFAIL (1 << 0)
132 #define MIISTATUS_BUSY (1 << 1)
133 #define MIISTATUS_INVALID (1 << 2)
134
135 /* TX buffer descriptor */
136 #define TX_BD_CS (1 << 0) /* carrier sense lost */
137 #define TX_BD_DF (1 << 1) /* defer indication */
138 #define TX_BD_LC (1 << 2) /* late collision */
139 #define TX_BD_RL (1 << 3) /* retransmission limit */
140 #define TX_BD_RETRY_MASK (0x00f0)
141 #define TX_BD_RETRY(x) (((x) & 0x00f0) >> 4)
142 #define TX_BD_UR (1 << 8) /* transmitter underrun */
143 #define TX_BD_CRC (1 << 11) /* TX CRC enable */
144 #define TX_BD_PAD (1 << 12) /* pad enable for short packets */
145 #define TX_BD_WRAP (1 << 13)
146 #define TX_BD_IRQ (1 << 14) /* interrupt request enable */
147 #define TX_BD_READY (1 << 15) /* TX buffer ready */
148 #define TX_BD_LEN(x) (((x) & 0xffff) << 16)
149 #define TX_BD_LEN_MASK (0xffff << 16)
150
151 #define TX_BD_STATS (TX_BD_CS | TX_BD_DF | TX_BD_LC | \
152 TX_BD_RL | TX_BD_RETRY_MASK | TX_BD_UR)
153
154 /* RX buffer descriptor */
155 #define RX_BD_LC (1 << 0) /* late collision */
156 #define RX_BD_CRC (1 << 1) /* RX CRC error */
157 #define RX_BD_SF (1 << 2) /* short frame */
158 #define RX_BD_TL (1 << 3) /* too long */
159 #define RX_BD_DN (1 << 4) /* dribble nibble */
160 #define RX_BD_IS (1 << 5) /* invalid symbol */
161 #define RX_BD_OR (1 << 6) /* receiver overrun */
162 #define RX_BD_MISS (1 << 7)
163 #define RX_BD_CF (1 << 8) /* control frame */
164 #define RX_BD_WRAP (1 << 13)
165 #define RX_BD_IRQ (1 << 14) /* interrupt request enable */
166 #define RX_BD_EMPTY (1 << 15)
167 #define RX_BD_LEN(x) (((x) & 0xffff) << 16)
168
169 #define RX_BD_STATS (RX_BD_LC | RX_BD_CRC | RX_BD_SF | RX_BD_TL | \
170 RX_BD_DN | RX_BD_IS | RX_BD_OR | RX_BD_MISS)
171
172 #define ETHOC_BUFSIZ 1536
173 #define ETHOC_ZLEN 64
174 #define ETHOC_BD_BASE 0x400
175 #define ETHOC_TIMEOUT (HZ / 2)
176 #define ETHOC_MII_TIMEOUT (1 + (HZ / 5))
177
178 /**
179 * struct ethoc - driver-private device structure
180 * @iobase: pointer to I/O memory region
181 * @membase: pointer to buffer memory region
182 * @dma_alloc: dma allocated buffer size
183 * @io_region_size: I/O memory region size
184 * @num_bd: number of buffer descriptors
185 * @num_tx: number of send buffers
186 * @cur_tx: last send buffer written
187 * @dty_tx: last buffer actually sent
188 * @num_rx: number of receive buffers
189 * @cur_rx: current receive buffer
190 * @vma: pointer to array of virtual memory addresses for buffers
191 * @netdev: pointer to network device structure
192 * @napi: NAPI structure
193 * @msg_enable: device state flags
194 * @lock: device lock
195 * @phy: attached PHY
196 * @mdio: MDIO bus for PHY access
197 * @phy_id: address of attached PHY
198 */
199 struct ethoc {
200 void __iomem *iobase;
201 void __iomem *membase;
202 int dma_alloc;
203 resource_size_t io_region_size;
204
205 unsigned int num_bd;
206 unsigned int num_tx;
207 unsigned int cur_tx;
208 unsigned int dty_tx;
209
210 unsigned int num_rx;
211 unsigned int cur_rx;
212
213 void **vma;
214
215 struct net_device *netdev;
216 struct napi_struct napi;
217 u32 msg_enable;
218
219 spinlock_t lock;
220
221 struct phy_device *phy;
222 struct mii_bus *mdio;
223 struct clk *clk;
224 s8 phy_id;
225 };
226
227 /**
228 * struct ethoc_bd - buffer descriptor
229 * @stat: buffer statistics
230 * @addr: physical memory address
231 */
232 struct ethoc_bd {
233 u32 stat;
234 u32 addr;
235 };
236
ethoc_read(struct ethoc * dev,loff_t offset)237 static inline u32 ethoc_read(struct ethoc *dev, loff_t offset)
238 {
239 return ioread32(dev->iobase + offset);
240 }
241
ethoc_write(struct ethoc * dev,loff_t offset,u32 data)242 static inline void ethoc_write(struct ethoc *dev, loff_t offset, u32 data)
243 {
244 iowrite32(data, dev->iobase + offset);
245 }
246
ethoc_read_bd(struct ethoc * dev,int index,struct ethoc_bd * bd)247 static inline void ethoc_read_bd(struct ethoc *dev, int index,
248 struct ethoc_bd *bd)
249 {
250 loff_t offset = ETHOC_BD_BASE + (index * sizeof(struct ethoc_bd));
251 bd->stat = ethoc_read(dev, offset + 0);
252 bd->addr = ethoc_read(dev, offset + 4);
253 }
254
ethoc_write_bd(struct ethoc * dev,int index,const struct ethoc_bd * bd)255 static inline void ethoc_write_bd(struct ethoc *dev, int index,
256 const struct ethoc_bd *bd)
257 {
258 loff_t offset = ETHOC_BD_BASE + (index * sizeof(struct ethoc_bd));
259 ethoc_write(dev, offset + 0, bd->stat);
260 ethoc_write(dev, offset + 4, bd->addr);
261 }
262
ethoc_enable_irq(struct ethoc * dev,u32 mask)263 static inline void ethoc_enable_irq(struct ethoc *dev, u32 mask)
264 {
265 u32 imask = ethoc_read(dev, INT_MASK);
266 imask |= mask;
267 ethoc_write(dev, INT_MASK, imask);
268 }
269
ethoc_disable_irq(struct ethoc * dev,u32 mask)270 static inline void ethoc_disable_irq(struct ethoc *dev, u32 mask)
271 {
272 u32 imask = ethoc_read(dev, INT_MASK);
273 imask &= ~mask;
274 ethoc_write(dev, INT_MASK, imask);
275 }
276
ethoc_ack_irq(struct ethoc * dev,u32 mask)277 static inline void ethoc_ack_irq(struct ethoc *dev, u32 mask)
278 {
279 ethoc_write(dev, INT_SOURCE, mask);
280 }
281
ethoc_enable_rx_and_tx(struct ethoc * dev)282 static inline void ethoc_enable_rx_and_tx(struct ethoc *dev)
283 {
284 u32 mode = ethoc_read(dev, MODER);
285 mode |= MODER_RXEN | MODER_TXEN;
286 ethoc_write(dev, MODER, mode);
287 }
288
ethoc_disable_rx_and_tx(struct ethoc * dev)289 static inline void ethoc_disable_rx_and_tx(struct ethoc *dev)
290 {
291 u32 mode = ethoc_read(dev, MODER);
292 mode &= ~(MODER_RXEN | MODER_TXEN);
293 ethoc_write(dev, MODER, mode);
294 }
295
ethoc_init_ring(struct ethoc * dev,unsigned long mem_start)296 static int ethoc_init_ring(struct ethoc *dev, unsigned long mem_start)
297 {
298 struct ethoc_bd bd;
299 int i;
300 void *vma;
301
302 dev->cur_tx = 0;
303 dev->dty_tx = 0;
304 dev->cur_rx = 0;
305
306 ethoc_write(dev, TX_BD_NUM, dev->num_tx);
307
308 /* setup transmission buffers */
309 bd.addr = mem_start;
310 bd.stat = TX_BD_IRQ | TX_BD_CRC;
311 vma = dev->membase;
312
313 for (i = 0; i < dev->num_tx; i++) {
314 if (i == dev->num_tx - 1)
315 bd.stat |= TX_BD_WRAP;
316
317 ethoc_write_bd(dev, i, &bd);
318 bd.addr += ETHOC_BUFSIZ;
319
320 dev->vma[i] = vma;
321 vma += ETHOC_BUFSIZ;
322 }
323
324 bd.stat = RX_BD_EMPTY | RX_BD_IRQ;
325
326 for (i = 0; i < dev->num_rx; i++) {
327 if (i == dev->num_rx - 1)
328 bd.stat |= RX_BD_WRAP;
329
330 ethoc_write_bd(dev, dev->num_tx + i, &bd);
331 bd.addr += ETHOC_BUFSIZ;
332
333 dev->vma[dev->num_tx + i] = vma;
334 vma += ETHOC_BUFSIZ;
335 }
336
337 return 0;
338 }
339
ethoc_reset(struct ethoc * dev)340 static int ethoc_reset(struct ethoc *dev)
341 {
342 u32 mode;
343
344 /* TODO: reset controller? */
345
346 ethoc_disable_rx_and_tx(dev);
347
348 /* TODO: setup registers */
349
350 /* enable FCS generation and automatic padding */
351 mode = ethoc_read(dev, MODER);
352 mode |= MODER_CRC | MODER_PAD;
353 ethoc_write(dev, MODER, mode);
354
355 /* set full-duplex mode */
356 mode = ethoc_read(dev, MODER);
357 mode |= MODER_FULLD;
358 ethoc_write(dev, MODER, mode);
359 ethoc_write(dev, IPGT, 0x15);
360
361 ethoc_ack_irq(dev, INT_MASK_ALL);
362 ethoc_enable_irq(dev, INT_MASK_ALL);
363 ethoc_enable_rx_and_tx(dev);
364 return 0;
365 }
366
ethoc_update_rx_stats(struct ethoc * dev,struct ethoc_bd * bd)367 static unsigned int ethoc_update_rx_stats(struct ethoc *dev,
368 struct ethoc_bd *bd)
369 {
370 struct net_device *netdev = dev->netdev;
371 unsigned int ret = 0;
372
373 if (bd->stat & RX_BD_TL) {
374 dev_err(&netdev->dev, "RX: frame too long\n");
375 netdev->stats.rx_length_errors++;
376 ret++;
377 }
378
379 if (bd->stat & RX_BD_SF) {
380 dev_err(&netdev->dev, "RX: frame too short\n");
381 netdev->stats.rx_length_errors++;
382 ret++;
383 }
384
385 if (bd->stat & RX_BD_DN) {
386 dev_err(&netdev->dev, "RX: dribble nibble\n");
387 netdev->stats.rx_frame_errors++;
388 }
389
390 if (bd->stat & RX_BD_CRC) {
391 dev_err(&netdev->dev, "RX: wrong CRC\n");
392 netdev->stats.rx_crc_errors++;
393 ret++;
394 }
395
396 if (bd->stat & RX_BD_OR) {
397 dev_err(&netdev->dev, "RX: overrun\n");
398 netdev->stats.rx_over_errors++;
399 ret++;
400 }
401
402 if (bd->stat & RX_BD_MISS)
403 netdev->stats.rx_missed_errors++;
404
405 if (bd->stat & RX_BD_LC) {
406 dev_err(&netdev->dev, "RX: late collision\n");
407 netdev->stats.collisions++;
408 ret++;
409 }
410
411 return ret;
412 }
413
ethoc_rx(struct net_device * dev,int limit)414 static int ethoc_rx(struct net_device *dev, int limit)
415 {
416 struct ethoc *priv = netdev_priv(dev);
417 int count;
418
419 for (count = 0; count < limit; ++count) {
420 unsigned int entry;
421 struct ethoc_bd bd;
422
423 entry = priv->num_tx + priv->cur_rx;
424 ethoc_read_bd(priv, entry, &bd);
425 if (bd.stat & RX_BD_EMPTY) {
426 ethoc_ack_irq(priv, INT_MASK_RX);
427 /* If packet (interrupt) came in between checking
428 * BD_EMTPY and clearing the interrupt source, then we
429 * risk missing the packet as the RX interrupt won't
430 * trigger right away when we reenable it; hence, check
431 * BD_EMTPY here again to make sure there isn't such a
432 * packet waiting for us...
433 */
434 ethoc_read_bd(priv, entry, &bd);
435 if (bd.stat & RX_BD_EMPTY)
436 break;
437 }
438
439 if (ethoc_update_rx_stats(priv, &bd) == 0) {
440 int size = bd.stat >> 16;
441 struct sk_buff *skb;
442
443 size -= 4; /* strip the CRC */
444 skb = netdev_alloc_skb_ip_align(dev, size);
445
446 if (likely(skb)) {
447 void *src = priv->vma[entry];
448 memcpy_fromio(skb_put(skb, size), src, size);
449 skb->protocol = eth_type_trans(skb, dev);
450 dev->stats.rx_packets++;
451 dev->stats.rx_bytes += size;
452 netif_receive_skb(skb);
453 } else {
454 if (net_ratelimit())
455 dev_warn(&dev->dev,
456 "low on memory - packet dropped\n");
457
458 dev->stats.rx_dropped++;
459 break;
460 }
461 }
462
463 /* clear the buffer descriptor so it can be reused */
464 bd.stat &= ~RX_BD_STATS;
465 bd.stat |= RX_BD_EMPTY;
466 ethoc_write_bd(priv, entry, &bd);
467 if (++priv->cur_rx == priv->num_rx)
468 priv->cur_rx = 0;
469 }
470
471 return count;
472 }
473
ethoc_update_tx_stats(struct ethoc * dev,struct ethoc_bd * bd)474 static void ethoc_update_tx_stats(struct ethoc *dev, struct ethoc_bd *bd)
475 {
476 struct net_device *netdev = dev->netdev;
477
478 if (bd->stat & TX_BD_LC) {
479 dev_err(&netdev->dev, "TX: late collision\n");
480 netdev->stats.tx_window_errors++;
481 }
482
483 if (bd->stat & TX_BD_RL) {
484 dev_err(&netdev->dev, "TX: retransmit limit\n");
485 netdev->stats.tx_aborted_errors++;
486 }
487
488 if (bd->stat & TX_BD_UR) {
489 dev_err(&netdev->dev, "TX: underrun\n");
490 netdev->stats.tx_fifo_errors++;
491 }
492
493 if (bd->stat & TX_BD_CS) {
494 dev_err(&netdev->dev, "TX: carrier sense lost\n");
495 netdev->stats.tx_carrier_errors++;
496 }
497
498 if (bd->stat & TX_BD_STATS)
499 netdev->stats.tx_errors++;
500
501 netdev->stats.collisions += (bd->stat >> 4) & 0xf;
502 netdev->stats.tx_bytes += bd->stat >> 16;
503 netdev->stats.tx_packets++;
504 }
505
ethoc_tx(struct net_device * dev,int limit)506 static int ethoc_tx(struct net_device *dev, int limit)
507 {
508 struct ethoc *priv = netdev_priv(dev);
509 int count;
510 struct ethoc_bd bd;
511
512 for (count = 0; count < limit; ++count) {
513 unsigned int entry;
514
515 entry = priv->dty_tx & (priv->num_tx-1);
516
517 ethoc_read_bd(priv, entry, &bd);
518
519 if (bd.stat & TX_BD_READY || (priv->dty_tx == priv->cur_tx)) {
520 ethoc_ack_irq(priv, INT_MASK_TX);
521 /* If interrupt came in between reading in the BD
522 * and clearing the interrupt source, then we risk
523 * missing the event as the TX interrupt won't trigger
524 * right away when we reenable it; hence, check
525 * BD_EMPTY here again to make sure there isn't such an
526 * event pending...
527 */
528 ethoc_read_bd(priv, entry, &bd);
529 if (bd.stat & TX_BD_READY ||
530 (priv->dty_tx == priv->cur_tx))
531 break;
532 }
533
534 ethoc_update_tx_stats(priv, &bd);
535 priv->dty_tx++;
536 }
537
538 if ((priv->cur_tx - priv->dty_tx) <= (priv->num_tx / 2))
539 netif_wake_queue(dev);
540
541 return count;
542 }
543
ethoc_interrupt(int irq,void * dev_id)544 static irqreturn_t ethoc_interrupt(int irq, void *dev_id)
545 {
546 struct net_device *dev = dev_id;
547 struct ethoc *priv = netdev_priv(dev);
548 u32 pending;
549 u32 mask;
550
551 /* Figure out what triggered the interrupt...
552 * The tricky bit here is that the interrupt source bits get
553 * set in INT_SOURCE for an event regardless of whether that
554 * event is masked or not. Thus, in order to figure out what
555 * triggered the interrupt, we need to remove the sources
556 * for all events that are currently masked. This behaviour
557 * is not particularly well documented but reasonable...
558 */
559 mask = ethoc_read(priv, INT_MASK);
560 pending = ethoc_read(priv, INT_SOURCE);
561 pending &= mask;
562
563 if (unlikely(pending == 0))
564 return IRQ_NONE;
565
566 ethoc_ack_irq(priv, pending);
567
568 /* We always handle the dropped packet interrupt */
569 if (pending & INT_MASK_BUSY) {
570 dev_err(&dev->dev, "packet dropped\n");
571 dev->stats.rx_dropped++;
572 }
573
574 /* Handle receive/transmit event by switching to polling */
575 if (pending & (INT_MASK_TX | INT_MASK_RX)) {
576 ethoc_disable_irq(priv, INT_MASK_TX | INT_MASK_RX);
577 napi_schedule(&priv->napi);
578 }
579
580 return IRQ_HANDLED;
581 }
582
ethoc_get_mac_address(struct net_device * dev,void * addr)583 static int ethoc_get_mac_address(struct net_device *dev, void *addr)
584 {
585 struct ethoc *priv = netdev_priv(dev);
586 u8 *mac = (u8 *)addr;
587 u32 reg;
588
589 reg = ethoc_read(priv, MAC_ADDR0);
590 mac[2] = (reg >> 24) & 0xff;
591 mac[3] = (reg >> 16) & 0xff;
592 mac[4] = (reg >> 8) & 0xff;
593 mac[5] = (reg >> 0) & 0xff;
594
595 reg = ethoc_read(priv, MAC_ADDR1);
596 mac[0] = (reg >> 8) & 0xff;
597 mac[1] = (reg >> 0) & 0xff;
598
599 return 0;
600 }
601
ethoc_poll(struct napi_struct * napi,int budget)602 static int ethoc_poll(struct napi_struct *napi, int budget)
603 {
604 struct ethoc *priv = container_of(napi, struct ethoc, napi);
605 int rx_work_done = 0;
606 int tx_work_done = 0;
607
608 rx_work_done = ethoc_rx(priv->netdev, budget);
609 tx_work_done = ethoc_tx(priv->netdev, budget);
610
611 if (rx_work_done < budget && tx_work_done < budget) {
612 napi_complete(napi);
613 ethoc_enable_irq(priv, INT_MASK_TX | INT_MASK_RX);
614 }
615
616 return rx_work_done;
617 }
618
ethoc_mdio_read(struct mii_bus * bus,int phy,int reg)619 static int ethoc_mdio_read(struct mii_bus *bus, int phy, int reg)
620 {
621 struct ethoc *priv = bus->priv;
622 int i;
623
624 ethoc_write(priv, MIIADDRESS, MIIADDRESS_ADDR(phy, reg));
625 ethoc_write(priv, MIICOMMAND, MIICOMMAND_READ);
626
627 for (i = 0; i < 5; i++) {
628 u32 status = ethoc_read(priv, MIISTATUS);
629 if (!(status & MIISTATUS_BUSY)) {
630 u32 data = ethoc_read(priv, MIIRX_DATA);
631 /* reset MII command register */
632 ethoc_write(priv, MIICOMMAND, 0);
633 return data;
634 }
635 usleep_range(100, 200);
636 }
637
638 return -EBUSY;
639 }
640
ethoc_mdio_write(struct mii_bus * bus,int phy,int reg,u16 val)641 static int ethoc_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val)
642 {
643 struct ethoc *priv = bus->priv;
644 int i;
645
646 ethoc_write(priv, MIIADDRESS, MIIADDRESS_ADDR(phy, reg));
647 ethoc_write(priv, MIITX_DATA, val);
648 ethoc_write(priv, MIICOMMAND, MIICOMMAND_WRITE);
649
650 for (i = 0; i < 5; i++) {
651 u32 stat = ethoc_read(priv, MIISTATUS);
652 if (!(stat & MIISTATUS_BUSY)) {
653 /* reset MII command register */
654 ethoc_write(priv, MIICOMMAND, 0);
655 return 0;
656 }
657 usleep_range(100, 200);
658 }
659
660 return -EBUSY;
661 }
662
ethoc_mdio_poll(struct net_device * dev)663 static void ethoc_mdio_poll(struct net_device *dev)
664 {
665 }
666
ethoc_mdio_probe(struct net_device * dev)667 static int ethoc_mdio_probe(struct net_device *dev)
668 {
669 struct ethoc *priv = netdev_priv(dev);
670 struct phy_device *phy;
671 int err;
672
673 if (priv->phy_id != -1)
674 phy = priv->mdio->phy_map[priv->phy_id];
675 else
676 phy = phy_find_first(priv->mdio);
677
678 if (!phy) {
679 dev_err(&dev->dev, "no PHY found\n");
680 return -ENXIO;
681 }
682
683 err = phy_connect_direct(dev, phy, ethoc_mdio_poll,
684 PHY_INTERFACE_MODE_GMII);
685 if (err) {
686 dev_err(&dev->dev, "could not attach to PHY\n");
687 return err;
688 }
689
690 priv->phy = phy;
691 phy->advertising &= ~(ADVERTISED_1000baseT_Full |
692 ADVERTISED_1000baseT_Half);
693 phy->supported &= ~(SUPPORTED_1000baseT_Full |
694 SUPPORTED_1000baseT_Half);
695
696 return 0;
697 }
698
ethoc_open(struct net_device * dev)699 static int ethoc_open(struct net_device *dev)
700 {
701 struct ethoc *priv = netdev_priv(dev);
702 int ret;
703
704 ret = request_irq(dev->irq, ethoc_interrupt, IRQF_SHARED,
705 dev->name, dev);
706 if (ret)
707 return ret;
708
709 napi_enable(&priv->napi);
710
711 ethoc_init_ring(priv, dev->mem_start);
712 ethoc_reset(priv);
713
714 if (netif_queue_stopped(dev)) {
715 dev_dbg(&dev->dev, " resuming queue\n");
716 netif_wake_queue(dev);
717 } else {
718 dev_dbg(&dev->dev, " starting queue\n");
719 netif_start_queue(dev);
720 }
721
722 phy_start(priv->phy);
723
724 if (netif_msg_ifup(priv)) {
725 dev_info(&dev->dev, "I/O: %08lx Memory: %08lx-%08lx\n",
726 dev->base_addr, dev->mem_start, dev->mem_end);
727 }
728
729 return 0;
730 }
731
ethoc_stop(struct net_device * dev)732 static int ethoc_stop(struct net_device *dev)
733 {
734 struct ethoc *priv = netdev_priv(dev);
735
736 napi_disable(&priv->napi);
737
738 if (priv->phy)
739 phy_stop(priv->phy);
740
741 ethoc_disable_rx_and_tx(priv);
742 free_irq(dev->irq, dev);
743
744 if (!netif_queue_stopped(dev))
745 netif_stop_queue(dev);
746
747 return 0;
748 }
749
ethoc_ioctl(struct net_device * dev,struct ifreq * ifr,int cmd)750 static int ethoc_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
751 {
752 struct ethoc *priv = netdev_priv(dev);
753 struct mii_ioctl_data *mdio = if_mii(ifr);
754 struct phy_device *phy = NULL;
755
756 if (!netif_running(dev))
757 return -EINVAL;
758
759 if (cmd != SIOCGMIIPHY) {
760 if (mdio->phy_id >= PHY_MAX_ADDR)
761 return -ERANGE;
762
763 phy = priv->mdio->phy_map[mdio->phy_id];
764 if (!phy)
765 return -ENODEV;
766 } else {
767 phy = priv->phy;
768 }
769
770 return phy_mii_ioctl(phy, ifr, cmd);
771 }
772
ethoc_do_set_mac_address(struct net_device * dev)773 static void ethoc_do_set_mac_address(struct net_device *dev)
774 {
775 struct ethoc *priv = netdev_priv(dev);
776 unsigned char *mac = dev->dev_addr;
777
778 ethoc_write(priv, MAC_ADDR0, (mac[2] << 24) | (mac[3] << 16) |
779 (mac[4] << 8) | (mac[5] << 0));
780 ethoc_write(priv, MAC_ADDR1, (mac[0] << 8) | (mac[1] << 0));
781 }
782
ethoc_set_mac_address(struct net_device * dev,void * p)783 static int ethoc_set_mac_address(struct net_device *dev, void *p)
784 {
785 const struct sockaddr *addr = p;
786
787 if (!is_valid_ether_addr(addr->sa_data))
788 return -EADDRNOTAVAIL;
789 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
790 ethoc_do_set_mac_address(dev);
791 return 0;
792 }
793
ethoc_set_multicast_list(struct net_device * dev)794 static void ethoc_set_multicast_list(struct net_device *dev)
795 {
796 struct ethoc *priv = netdev_priv(dev);
797 u32 mode = ethoc_read(priv, MODER);
798 struct netdev_hw_addr *ha;
799 u32 hash[2] = { 0, 0 };
800
801 /* set loopback mode if requested */
802 if (dev->flags & IFF_LOOPBACK)
803 mode |= MODER_LOOP;
804 else
805 mode &= ~MODER_LOOP;
806
807 /* receive broadcast frames if requested */
808 if (dev->flags & IFF_BROADCAST)
809 mode &= ~MODER_BRO;
810 else
811 mode |= MODER_BRO;
812
813 /* enable promiscuous mode if requested */
814 if (dev->flags & IFF_PROMISC)
815 mode |= MODER_PRO;
816 else
817 mode &= ~MODER_PRO;
818
819 ethoc_write(priv, MODER, mode);
820
821 /* receive multicast frames */
822 if (dev->flags & IFF_ALLMULTI) {
823 hash[0] = 0xffffffff;
824 hash[1] = 0xffffffff;
825 } else {
826 netdev_for_each_mc_addr(ha, dev) {
827 u32 crc = ether_crc(ETH_ALEN, ha->addr);
828 int bit = (crc >> 26) & 0x3f;
829 hash[bit >> 5] |= 1 << (bit & 0x1f);
830 }
831 }
832
833 ethoc_write(priv, ETH_HASH0, hash[0]);
834 ethoc_write(priv, ETH_HASH1, hash[1]);
835 }
836
ethoc_change_mtu(struct net_device * dev,int new_mtu)837 static int ethoc_change_mtu(struct net_device *dev, int new_mtu)
838 {
839 return -ENOSYS;
840 }
841
ethoc_tx_timeout(struct net_device * dev)842 static void ethoc_tx_timeout(struct net_device *dev)
843 {
844 struct ethoc *priv = netdev_priv(dev);
845 u32 pending = ethoc_read(priv, INT_SOURCE);
846 if (likely(pending))
847 ethoc_interrupt(dev->irq, dev);
848 }
849
ethoc_start_xmit(struct sk_buff * skb,struct net_device * dev)850 static netdev_tx_t ethoc_start_xmit(struct sk_buff *skb, struct net_device *dev)
851 {
852 struct ethoc *priv = netdev_priv(dev);
853 struct ethoc_bd bd;
854 unsigned int entry;
855 void *dest;
856
857 if (unlikely(skb->len > ETHOC_BUFSIZ)) {
858 dev->stats.tx_errors++;
859 goto out;
860 }
861
862 entry = priv->cur_tx % priv->num_tx;
863 spin_lock_irq(&priv->lock);
864 priv->cur_tx++;
865
866 ethoc_read_bd(priv, entry, &bd);
867 if (unlikely(skb->len < ETHOC_ZLEN))
868 bd.stat |= TX_BD_PAD;
869 else
870 bd.stat &= ~TX_BD_PAD;
871
872 dest = priv->vma[entry];
873 memcpy_toio(dest, skb->data, skb->len);
874
875 bd.stat &= ~(TX_BD_STATS | TX_BD_LEN_MASK);
876 bd.stat |= TX_BD_LEN(skb->len);
877 ethoc_write_bd(priv, entry, &bd);
878
879 bd.stat |= TX_BD_READY;
880 ethoc_write_bd(priv, entry, &bd);
881
882 if (priv->cur_tx == (priv->dty_tx + priv->num_tx)) {
883 dev_dbg(&dev->dev, "stopping queue\n");
884 netif_stop_queue(dev);
885 }
886
887 spin_unlock_irq(&priv->lock);
888 skb_tx_timestamp(skb);
889 out:
890 dev_kfree_skb(skb);
891 return NETDEV_TX_OK;
892 }
893
ethoc_get_settings(struct net_device * dev,struct ethtool_cmd * cmd)894 static int ethoc_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
895 {
896 struct ethoc *priv = netdev_priv(dev);
897 struct phy_device *phydev = priv->phy;
898
899 if (!phydev)
900 return -EOPNOTSUPP;
901
902 return phy_ethtool_gset(phydev, cmd);
903 }
904
ethoc_set_settings(struct net_device * dev,struct ethtool_cmd * cmd)905 static int ethoc_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
906 {
907 struct ethoc *priv = netdev_priv(dev);
908 struct phy_device *phydev = priv->phy;
909
910 if (!phydev)
911 return -EOPNOTSUPP;
912
913 return phy_ethtool_sset(phydev, cmd);
914 }
915
ethoc_get_regs_len(struct net_device * netdev)916 static int ethoc_get_regs_len(struct net_device *netdev)
917 {
918 return ETH_END;
919 }
920
ethoc_get_regs(struct net_device * dev,struct ethtool_regs * regs,void * p)921 static void ethoc_get_regs(struct net_device *dev, struct ethtool_regs *regs,
922 void *p)
923 {
924 struct ethoc *priv = netdev_priv(dev);
925 u32 *regs_buff = p;
926 unsigned i;
927
928 regs->version = 0;
929 for (i = 0; i < ETH_END / sizeof(u32); ++i)
930 regs_buff[i] = ethoc_read(priv, i * sizeof(u32));
931 }
932
ethoc_get_ringparam(struct net_device * dev,struct ethtool_ringparam * ring)933 static void ethoc_get_ringparam(struct net_device *dev,
934 struct ethtool_ringparam *ring)
935 {
936 struct ethoc *priv = netdev_priv(dev);
937
938 ring->rx_max_pending = priv->num_bd - 1;
939 ring->rx_mini_max_pending = 0;
940 ring->rx_jumbo_max_pending = 0;
941 ring->tx_max_pending = priv->num_bd - 1;
942
943 ring->rx_pending = priv->num_rx;
944 ring->rx_mini_pending = 0;
945 ring->rx_jumbo_pending = 0;
946 ring->tx_pending = priv->num_tx;
947 }
948
ethoc_set_ringparam(struct net_device * dev,struct ethtool_ringparam * ring)949 static int ethoc_set_ringparam(struct net_device *dev,
950 struct ethtool_ringparam *ring)
951 {
952 struct ethoc *priv = netdev_priv(dev);
953
954 if (ring->tx_pending < 1 || ring->rx_pending < 1 ||
955 ring->tx_pending + ring->rx_pending > priv->num_bd)
956 return -EINVAL;
957 if (ring->rx_mini_pending || ring->rx_jumbo_pending)
958 return -EINVAL;
959
960 if (netif_running(dev)) {
961 netif_tx_disable(dev);
962 ethoc_disable_rx_and_tx(priv);
963 ethoc_disable_irq(priv, INT_MASK_TX | INT_MASK_RX);
964 synchronize_irq(dev->irq);
965 }
966
967 priv->num_tx = rounddown_pow_of_two(ring->tx_pending);
968 priv->num_rx = ring->rx_pending;
969 ethoc_init_ring(priv, dev->mem_start);
970
971 if (netif_running(dev)) {
972 ethoc_enable_irq(priv, INT_MASK_TX | INT_MASK_RX);
973 ethoc_enable_rx_and_tx(priv);
974 netif_wake_queue(dev);
975 }
976 return 0;
977 }
978
979 const struct ethtool_ops ethoc_ethtool_ops = {
980 .get_settings = ethoc_get_settings,
981 .set_settings = ethoc_set_settings,
982 .get_regs_len = ethoc_get_regs_len,
983 .get_regs = ethoc_get_regs,
984 .get_link = ethtool_op_get_link,
985 .get_ringparam = ethoc_get_ringparam,
986 .set_ringparam = ethoc_set_ringparam,
987 .get_ts_info = ethtool_op_get_ts_info,
988 };
989
990 static const struct net_device_ops ethoc_netdev_ops = {
991 .ndo_open = ethoc_open,
992 .ndo_stop = ethoc_stop,
993 .ndo_do_ioctl = ethoc_ioctl,
994 .ndo_set_mac_address = ethoc_set_mac_address,
995 .ndo_set_rx_mode = ethoc_set_multicast_list,
996 .ndo_change_mtu = ethoc_change_mtu,
997 .ndo_tx_timeout = ethoc_tx_timeout,
998 .ndo_start_xmit = ethoc_start_xmit,
999 };
1000
1001 /**
1002 * ethoc_probe - initialize OpenCores ethernet MAC
1003 * pdev: platform device
1004 */
ethoc_probe(struct platform_device * pdev)1005 static int ethoc_probe(struct platform_device *pdev)
1006 {
1007 struct net_device *netdev = NULL;
1008 struct resource *res = NULL;
1009 struct resource *mmio = NULL;
1010 struct resource *mem = NULL;
1011 struct ethoc *priv = NULL;
1012 unsigned int phy;
1013 int num_bd;
1014 int ret = 0;
1015 bool random_mac = false;
1016 struct ethoc_platform_data *pdata = dev_get_platdata(&pdev->dev);
1017 u32 eth_clkfreq = pdata ? pdata->eth_clkfreq : 0;
1018
1019 /* allocate networking device */
1020 netdev = alloc_etherdev(sizeof(struct ethoc));
1021 if (!netdev) {
1022 ret = -ENOMEM;
1023 goto out;
1024 }
1025
1026 SET_NETDEV_DEV(netdev, &pdev->dev);
1027 platform_set_drvdata(pdev, netdev);
1028
1029 /* obtain I/O memory space */
1030 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1031 if (!res) {
1032 dev_err(&pdev->dev, "cannot obtain I/O memory space\n");
1033 ret = -ENXIO;
1034 goto free;
1035 }
1036
1037 mmio = devm_request_mem_region(&pdev->dev, res->start,
1038 resource_size(res), res->name);
1039 if (!mmio) {
1040 dev_err(&pdev->dev, "cannot request I/O memory space\n");
1041 ret = -ENXIO;
1042 goto free;
1043 }
1044
1045 netdev->base_addr = mmio->start;
1046
1047 /* obtain buffer memory space */
1048 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1049 if (res) {
1050 mem = devm_request_mem_region(&pdev->dev, res->start,
1051 resource_size(res), res->name);
1052 if (!mem) {
1053 dev_err(&pdev->dev, "cannot request memory space\n");
1054 ret = -ENXIO;
1055 goto free;
1056 }
1057
1058 netdev->mem_start = mem->start;
1059 netdev->mem_end = mem->end;
1060 }
1061
1062
1063 /* obtain device IRQ number */
1064 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1065 if (!res) {
1066 dev_err(&pdev->dev, "cannot obtain IRQ\n");
1067 ret = -ENXIO;
1068 goto free;
1069 }
1070
1071 netdev->irq = res->start;
1072
1073 /* setup driver-private data */
1074 priv = netdev_priv(netdev);
1075 priv->netdev = netdev;
1076 priv->dma_alloc = 0;
1077 priv->io_region_size = resource_size(mmio);
1078
1079 priv->iobase = devm_ioremap_nocache(&pdev->dev, netdev->base_addr,
1080 resource_size(mmio));
1081 if (!priv->iobase) {
1082 dev_err(&pdev->dev, "cannot remap I/O memory space\n");
1083 ret = -ENXIO;
1084 goto error;
1085 }
1086
1087 if (netdev->mem_end) {
1088 priv->membase = devm_ioremap_nocache(&pdev->dev,
1089 netdev->mem_start, resource_size(mem));
1090 if (!priv->membase) {
1091 dev_err(&pdev->dev, "cannot remap memory space\n");
1092 ret = -ENXIO;
1093 goto error;
1094 }
1095 } else {
1096 /* Allocate buffer memory */
1097 priv->membase = dmam_alloc_coherent(&pdev->dev,
1098 buffer_size, (void *)&netdev->mem_start,
1099 GFP_KERNEL);
1100 if (!priv->membase) {
1101 dev_err(&pdev->dev, "cannot allocate %dB buffer\n",
1102 buffer_size);
1103 ret = -ENOMEM;
1104 goto error;
1105 }
1106 netdev->mem_end = netdev->mem_start + buffer_size;
1107 priv->dma_alloc = buffer_size;
1108 }
1109
1110 /* calculate the number of TX/RX buffers, maximum 128 supported */
1111 num_bd = min_t(unsigned int,
1112 128, (netdev->mem_end - netdev->mem_start + 1) / ETHOC_BUFSIZ);
1113 if (num_bd < 4) {
1114 ret = -ENODEV;
1115 goto error;
1116 }
1117 priv->num_bd = num_bd;
1118 /* num_tx must be a power of two */
1119 priv->num_tx = rounddown_pow_of_two(num_bd >> 1);
1120 priv->num_rx = num_bd - priv->num_tx;
1121
1122 dev_dbg(&pdev->dev, "ethoc: num_tx: %d num_rx: %d\n",
1123 priv->num_tx, priv->num_rx);
1124
1125 priv->vma = devm_kzalloc(&pdev->dev, num_bd*sizeof(void *), GFP_KERNEL);
1126 if (!priv->vma) {
1127 ret = -ENOMEM;
1128 goto error;
1129 }
1130
1131 /* Allow the platform setup code to pass in a MAC address. */
1132 if (pdata) {
1133 memcpy(netdev->dev_addr, pdata->hwaddr, IFHWADDRLEN);
1134 priv->phy_id = pdata->phy_id;
1135 } else {
1136 priv->phy_id = -1;
1137
1138 #ifdef CONFIG_OF
1139 {
1140 const uint8_t *mac;
1141
1142 mac = of_get_property(pdev->dev.of_node,
1143 "local-mac-address",
1144 NULL);
1145 if (mac)
1146 memcpy(netdev->dev_addr, mac, IFHWADDRLEN);
1147 }
1148 #endif
1149 }
1150
1151 /* Check that the given MAC address is valid. If it isn't, read the
1152 * current MAC from the controller.
1153 */
1154 if (!is_valid_ether_addr(netdev->dev_addr))
1155 ethoc_get_mac_address(netdev, netdev->dev_addr);
1156
1157 /* Check the MAC again for validity, if it still isn't choose and
1158 * program a random one.
1159 */
1160 if (!is_valid_ether_addr(netdev->dev_addr)) {
1161 eth_random_addr(netdev->dev_addr);
1162 random_mac = true;
1163 }
1164
1165 ethoc_do_set_mac_address(netdev);
1166
1167 if (random_mac)
1168 netdev->addr_assign_type = NET_ADDR_RANDOM;
1169
1170 /* Allow the platform setup code to adjust MII management bus clock. */
1171 if (!eth_clkfreq) {
1172 struct clk *clk = devm_clk_get(&pdev->dev, NULL);
1173
1174 if (!IS_ERR(clk)) {
1175 priv->clk = clk;
1176 clk_prepare_enable(clk);
1177 eth_clkfreq = clk_get_rate(clk);
1178 }
1179 }
1180 if (eth_clkfreq) {
1181 u32 clkdiv = MIIMODER_CLKDIV(eth_clkfreq / 2500000 + 1);
1182
1183 if (!clkdiv)
1184 clkdiv = 2;
1185 dev_dbg(&pdev->dev, "setting MII clkdiv to %u\n", clkdiv);
1186 ethoc_write(priv, MIIMODER,
1187 (ethoc_read(priv, MIIMODER) & MIIMODER_NOPRE) |
1188 clkdiv);
1189 }
1190
1191 /* register MII bus */
1192 priv->mdio = mdiobus_alloc();
1193 if (!priv->mdio) {
1194 ret = -ENOMEM;
1195 goto free;
1196 }
1197
1198 priv->mdio->name = "ethoc-mdio";
1199 snprintf(priv->mdio->id, MII_BUS_ID_SIZE, "%s-%d",
1200 priv->mdio->name, pdev->id);
1201 priv->mdio->read = ethoc_mdio_read;
1202 priv->mdio->write = ethoc_mdio_write;
1203 priv->mdio->priv = priv;
1204
1205 priv->mdio->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL);
1206 if (!priv->mdio->irq) {
1207 ret = -ENOMEM;
1208 goto free_mdio;
1209 }
1210
1211 for (phy = 0; phy < PHY_MAX_ADDR; phy++)
1212 priv->mdio->irq[phy] = PHY_POLL;
1213
1214 ret = mdiobus_register(priv->mdio);
1215 if (ret) {
1216 dev_err(&netdev->dev, "failed to register MDIO bus\n");
1217 goto free_mdio;
1218 }
1219
1220 ret = ethoc_mdio_probe(netdev);
1221 if (ret) {
1222 dev_err(&netdev->dev, "failed to probe MDIO bus\n");
1223 goto error;
1224 }
1225
1226 /* setup the net_device structure */
1227 netdev->netdev_ops = ðoc_netdev_ops;
1228 netdev->watchdog_timeo = ETHOC_TIMEOUT;
1229 netdev->features |= 0;
1230 netdev->ethtool_ops = ðoc_ethtool_ops;
1231
1232 /* setup NAPI */
1233 netif_napi_add(netdev, &priv->napi, ethoc_poll, 64);
1234
1235 spin_lock_init(&priv->lock);
1236
1237 ret = register_netdev(netdev);
1238 if (ret < 0) {
1239 dev_err(&netdev->dev, "failed to register interface\n");
1240 goto error2;
1241 }
1242
1243 goto out;
1244
1245 error2:
1246 netif_napi_del(&priv->napi);
1247 error:
1248 mdiobus_unregister(priv->mdio);
1249 free_mdio:
1250 kfree(priv->mdio->irq);
1251 mdiobus_free(priv->mdio);
1252 free:
1253 if (priv->clk)
1254 clk_disable_unprepare(priv->clk);
1255 free_netdev(netdev);
1256 out:
1257 return ret;
1258 }
1259
1260 /**
1261 * ethoc_remove - shutdown OpenCores ethernet MAC
1262 * @pdev: platform device
1263 */
ethoc_remove(struct platform_device * pdev)1264 static int ethoc_remove(struct platform_device *pdev)
1265 {
1266 struct net_device *netdev = platform_get_drvdata(pdev);
1267 struct ethoc *priv = netdev_priv(netdev);
1268
1269 if (netdev) {
1270 netif_napi_del(&priv->napi);
1271 phy_disconnect(priv->phy);
1272 priv->phy = NULL;
1273
1274 if (priv->mdio) {
1275 mdiobus_unregister(priv->mdio);
1276 kfree(priv->mdio->irq);
1277 mdiobus_free(priv->mdio);
1278 }
1279 if (priv->clk)
1280 clk_disable_unprepare(priv->clk);
1281 unregister_netdev(netdev);
1282 free_netdev(netdev);
1283 }
1284
1285 return 0;
1286 }
1287
1288 #ifdef CONFIG_PM
ethoc_suspend(struct platform_device * pdev,pm_message_t state)1289 static int ethoc_suspend(struct platform_device *pdev, pm_message_t state)
1290 {
1291 return -ENOSYS;
1292 }
1293
ethoc_resume(struct platform_device * pdev)1294 static int ethoc_resume(struct platform_device *pdev)
1295 {
1296 return -ENOSYS;
1297 }
1298 #else
1299 # define ethoc_suspend NULL
1300 # define ethoc_resume NULL
1301 #endif
1302
1303 static struct of_device_id ethoc_match[] = {
1304 { .compatible = "opencores,ethoc", },
1305 {},
1306 };
1307 MODULE_DEVICE_TABLE(of, ethoc_match);
1308
1309 static struct platform_driver ethoc_driver = {
1310 .probe = ethoc_probe,
1311 .remove = ethoc_remove,
1312 .suspend = ethoc_suspend,
1313 .resume = ethoc_resume,
1314 .driver = {
1315 .name = "ethoc",
1316 .owner = THIS_MODULE,
1317 .of_match_table = ethoc_match,
1318 },
1319 };
1320
1321 module_platform_driver(ethoc_driver);
1322
1323 MODULE_AUTHOR("Thierry Reding <thierry.reding@avionic-design.de>");
1324 MODULE_DESCRIPTION("OpenCores Ethernet MAC driver");
1325 MODULE_LICENSE("GPL v2");
1326
1327