1 /*
2 * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx.
3 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
4 *
5 * Right now, I am very wasteful with the buffers. I allocate memory
6 * pages and then divide them into 2K frame buffers. This way I know I
7 * have buffers large enough to hold one frame within one buffer descriptor.
8 * Once I get this working, I will use 64 or 128 byte CPM buffers, which
9 * will be much more memory efficient and will easily handle lots of
10 * small packets.
11 *
12 * Much better multiple PHY support by Magnus Damm.
13 * Copyright (c) 2000 Ericsson Radio Systems AB.
14 *
15 * Support for FEC controller of ColdFire processors.
16 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com)
17 *
18 * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be)
19 * Copyright (c) 2004-2006 Macq Electronique SA.
20 *
21 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
22 */
23
24 #include <linux/module.h>
25 #include <linux/kernel.h>
26 #include <linux/string.h>
27 #include <linux/ptrace.h>
28 #include <linux/errno.h>
29 #include <linux/ioport.h>
30 #include <linux/slab.h>
31 #include <linux/interrupt.h>
32 #include <linux/delay.h>
33 #include <linux/netdevice.h>
34 #include <linux/etherdevice.h>
35 #include <linux/skbuff.h>
36 #include <linux/in.h>
37 #include <linux/ip.h>
38 #include <net/ip.h>
39 #include <net/tso.h>
40 #include <linux/tcp.h>
41 #include <linux/udp.h>
42 #include <linux/icmp.h>
43 #include <linux/spinlock.h>
44 #include <linux/workqueue.h>
45 #include <linux/bitops.h>
46 #include <linux/io.h>
47 #include <linux/irq.h>
48 #include <linux/clk.h>
49 #include <linux/platform_device.h>
50 #include <linux/phy.h>
51 #include <linux/fec.h>
52 #include <linux/of.h>
53 #include <linux/of_device.h>
54 #include <linux/of_gpio.h>
55 #include <linux/of_mdio.h>
56 #include <linux/of_net.h>
57 #include <linux/regulator/consumer.h>
58 #include <linux/if_vlan.h>
59 #include <linux/pinctrl/consumer.h>
60 #include <linux/prefetch.h>
61
62 #include <asm/cacheflush.h>
63
64 #include "fec.h"
65
66 static void set_multicast_list(struct net_device *ndev);
67 static void fec_enet_itr_coal_init(struct net_device *ndev);
68
69 #define DRIVER_NAME "fec"
70
71 #define FEC_ENET_GET_QUQUE(_x) ((_x == 0) ? 1 : ((_x == 1) ? 2 : 0))
72
73 /* Pause frame feild and FIFO threshold */
74 #define FEC_ENET_FCE (1 << 5)
75 #define FEC_ENET_RSEM_V 0x84
76 #define FEC_ENET_RSFL_V 16
77 #define FEC_ENET_RAEM_V 0x8
78 #define FEC_ENET_RAFL_V 0x8
79 #define FEC_ENET_OPD_V 0xFFF0
80
81 static struct platform_device_id fec_devtype[] = {
82 {
83 /* keep it for coldfire */
84 .name = DRIVER_NAME,
85 .driver_data = 0,
86 }, {
87 .name = "imx25-fec",
88 .driver_data = FEC_QUIRK_USE_GASKET,
89 }, {
90 .name = "imx27-fec",
91 .driver_data = 0,
92 }, {
93 .name = "imx28-fec",
94 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME,
95 }, {
96 .name = "imx6q-fec",
97 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
98 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
99 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR006358,
100 }, {
101 .name = "mvf600-fec",
102 .driver_data = FEC_QUIRK_ENET_MAC,
103 }, {
104 .name = "imx6sx-fec",
105 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
106 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
107 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB |
108 FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE,
109 }, {
110 /* sentinel */
111 }
112 };
113 MODULE_DEVICE_TABLE(platform, fec_devtype);
114
115 enum imx_fec_type {
116 IMX25_FEC = 1, /* runs on i.mx25/50/53 */
117 IMX27_FEC, /* runs on i.mx27/35/51 */
118 IMX28_FEC,
119 IMX6Q_FEC,
120 MVF600_FEC,
121 IMX6SX_FEC,
122 };
123
124 static const struct of_device_id fec_dt_ids[] = {
125 { .compatible = "fsl,imx25-fec", .data = &fec_devtype[IMX25_FEC], },
126 { .compatible = "fsl,imx27-fec", .data = &fec_devtype[IMX27_FEC], },
127 { .compatible = "fsl,imx28-fec", .data = &fec_devtype[IMX28_FEC], },
128 { .compatible = "fsl,imx6q-fec", .data = &fec_devtype[IMX6Q_FEC], },
129 { .compatible = "fsl,mvf600-fec", .data = &fec_devtype[MVF600_FEC], },
130 { .compatible = "fsl,imx6sx-fec", .data = &fec_devtype[IMX6SX_FEC], },
131 { /* sentinel */ }
132 };
133 MODULE_DEVICE_TABLE(of, fec_dt_ids);
134
135 static unsigned char macaddr[ETH_ALEN];
136 module_param_array(macaddr, byte, NULL, 0);
137 MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address");
138
139 #if defined(CONFIG_M5272)
140 /*
141 * Some hardware gets it MAC address out of local flash memory.
142 * if this is non-zero then assume it is the address to get MAC from.
143 */
144 #if defined(CONFIG_NETtel)
145 #define FEC_FLASHMAC 0xf0006006
146 #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES)
147 #define FEC_FLASHMAC 0xf0006000
148 #elif defined(CONFIG_CANCam)
149 #define FEC_FLASHMAC 0xf0020000
150 #elif defined (CONFIG_M5272C3)
151 #define FEC_FLASHMAC (0xffe04000 + 4)
152 #elif defined(CONFIG_MOD5272)
153 #define FEC_FLASHMAC 0xffc0406b
154 #else
155 #define FEC_FLASHMAC 0
156 #endif
157 #endif /* CONFIG_M5272 */
158
159 /* The FEC stores dest/src/type/vlan, data, and checksum for receive packets.
160 */
161 #define PKT_MAXBUF_SIZE 1522
162 #define PKT_MINBUF_SIZE 64
163 #define PKT_MAXBLR_SIZE 1536
164
165 /* FEC receive acceleration */
166 #define FEC_RACC_IPDIS (1 << 1)
167 #define FEC_RACC_PRODIS (1 << 2)
168 #define FEC_RACC_OPTIONS (FEC_RACC_IPDIS | FEC_RACC_PRODIS)
169
170 /*
171 * The 5270/5271/5280/5282/532x RX control register also contains maximum frame
172 * size bits. Other FEC hardware does not, so we need to take that into
173 * account when setting it.
174 */
175 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
176 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM)
177 #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16)
178 #else
179 #define OPT_FRAME_SIZE 0
180 #endif
181
182 /* FEC MII MMFR bits definition */
183 #define FEC_MMFR_ST (1 << 30)
184 #define FEC_MMFR_OP_READ (2 << 28)
185 #define FEC_MMFR_OP_WRITE (1 << 28)
186 #define FEC_MMFR_PA(v) ((v & 0x1f) << 23)
187 #define FEC_MMFR_RA(v) ((v & 0x1f) << 18)
188 #define FEC_MMFR_TA (2 << 16)
189 #define FEC_MMFR_DATA(v) (v & 0xffff)
190
191 #define FEC_MII_TIMEOUT 30000 /* us */
192
193 /* Transmitter timeout */
194 #define TX_TIMEOUT (2 * HZ)
195
196 #define FEC_PAUSE_FLAG_AUTONEG 0x1
197 #define FEC_PAUSE_FLAG_ENABLE 0x2
198
199 #define COPYBREAK_DEFAULT 256
200
201 #define TSO_HEADER_SIZE 128
202 /* Max number of allowed TCP segments for software TSO */
203 #define FEC_MAX_TSO_SEGS 100
204 #define FEC_MAX_SKB_DESCS (FEC_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS)
205
206 #define IS_TSO_HEADER(txq, addr) \
207 ((addr >= txq->tso_hdrs_dma) && \
208 (addr < txq->tso_hdrs_dma + txq->tx_ring_size * TSO_HEADER_SIZE))
209
210 static int mii_cnt;
211
212 static inline
fec_enet_get_nextdesc(struct bufdesc * bdp,struct fec_enet_private * fep,int queue_id)213 struct bufdesc *fec_enet_get_nextdesc(struct bufdesc *bdp,
214 struct fec_enet_private *fep,
215 int queue_id)
216 {
217 struct bufdesc *new_bd = bdp + 1;
218 struct bufdesc_ex *ex_new_bd = (struct bufdesc_ex *)bdp + 1;
219 struct fec_enet_priv_tx_q *txq = fep->tx_queue[queue_id];
220 struct fec_enet_priv_rx_q *rxq = fep->rx_queue[queue_id];
221 struct bufdesc_ex *ex_base;
222 struct bufdesc *base;
223 int ring_size;
224
225 if (bdp >= txq->tx_bd_base) {
226 base = txq->tx_bd_base;
227 ring_size = txq->tx_ring_size;
228 ex_base = (struct bufdesc_ex *)txq->tx_bd_base;
229 } else {
230 base = rxq->rx_bd_base;
231 ring_size = rxq->rx_ring_size;
232 ex_base = (struct bufdesc_ex *)rxq->rx_bd_base;
233 }
234
235 if (fep->bufdesc_ex)
236 return (struct bufdesc *)((ex_new_bd >= (ex_base + ring_size)) ?
237 ex_base : ex_new_bd);
238 else
239 return (new_bd >= (base + ring_size)) ?
240 base : new_bd;
241 }
242
243 static inline
fec_enet_get_prevdesc(struct bufdesc * bdp,struct fec_enet_private * fep,int queue_id)244 struct bufdesc *fec_enet_get_prevdesc(struct bufdesc *bdp,
245 struct fec_enet_private *fep,
246 int queue_id)
247 {
248 struct bufdesc *new_bd = bdp - 1;
249 struct bufdesc_ex *ex_new_bd = (struct bufdesc_ex *)bdp - 1;
250 struct fec_enet_priv_tx_q *txq = fep->tx_queue[queue_id];
251 struct fec_enet_priv_rx_q *rxq = fep->rx_queue[queue_id];
252 struct bufdesc_ex *ex_base;
253 struct bufdesc *base;
254 int ring_size;
255
256 if (bdp >= txq->tx_bd_base) {
257 base = txq->tx_bd_base;
258 ring_size = txq->tx_ring_size;
259 ex_base = (struct bufdesc_ex *)txq->tx_bd_base;
260 } else {
261 base = rxq->rx_bd_base;
262 ring_size = rxq->rx_ring_size;
263 ex_base = (struct bufdesc_ex *)rxq->rx_bd_base;
264 }
265
266 if (fep->bufdesc_ex)
267 return (struct bufdesc *)((ex_new_bd < ex_base) ?
268 (ex_new_bd + ring_size) : ex_new_bd);
269 else
270 return (new_bd < base) ? (new_bd + ring_size) : new_bd;
271 }
272
fec_enet_get_bd_index(struct bufdesc * base,struct bufdesc * bdp,struct fec_enet_private * fep)273 static int fec_enet_get_bd_index(struct bufdesc *base, struct bufdesc *bdp,
274 struct fec_enet_private *fep)
275 {
276 return ((const char *)bdp - (const char *)base) / fep->bufdesc_size;
277 }
278
fec_enet_get_free_txdesc_num(struct fec_enet_private * fep,struct fec_enet_priv_tx_q * txq)279 static int fec_enet_get_free_txdesc_num(struct fec_enet_private *fep,
280 struct fec_enet_priv_tx_q *txq)
281 {
282 int entries;
283
284 entries = ((const char *)txq->dirty_tx -
285 (const char *)txq->cur_tx) / fep->bufdesc_size - 1;
286
287 return entries > 0 ? entries : entries + txq->tx_ring_size;
288 }
289
swap_buffer(void * bufaddr,int len)290 static void *swap_buffer(void *bufaddr, int len)
291 {
292 int i;
293 unsigned int *buf = bufaddr;
294
295 for (i = 0; i < DIV_ROUND_UP(len, 4); i++, buf++)
296 *buf = cpu_to_be32(*buf);
297
298 return bufaddr;
299 }
300
swap_buffer2(void * dst_buf,void * src_buf,int len)301 static void swap_buffer2(void *dst_buf, void *src_buf, int len)
302 {
303 int i;
304 unsigned int *src = src_buf;
305 unsigned int *dst = dst_buf;
306
307 for (i = 0; i < len; i += 4, src++, dst++)
308 *dst = swab32p(src);
309 }
310
fec_dump(struct net_device * ndev)311 static void fec_dump(struct net_device *ndev)
312 {
313 struct fec_enet_private *fep = netdev_priv(ndev);
314 struct bufdesc *bdp;
315 struct fec_enet_priv_tx_q *txq;
316 int index = 0;
317
318 netdev_info(ndev, "TX ring dump\n");
319 pr_info("Nr SC addr len SKB\n");
320
321 txq = fep->tx_queue[0];
322 bdp = txq->tx_bd_base;
323
324 do {
325 pr_info("%3u %c%c 0x%04x 0x%08lx %4u %p\n",
326 index,
327 bdp == txq->cur_tx ? 'S' : ' ',
328 bdp == txq->dirty_tx ? 'H' : ' ',
329 bdp->cbd_sc, bdp->cbd_bufaddr, bdp->cbd_datlen,
330 txq->tx_skbuff[index]);
331 bdp = fec_enet_get_nextdesc(bdp, fep, 0);
332 index++;
333 } while (bdp != txq->tx_bd_base);
334 }
335
is_ipv4_pkt(struct sk_buff * skb)336 static inline bool is_ipv4_pkt(struct sk_buff *skb)
337 {
338 return skb->protocol == htons(ETH_P_IP) && ip_hdr(skb)->version == 4;
339 }
340
341 static int
fec_enet_clear_csum(struct sk_buff * skb,struct net_device * ndev)342 fec_enet_clear_csum(struct sk_buff *skb, struct net_device *ndev)
343 {
344 /* Only run for packets requiring a checksum. */
345 if (skb->ip_summed != CHECKSUM_PARTIAL)
346 return 0;
347
348 if (unlikely(skb_cow_head(skb, 0)))
349 return -1;
350
351 if (is_ipv4_pkt(skb))
352 ip_hdr(skb)->check = 0;
353 *(__sum16 *)(skb->head + skb->csum_start + skb->csum_offset) = 0;
354
355 return 0;
356 }
357
358 static int
fec_enet_txq_submit_frag_skb(struct fec_enet_priv_tx_q * txq,struct sk_buff * skb,struct net_device * ndev)359 fec_enet_txq_submit_frag_skb(struct fec_enet_priv_tx_q *txq,
360 struct sk_buff *skb,
361 struct net_device *ndev)
362 {
363 struct fec_enet_private *fep = netdev_priv(ndev);
364 const struct platform_device_id *id_entry =
365 platform_get_device_id(fep->pdev);
366 struct bufdesc *bdp = txq->cur_tx;
367 struct bufdesc_ex *ebdp;
368 int nr_frags = skb_shinfo(skb)->nr_frags;
369 unsigned short queue = skb_get_queue_mapping(skb);
370 int frag, frag_len;
371 unsigned short status;
372 unsigned int estatus = 0;
373 skb_frag_t *this_frag;
374 unsigned int index;
375 void *bufaddr;
376 dma_addr_t addr;
377 int i;
378
379 for (frag = 0; frag < nr_frags; frag++) {
380 this_frag = &skb_shinfo(skb)->frags[frag];
381 bdp = fec_enet_get_nextdesc(bdp, fep, queue);
382 ebdp = (struct bufdesc_ex *)bdp;
383
384 status = bdp->cbd_sc;
385 status &= ~BD_ENET_TX_STATS;
386 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY);
387 frag_len = skb_shinfo(skb)->frags[frag].size;
388
389 /* Handle the last BD specially */
390 if (frag == nr_frags - 1) {
391 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST);
392 if (fep->bufdesc_ex) {
393 estatus |= BD_ENET_TX_INT;
394 if (unlikely(skb_shinfo(skb)->tx_flags &
395 SKBTX_HW_TSTAMP && fep->hwts_tx_en))
396 estatus |= BD_ENET_TX_TS;
397 }
398 }
399
400 if (fep->bufdesc_ex) {
401 if (id_entry->driver_data & FEC_QUIRK_HAS_AVB)
402 estatus |= FEC_TX_BD_FTYPE(queue);
403 if (skb->ip_summed == CHECKSUM_PARTIAL)
404 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
405 ebdp->cbd_bdu = 0;
406 ebdp->cbd_esc = estatus;
407 }
408
409 bufaddr = page_address(this_frag->page.p) + this_frag->page_offset;
410
411 index = fec_enet_get_bd_index(txq->tx_bd_base, bdp, fep);
412 if (((unsigned long) bufaddr) & fep->tx_align ||
413 id_entry->driver_data & FEC_QUIRK_SWAP_FRAME) {
414 memcpy(txq->tx_bounce[index], bufaddr, frag_len);
415 bufaddr = txq->tx_bounce[index];
416
417 if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME)
418 swap_buffer(bufaddr, frag_len);
419 }
420
421 addr = dma_map_single(&fep->pdev->dev, bufaddr, frag_len,
422 DMA_TO_DEVICE);
423 if (dma_mapping_error(&fep->pdev->dev, addr)) {
424 dev_kfree_skb_any(skb);
425 if (net_ratelimit())
426 netdev_err(ndev, "Tx DMA memory map failed\n");
427 goto dma_mapping_error;
428 }
429
430 bdp->cbd_bufaddr = addr;
431 bdp->cbd_datlen = frag_len;
432 bdp->cbd_sc = status;
433 }
434
435 txq->cur_tx = bdp;
436
437 return 0;
438
439 dma_mapping_error:
440 bdp = txq->cur_tx;
441 for (i = 0; i < frag; i++) {
442 bdp = fec_enet_get_nextdesc(bdp, fep, queue);
443 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
444 bdp->cbd_datlen, DMA_TO_DEVICE);
445 }
446 return NETDEV_TX_OK;
447 }
448
fec_enet_txq_submit_skb(struct fec_enet_priv_tx_q * txq,struct sk_buff * skb,struct net_device * ndev)449 static int fec_enet_txq_submit_skb(struct fec_enet_priv_tx_q *txq,
450 struct sk_buff *skb, struct net_device *ndev)
451 {
452 struct fec_enet_private *fep = netdev_priv(ndev);
453 const struct platform_device_id *id_entry =
454 platform_get_device_id(fep->pdev);
455 int nr_frags = skb_shinfo(skb)->nr_frags;
456 struct bufdesc *bdp, *last_bdp;
457 void *bufaddr;
458 dma_addr_t addr;
459 unsigned short status;
460 unsigned short buflen;
461 unsigned short queue;
462 unsigned int estatus = 0;
463 unsigned int index;
464 int entries_free;
465 int ret;
466
467 entries_free = fec_enet_get_free_txdesc_num(fep, txq);
468 if (entries_free < MAX_SKB_FRAGS + 1) {
469 dev_kfree_skb_any(skb);
470 if (net_ratelimit())
471 netdev_err(ndev, "NOT enough BD for SG!\n");
472 return NETDEV_TX_OK;
473 }
474
475 /* Protocol checksum off-load for TCP and UDP. */
476 if (fec_enet_clear_csum(skb, ndev)) {
477 dev_kfree_skb_any(skb);
478 return NETDEV_TX_OK;
479 }
480
481 /* Fill in a Tx ring entry */
482 bdp = txq->cur_tx;
483 status = bdp->cbd_sc;
484 status &= ~BD_ENET_TX_STATS;
485
486 /* Set buffer length and buffer pointer */
487 bufaddr = skb->data;
488 buflen = skb_headlen(skb);
489
490 queue = skb_get_queue_mapping(skb);
491 index = fec_enet_get_bd_index(txq->tx_bd_base, bdp, fep);
492 if (((unsigned long) bufaddr) & fep->tx_align ||
493 id_entry->driver_data & FEC_QUIRK_SWAP_FRAME) {
494 memcpy(txq->tx_bounce[index], skb->data, buflen);
495 bufaddr = txq->tx_bounce[index];
496
497 if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME)
498 swap_buffer(bufaddr, buflen);
499 }
500
501 /* Push the data cache so the CPM does not get stale memory data. */
502 addr = dma_map_single(&fep->pdev->dev, bufaddr, buflen, DMA_TO_DEVICE);
503 if (dma_mapping_error(&fep->pdev->dev, addr)) {
504 dev_kfree_skb_any(skb);
505 if (net_ratelimit())
506 netdev_err(ndev, "Tx DMA memory map failed\n");
507 return NETDEV_TX_OK;
508 }
509
510 if (nr_frags) {
511 ret = fec_enet_txq_submit_frag_skb(txq, skb, ndev);
512 if (ret)
513 return ret;
514 } else {
515 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST);
516 if (fep->bufdesc_ex) {
517 estatus = BD_ENET_TX_INT;
518 if (unlikely(skb_shinfo(skb)->tx_flags &
519 SKBTX_HW_TSTAMP && fep->hwts_tx_en))
520 estatus |= BD_ENET_TX_TS;
521 }
522 }
523
524 if (fep->bufdesc_ex) {
525
526 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
527
528 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
529 fep->hwts_tx_en))
530 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
531
532 if (id_entry->driver_data & FEC_QUIRK_HAS_AVB)
533 estatus |= FEC_TX_BD_FTYPE(queue);
534
535 if (skb->ip_summed == CHECKSUM_PARTIAL)
536 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
537
538 ebdp->cbd_bdu = 0;
539 ebdp->cbd_esc = estatus;
540 }
541
542 last_bdp = txq->cur_tx;
543 index = fec_enet_get_bd_index(txq->tx_bd_base, last_bdp, fep);
544 /* Save skb pointer */
545 txq->tx_skbuff[index] = skb;
546
547 bdp->cbd_datlen = buflen;
548 bdp->cbd_bufaddr = addr;
549
550 /* Send it on its way. Tell FEC it's ready, interrupt when done,
551 * it's the last BD of the frame, and to put the CRC on the end.
552 */
553 status |= (BD_ENET_TX_READY | BD_ENET_TX_TC);
554 bdp->cbd_sc = status;
555
556 /* If this was the last BD in the ring, start at the beginning again. */
557 bdp = fec_enet_get_nextdesc(last_bdp, fep, queue);
558
559 skb_tx_timestamp(skb);
560
561 txq->cur_tx = bdp;
562
563 /* Trigger transmission start */
564 writel(0, fep->hwp + FEC_X_DES_ACTIVE(queue));
565
566 return 0;
567 }
568
569 static int
fec_enet_txq_put_data_tso(struct fec_enet_priv_tx_q * txq,struct sk_buff * skb,struct net_device * ndev,struct bufdesc * bdp,int index,char * data,int size,bool last_tcp,bool is_last)570 fec_enet_txq_put_data_tso(struct fec_enet_priv_tx_q *txq, struct sk_buff *skb,
571 struct net_device *ndev,
572 struct bufdesc *bdp, int index, char *data,
573 int size, bool last_tcp, bool is_last)
574 {
575 struct fec_enet_private *fep = netdev_priv(ndev);
576 const struct platform_device_id *id_entry =
577 platform_get_device_id(fep->pdev);
578 struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc);
579 unsigned short queue = skb_get_queue_mapping(skb);
580 unsigned short status;
581 unsigned int estatus = 0;
582 dma_addr_t addr;
583
584 status = bdp->cbd_sc;
585 status &= ~BD_ENET_TX_STATS;
586
587 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY);
588
589 if (((unsigned long) data) & fep->tx_align ||
590 id_entry->driver_data & FEC_QUIRK_SWAP_FRAME) {
591 memcpy(txq->tx_bounce[index], data, size);
592 data = txq->tx_bounce[index];
593
594 if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME)
595 swap_buffer(data, size);
596 }
597
598 addr = dma_map_single(&fep->pdev->dev, data, size, DMA_TO_DEVICE);
599 if (dma_mapping_error(&fep->pdev->dev, addr)) {
600 dev_kfree_skb_any(skb);
601 if (net_ratelimit())
602 netdev_err(ndev, "Tx DMA memory map failed\n");
603 return NETDEV_TX_BUSY;
604 }
605
606 bdp->cbd_datlen = size;
607 bdp->cbd_bufaddr = addr;
608
609 if (fep->bufdesc_ex) {
610 if (id_entry->driver_data & FEC_QUIRK_HAS_AVB)
611 estatus |= FEC_TX_BD_FTYPE(queue);
612 if (skb->ip_summed == CHECKSUM_PARTIAL)
613 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
614 ebdp->cbd_bdu = 0;
615 ebdp->cbd_esc = estatus;
616 }
617
618 /* Handle the last BD specially */
619 if (last_tcp)
620 status |= (BD_ENET_TX_LAST | BD_ENET_TX_TC);
621 if (is_last) {
622 status |= BD_ENET_TX_INTR;
623 if (fep->bufdesc_ex)
624 ebdp->cbd_esc |= BD_ENET_TX_INT;
625 }
626
627 bdp->cbd_sc = status;
628
629 return 0;
630 }
631
632 static int
fec_enet_txq_put_hdr_tso(struct fec_enet_priv_tx_q * txq,struct sk_buff * skb,struct net_device * ndev,struct bufdesc * bdp,int index)633 fec_enet_txq_put_hdr_tso(struct fec_enet_priv_tx_q *txq,
634 struct sk_buff *skb, struct net_device *ndev,
635 struct bufdesc *bdp, int index)
636 {
637 struct fec_enet_private *fep = netdev_priv(ndev);
638 const struct platform_device_id *id_entry =
639 platform_get_device_id(fep->pdev);
640 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
641 struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc);
642 unsigned short queue = skb_get_queue_mapping(skb);
643 void *bufaddr;
644 unsigned long dmabuf;
645 unsigned short status;
646 unsigned int estatus = 0;
647
648 status = bdp->cbd_sc;
649 status &= ~BD_ENET_TX_STATS;
650 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY);
651
652 bufaddr = txq->tso_hdrs + index * TSO_HEADER_SIZE;
653 dmabuf = txq->tso_hdrs_dma + index * TSO_HEADER_SIZE;
654 if (((unsigned long)bufaddr) & fep->tx_align ||
655 id_entry->driver_data & FEC_QUIRK_SWAP_FRAME) {
656 memcpy(txq->tx_bounce[index], skb->data, hdr_len);
657 bufaddr = txq->tx_bounce[index];
658
659 if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME)
660 swap_buffer(bufaddr, hdr_len);
661
662 dmabuf = dma_map_single(&fep->pdev->dev, bufaddr,
663 hdr_len, DMA_TO_DEVICE);
664 if (dma_mapping_error(&fep->pdev->dev, dmabuf)) {
665 dev_kfree_skb_any(skb);
666 if (net_ratelimit())
667 netdev_err(ndev, "Tx DMA memory map failed\n");
668 return NETDEV_TX_BUSY;
669 }
670 }
671
672 bdp->cbd_bufaddr = dmabuf;
673 bdp->cbd_datlen = hdr_len;
674
675 if (fep->bufdesc_ex) {
676 if (id_entry->driver_data & FEC_QUIRK_HAS_AVB)
677 estatus |= FEC_TX_BD_FTYPE(queue);
678 if (skb->ip_summed == CHECKSUM_PARTIAL)
679 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
680 ebdp->cbd_bdu = 0;
681 ebdp->cbd_esc = estatus;
682 }
683
684 bdp->cbd_sc = status;
685
686 return 0;
687 }
688
fec_enet_txq_submit_tso(struct fec_enet_priv_tx_q * txq,struct sk_buff * skb,struct net_device * ndev)689 static int fec_enet_txq_submit_tso(struct fec_enet_priv_tx_q *txq,
690 struct sk_buff *skb,
691 struct net_device *ndev)
692 {
693 struct fec_enet_private *fep = netdev_priv(ndev);
694 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
695 int total_len, data_left;
696 struct bufdesc *bdp = txq->cur_tx;
697 unsigned short queue = skb_get_queue_mapping(skb);
698 struct tso_t tso;
699 unsigned int index = 0;
700 int ret;
701 const struct platform_device_id *id_entry =
702 platform_get_device_id(fep->pdev);
703
704 if (tso_count_descs(skb) >= fec_enet_get_free_txdesc_num(fep, txq)) {
705 dev_kfree_skb_any(skb);
706 if (net_ratelimit())
707 netdev_err(ndev, "NOT enough BD for TSO!\n");
708 return NETDEV_TX_OK;
709 }
710
711 /* Protocol checksum off-load for TCP and UDP. */
712 if (fec_enet_clear_csum(skb, ndev)) {
713 dev_kfree_skb_any(skb);
714 return NETDEV_TX_OK;
715 }
716
717 /* Initialize the TSO handler, and prepare the first payload */
718 tso_start(skb, &tso);
719
720 total_len = skb->len - hdr_len;
721 while (total_len > 0) {
722 char *hdr;
723
724 index = fec_enet_get_bd_index(txq->tx_bd_base, bdp, fep);
725 data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len);
726 total_len -= data_left;
727
728 /* prepare packet headers: MAC + IP + TCP */
729 hdr = txq->tso_hdrs + index * TSO_HEADER_SIZE;
730 tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0);
731 ret = fec_enet_txq_put_hdr_tso(txq, skb, ndev, bdp, index);
732 if (ret)
733 goto err_release;
734
735 while (data_left > 0) {
736 int size;
737
738 size = min_t(int, tso.size, data_left);
739 bdp = fec_enet_get_nextdesc(bdp, fep, queue);
740 index = fec_enet_get_bd_index(txq->tx_bd_base,
741 bdp, fep);
742 ret = fec_enet_txq_put_data_tso(txq, skb, ndev,
743 bdp, index,
744 tso.data, size,
745 size == data_left,
746 total_len == 0);
747 if (ret)
748 goto err_release;
749
750 data_left -= size;
751 tso_build_data(skb, &tso, size);
752 }
753
754 bdp = fec_enet_get_nextdesc(bdp, fep, queue);
755 }
756
757 /* Save skb pointer */
758 txq->tx_skbuff[index] = skb;
759
760 skb_tx_timestamp(skb);
761 txq->cur_tx = bdp;
762
763 /* Trigger transmission start */
764 if (!(id_entry->driver_data & FEC_QUIRK_ERR007885) ||
765 !readl(fep->hwp + FEC_X_DES_ACTIVE(queue)) ||
766 !readl(fep->hwp + FEC_X_DES_ACTIVE(queue)) ||
767 !readl(fep->hwp + FEC_X_DES_ACTIVE(queue)) ||
768 !readl(fep->hwp + FEC_X_DES_ACTIVE(queue)))
769 writel(0, fep->hwp + FEC_X_DES_ACTIVE(queue));
770
771 return 0;
772
773 err_release:
774 /* TODO: Release all used data descriptors for TSO */
775 return ret;
776 }
777
778 static netdev_tx_t
fec_enet_start_xmit(struct sk_buff * skb,struct net_device * ndev)779 fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev)
780 {
781 struct fec_enet_private *fep = netdev_priv(ndev);
782 int entries_free;
783 unsigned short queue;
784 struct fec_enet_priv_tx_q *txq;
785 struct netdev_queue *nq;
786 int ret;
787
788 queue = skb_get_queue_mapping(skb);
789 txq = fep->tx_queue[queue];
790 nq = netdev_get_tx_queue(ndev, queue);
791
792 if (skb_is_gso(skb))
793 ret = fec_enet_txq_submit_tso(txq, skb, ndev);
794 else
795 ret = fec_enet_txq_submit_skb(txq, skb, ndev);
796 if (ret)
797 return ret;
798
799 entries_free = fec_enet_get_free_txdesc_num(fep, txq);
800 if (entries_free <= txq->tx_stop_threshold)
801 netif_tx_stop_queue(nq);
802
803 return NETDEV_TX_OK;
804 }
805
806 /* Init RX & TX buffer descriptors
807 */
fec_enet_bd_init(struct net_device * dev)808 static void fec_enet_bd_init(struct net_device *dev)
809 {
810 struct fec_enet_private *fep = netdev_priv(dev);
811 struct fec_enet_priv_tx_q *txq;
812 struct fec_enet_priv_rx_q *rxq;
813 struct bufdesc *bdp;
814 unsigned int i;
815 unsigned int q;
816
817 for (q = 0; q < fep->num_rx_queues; q++) {
818 /* Initialize the receive buffer descriptors. */
819 rxq = fep->rx_queue[q];
820 bdp = rxq->rx_bd_base;
821
822 for (i = 0; i < rxq->rx_ring_size; i++) {
823
824 /* Initialize the BD for every fragment in the page. */
825 if (bdp->cbd_bufaddr)
826 bdp->cbd_sc = BD_ENET_RX_EMPTY;
827 else
828 bdp->cbd_sc = 0;
829 bdp = fec_enet_get_nextdesc(bdp, fep, q);
830 }
831
832 /* Set the last buffer to wrap */
833 bdp = fec_enet_get_prevdesc(bdp, fep, q);
834 bdp->cbd_sc |= BD_SC_WRAP;
835
836 rxq->cur_rx = rxq->rx_bd_base;
837 }
838
839 for (q = 0; q < fep->num_tx_queues; q++) {
840 /* ...and the same for transmit */
841 txq = fep->tx_queue[q];
842 bdp = txq->tx_bd_base;
843 txq->cur_tx = bdp;
844
845 for (i = 0; i < txq->tx_ring_size; i++) {
846 /* Initialize the BD for every fragment in the page. */
847 bdp->cbd_sc = 0;
848 if (txq->tx_skbuff[i]) {
849 dev_kfree_skb_any(txq->tx_skbuff[i]);
850 txq->tx_skbuff[i] = NULL;
851 }
852 bdp->cbd_bufaddr = 0;
853 bdp = fec_enet_get_nextdesc(bdp, fep, q);
854 }
855
856 /* Set the last buffer to wrap */
857 bdp = fec_enet_get_prevdesc(bdp, fep, q);
858 bdp->cbd_sc |= BD_SC_WRAP;
859 txq->dirty_tx = bdp;
860 }
861 }
862
fec_enet_active_rxring(struct net_device * ndev)863 static void fec_enet_active_rxring(struct net_device *ndev)
864 {
865 struct fec_enet_private *fep = netdev_priv(ndev);
866 int i;
867
868 for (i = 0; i < fep->num_rx_queues; i++)
869 writel(0, fep->hwp + FEC_R_DES_ACTIVE(i));
870 }
871
fec_enet_enable_ring(struct net_device * ndev)872 static void fec_enet_enable_ring(struct net_device *ndev)
873 {
874 struct fec_enet_private *fep = netdev_priv(ndev);
875 struct fec_enet_priv_tx_q *txq;
876 struct fec_enet_priv_rx_q *rxq;
877 int i;
878
879 for (i = 0; i < fep->num_rx_queues; i++) {
880 rxq = fep->rx_queue[i];
881 writel(rxq->bd_dma, fep->hwp + FEC_R_DES_START(i));
882
883 /* enable DMA1/2 */
884 if (i)
885 writel(RCMR_MATCHEN | RCMR_CMP(i),
886 fep->hwp + FEC_RCMR(i));
887 }
888
889 for (i = 0; i < fep->num_tx_queues; i++) {
890 txq = fep->tx_queue[i];
891 writel(txq->bd_dma, fep->hwp + FEC_X_DES_START(i));
892
893 /* enable DMA1/2 */
894 if (i)
895 writel(DMA_CLASS_EN | IDLE_SLOPE(i),
896 fep->hwp + FEC_DMA_CFG(i));
897 }
898 }
899
fec_enet_reset_skb(struct net_device * ndev)900 static void fec_enet_reset_skb(struct net_device *ndev)
901 {
902 struct fec_enet_private *fep = netdev_priv(ndev);
903 struct fec_enet_priv_tx_q *txq;
904 int i, j;
905
906 for (i = 0; i < fep->num_tx_queues; i++) {
907 txq = fep->tx_queue[i];
908
909 for (j = 0; j < txq->tx_ring_size; j++) {
910 if (txq->tx_skbuff[j]) {
911 dev_kfree_skb_any(txq->tx_skbuff[j]);
912 txq->tx_skbuff[j] = NULL;
913 }
914 }
915 }
916 }
917
918 /*
919 * This function is called to start or restart the FEC during a link
920 * change, transmit timeout, or to reconfigure the FEC. The network
921 * packet processing for this device must be stopped before this call.
922 */
923 static void
fec_restart(struct net_device * ndev)924 fec_restart(struct net_device *ndev)
925 {
926 struct fec_enet_private *fep = netdev_priv(ndev);
927 const struct platform_device_id *id_entry =
928 platform_get_device_id(fep->pdev);
929 u32 val;
930 u32 temp_mac[2];
931 u32 rcntl = OPT_FRAME_SIZE | 0x04;
932 u32 ecntl = 0x2; /* ETHEREN */
933
934 /* Whack a reset. We should wait for this.
935 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC
936 * instead of reset MAC itself.
937 */
938 if (id_entry && id_entry->driver_data & FEC_QUIRK_HAS_AVB) {
939 writel(0, fep->hwp + FEC_ECNTRL);
940 } else {
941 writel(1, fep->hwp + FEC_ECNTRL);
942 udelay(10);
943 }
944
945 /*
946 * enet-mac reset will reset mac address registers too,
947 * so need to reconfigure it.
948 */
949 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
950 memcpy(&temp_mac, ndev->dev_addr, ETH_ALEN);
951 writel(cpu_to_be32(temp_mac[0]), fep->hwp + FEC_ADDR_LOW);
952 writel(cpu_to_be32(temp_mac[1]), fep->hwp + FEC_ADDR_HIGH);
953 }
954
955 /* Clear any outstanding interrupt. */
956 writel(0xffc00000, fep->hwp + FEC_IEVENT);
957
958 /* Set maximum receive buffer size. */
959 writel(PKT_MAXBLR_SIZE, fep->hwp + FEC_R_BUFF_SIZE);
960
961 fec_enet_bd_init(ndev);
962
963 fec_enet_enable_ring(ndev);
964
965 /* Reset tx SKB buffers. */
966 fec_enet_reset_skb(ndev);
967
968 /* Enable MII mode */
969 if (fep->full_duplex == DUPLEX_FULL) {
970 /* FD enable */
971 writel(0x04, fep->hwp + FEC_X_CNTRL);
972 } else {
973 /* No Rcv on Xmit */
974 rcntl |= 0x02;
975 writel(0x0, fep->hwp + FEC_X_CNTRL);
976 }
977
978 /* Set MII speed */
979 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
980
981 #if !defined(CONFIG_M5272)
982 /* set RX checksum */
983 val = readl(fep->hwp + FEC_RACC);
984 if (fep->csum_flags & FLAG_RX_CSUM_ENABLED)
985 val |= FEC_RACC_OPTIONS;
986 else
987 val &= ~FEC_RACC_OPTIONS;
988 writel(val, fep->hwp + FEC_RACC);
989 #endif
990
991 /*
992 * The phy interface and speed need to get configured
993 * differently on enet-mac.
994 */
995 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
996 /* Enable flow control and length check */
997 rcntl |= 0x40000000 | 0x00000020;
998
999 /* RGMII, RMII or MII */
1000 if (fep->phy_interface == PHY_INTERFACE_MODE_RGMII)
1001 rcntl |= (1 << 6);
1002 else if (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
1003 rcntl |= (1 << 8);
1004 else
1005 rcntl &= ~(1 << 8);
1006
1007 /* 1G, 100M or 10M */
1008 if (fep->phy_dev) {
1009 if (fep->phy_dev->speed == SPEED_1000)
1010 ecntl |= (1 << 5);
1011 else if (fep->phy_dev->speed == SPEED_100)
1012 rcntl &= ~(1 << 9);
1013 else
1014 rcntl |= (1 << 9);
1015 }
1016 } else {
1017 #ifdef FEC_MIIGSK_ENR
1018 if (id_entry->driver_data & FEC_QUIRK_USE_GASKET) {
1019 u32 cfgr;
1020 /* disable the gasket and wait */
1021 writel(0, fep->hwp + FEC_MIIGSK_ENR);
1022 while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4)
1023 udelay(1);
1024
1025 /*
1026 * configure the gasket:
1027 * RMII, 50 MHz, no loopback, no echo
1028 * MII, 25 MHz, no loopback, no echo
1029 */
1030 cfgr = (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
1031 ? BM_MIIGSK_CFGR_RMII : BM_MIIGSK_CFGR_MII;
1032 if (fep->phy_dev && fep->phy_dev->speed == SPEED_10)
1033 cfgr |= BM_MIIGSK_CFGR_FRCONT_10M;
1034 writel(cfgr, fep->hwp + FEC_MIIGSK_CFGR);
1035
1036 /* re-enable the gasket */
1037 writel(2, fep->hwp + FEC_MIIGSK_ENR);
1038 }
1039 #endif
1040 }
1041
1042 #if !defined(CONFIG_M5272)
1043 /* enable pause frame*/
1044 if ((fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) ||
1045 ((fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) &&
1046 fep->phy_dev && fep->phy_dev->pause)) {
1047 rcntl |= FEC_ENET_FCE;
1048
1049 /* set FIFO threshold parameter to reduce overrun */
1050 writel(FEC_ENET_RSEM_V, fep->hwp + FEC_R_FIFO_RSEM);
1051 writel(FEC_ENET_RSFL_V, fep->hwp + FEC_R_FIFO_RSFL);
1052 writel(FEC_ENET_RAEM_V, fep->hwp + FEC_R_FIFO_RAEM);
1053 writel(FEC_ENET_RAFL_V, fep->hwp + FEC_R_FIFO_RAFL);
1054
1055 /* OPD */
1056 writel(FEC_ENET_OPD_V, fep->hwp + FEC_OPD);
1057 } else {
1058 rcntl &= ~FEC_ENET_FCE;
1059 }
1060 #endif /* !defined(CONFIG_M5272) */
1061
1062 writel(rcntl, fep->hwp + FEC_R_CNTRL);
1063
1064 /* Setup multicast filter. */
1065 set_multicast_list(ndev);
1066 #ifndef CONFIG_M5272
1067 writel(0, fep->hwp + FEC_HASH_TABLE_HIGH);
1068 writel(0, fep->hwp + FEC_HASH_TABLE_LOW);
1069 #endif
1070
1071 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
1072 /* enable ENET endian swap */
1073 ecntl |= (1 << 8);
1074 /* enable ENET store and forward mode */
1075 writel(1 << 8, fep->hwp + FEC_X_WMRK);
1076 }
1077
1078 if (fep->bufdesc_ex)
1079 ecntl |= (1 << 4);
1080
1081 #ifndef CONFIG_M5272
1082 /* Enable the MIB statistic event counters */
1083 writel(0 << 31, fep->hwp + FEC_MIB_CTRLSTAT);
1084 #endif
1085
1086 /* And last, enable the transmit and receive processing */
1087 writel(ecntl, fep->hwp + FEC_ECNTRL);
1088 fec_enet_active_rxring(ndev);
1089
1090 if (fep->bufdesc_ex)
1091 fec_ptp_start_cyclecounter(ndev);
1092
1093 /* Enable interrupts we wish to service */
1094 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
1095
1096 /* Init the interrupt coalescing */
1097 fec_enet_itr_coal_init(ndev);
1098
1099 }
1100
1101 static void
fec_stop(struct net_device * ndev)1102 fec_stop(struct net_device *ndev)
1103 {
1104 struct fec_enet_private *fep = netdev_priv(ndev);
1105 const struct platform_device_id *id_entry =
1106 platform_get_device_id(fep->pdev);
1107 u32 rmii_mode = readl(fep->hwp + FEC_R_CNTRL) & (1 << 8);
1108
1109 /* We cannot expect a graceful transmit stop without link !!! */
1110 if (fep->link) {
1111 writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */
1112 udelay(10);
1113 if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA))
1114 netdev_err(ndev, "Graceful transmit stop did not complete!\n");
1115 }
1116
1117 /* Whack a reset. We should wait for this.
1118 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC
1119 * instead of reset MAC itself.
1120 */
1121 if (id_entry && id_entry->driver_data & FEC_QUIRK_HAS_AVB) {
1122 writel(0, fep->hwp + FEC_ECNTRL);
1123 } else {
1124 writel(1, fep->hwp + FEC_ECNTRL);
1125 udelay(10);
1126 }
1127 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
1128 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
1129
1130 /* We have to keep ENET enabled to have MII interrupt stay working */
1131 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
1132 writel(2, fep->hwp + FEC_ECNTRL);
1133 writel(rmii_mode, fep->hwp + FEC_R_CNTRL);
1134 }
1135 }
1136
1137
1138 static void
fec_timeout(struct net_device * ndev)1139 fec_timeout(struct net_device *ndev)
1140 {
1141 struct fec_enet_private *fep = netdev_priv(ndev);
1142
1143 fec_dump(ndev);
1144
1145 ndev->stats.tx_errors++;
1146
1147 schedule_work(&fep->tx_timeout_work);
1148 }
1149
fec_enet_timeout_work(struct work_struct * work)1150 static void fec_enet_timeout_work(struct work_struct *work)
1151 {
1152 struct fec_enet_private *fep =
1153 container_of(work, struct fec_enet_private, tx_timeout_work);
1154 struct net_device *ndev = fep->netdev;
1155
1156 rtnl_lock();
1157 if (netif_device_present(ndev) || netif_running(ndev)) {
1158 napi_disable(&fep->napi);
1159 netif_tx_lock_bh(ndev);
1160 fec_restart(ndev);
1161 netif_wake_queue(ndev);
1162 netif_tx_unlock_bh(ndev);
1163 napi_enable(&fep->napi);
1164 }
1165 rtnl_unlock();
1166 }
1167
1168 static void
fec_enet_hwtstamp(struct fec_enet_private * fep,unsigned ts,struct skb_shared_hwtstamps * hwtstamps)1169 fec_enet_hwtstamp(struct fec_enet_private *fep, unsigned ts,
1170 struct skb_shared_hwtstamps *hwtstamps)
1171 {
1172 unsigned long flags;
1173 u64 ns;
1174
1175 spin_lock_irqsave(&fep->tmreg_lock, flags);
1176 ns = timecounter_cyc2time(&fep->tc, ts);
1177 spin_unlock_irqrestore(&fep->tmreg_lock, flags);
1178
1179 memset(hwtstamps, 0, sizeof(*hwtstamps));
1180 hwtstamps->hwtstamp = ns_to_ktime(ns);
1181 }
1182
1183 static void
fec_enet_tx_queue(struct net_device * ndev,u16 queue_id)1184 fec_enet_tx_queue(struct net_device *ndev, u16 queue_id)
1185 {
1186 struct fec_enet_private *fep;
1187 struct bufdesc *bdp;
1188 unsigned short status;
1189 struct sk_buff *skb;
1190 struct fec_enet_priv_tx_q *txq;
1191 struct netdev_queue *nq;
1192 int index = 0;
1193 int entries_free;
1194
1195 fep = netdev_priv(ndev);
1196
1197 queue_id = FEC_ENET_GET_QUQUE(queue_id);
1198
1199 txq = fep->tx_queue[queue_id];
1200 /* get next bdp of dirty_tx */
1201 nq = netdev_get_tx_queue(ndev, queue_id);
1202 bdp = txq->dirty_tx;
1203
1204 /* get next bdp of dirty_tx */
1205 bdp = fec_enet_get_nextdesc(bdp, fep, queue_id);
1206
1207 while (((status = bdp->cbd_sc) & BD_ENET_TX_READY) == 0) {
1208
1209 /* current queue is empty */
1210 if (bdp == txq->cur_tx)
1211 break;
1212
1213 index = fec_enet_get_bd_index(txq->tx_bd_base, bdp, fep);
1214
1215 skb = txq->tx_skbuff[index];
1216 txq->tx_skbuff[index] = NULL;
1217 if (!IS_TSO_HEADER(txq, bdp->cbd_bufaddr))
1218 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
1219 bdp->cbd_datlen, DMA_TO_DEVICE);
1220 bdp->cbd_bufaddr = 0;
1221 if (!skb) {
1222 bdp = fec_enet_get_nextdesc(bdp, fep, queue_id);
1223 continue;
1224 }
1225
1226 /* Check for errors. */
1227 if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC |
1228 BD_ENET_TX_RL | BD_ENET_TX_UN |
1229 BD_ENET_TX_CSL)) {
1230 ndev->stats.tx_errors++;
1231 if (status & BD_ENET_TX_HB) /* No heartbeat */
1232 ndev->stats.tx_heartbeat_errors++;
1233 if (status & BD_ENET_TX_LC) /* Late collision */
1234 ndev->stats.tx_window_errors++;
1235 if (status & BD_ENET_TX_RL) /* Retrans limit */
1236 ndev->stats.tx_aborted_errors++;
1237 if (status & BD_ENET_TX_UN) /* Underrun */
1238 ndev->stats.tx_fifo_errors++;
1239 if (status & BD_ENET_TX_CSL) /* Carrier lost */
1240 ndev->stats.tx_carrier_errors++;
1241 } else {
1242 ndev->stats.tx_packets++;
1243 ndev->stats.tx_bytes += skb->len;
1244 }
1245
1246 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS) &&
1247 fep->bufdesc_ex) {
1248 struct skb_shared_hwtstamps shhwtstamps;
1249 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
1250
1251 fec_enet_hwtstamp(fep, ebdp->ts, &shhwtstamps);
1252 skb_tstamp_tx(skb, &shhwtstamps);
1253 }
1254
1255 /* Deferred means some collisions occurred during transmit,
1256 * but we eventually sent the packet OK.
1257 */
1258 if (status & BD_ENET_TX_DEF)
1259 ndev->stats.collisions++;
1260
1261 /* Free the sk buffer associated with this last transmit */
1262 dev_kfree_skb_any(skb);
1263
1264 txq->dirty_tx = bdp;
1265
1266 /* Update pointer to next buffer descriptor to be transmitted */
1267 bdp = fec_enet_get_nextdesc(bdp, fep, queue_id);
1268
1269 /* Since we have freed up a buffer, the ring is no longer full
1270 */
1271 if (netif_queue_stopped(ndev)) {
1272 entries_free = fec_enet_get_free_txdesc_num(fep, txq);
1273 if (entries_free >= txq->tx_wake_threshold)
1274 netif_tx_wake_queue(nq);
1275 }
1276 }
1277
1278 /* ERR006538: Keep the transmitter going */
1279 if (bdp != txq->cur_tx &&
1280 readl(fep->hwp + FEC_X_DES_ACTIVE(queue_id)) == 0)
1281 writel(0, fep->hwp + FEC_X_DES_ACTIVE(queue_id));
1282 }
1283
1284 static void
fec_enet_tx(struct net_device * ndev)1285 fec_enet_tx(struct net_device *ndev)
1286 {
1287 struct fec_enet_private *fep = netdev_priv(ndev);
1288 u16 queue_id;
1289 /* First process class A queue, then Class B and Best Effort queue */
1290 for_each_set_bit(queue_id, &fep->work_tx, FEC_ENET_MAX_TX_QS) {
1291 clear_bit(queue_id, &fep->work_tx);
1292 fec_enet_tx_queue(ndev, queue_id);
1293 }
1294 return;
1295 }
1296
1297 static int
fec_enet_new_rxbdp(struct net_device * ndev,struct bufdesc * bdp,struct sk_buff * skb)1298 fec_enet_new_rxbdp(struct net_device *ndev, struct bufdesc *bdp, struct sk_buff *skb)
1299 {
1300 struct fec_enet_private *fep = netdev_priv(ndev);
1301 int off;
1302
1303 off = ((unsigned long)skb->data) & fep->rx_align;
1304 if (off)
1305 skb_reserve(skb, fep->rx_align + 1 - off);
1306
1307 bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, skb->data,
1308 FEC_ENET_RX_FRSIZE - fep->rx_align,
1309 DMA_FROM_DEVICE);
1310 if (dma_mapping_error(&fep->pdev->dev, bdp->cbd_bufaddr)) {
1311 if (net_ratelimit())
1312 netdev_err(ndev, "Rx DMA memory map failed\n");
1313 return -ENOMEM;
1314 }
1315
1316 return 0;
1317 }
1318
fec_enet_copybreak(struct net_device * ndev,struct sk_buff ** skb,struct bufdesc * bdp,u32 length,bool swap)1319 static bool fec_enet_copybreak(struct net_device *ndev, struct sk_buff **skb,
1320 struct bufdesc *bdp, u32 length, bool swap)
1321 {
1322 struct fec_enet_private *fep = netdev_priv(ndev);
1323 struct sk_buff *new_skb;
1324
1325 if (length > fep->rx_copybreak)
1326 return false;
1327
1328 new_skb = netdev_alloc_skb(ndev, length);
1329 if (!new_skb)
1330 return false;
1331
1332 dma_sync_single_for_cpu(&fep->pdev->dev, bdp->cbd_bufaddr,
1333 FEC_ENET_RX_FRSIZE - fep->rx_align,
1334 DMA_FROM_DEVICE);
1335 if (!swap)
1336 memcpy(new_skb->data, (*skb)->data, length);
1337 else
1338 swap_buffer2(new_skb->data, (*skb)->data, length);
1339 *skb = new_skb;
1340
1341 return true;
1342 }
1343
1344 /* During a receive, the cur_rx points to the current incoming buffer.
1345 * When we update through the ring, if the next incoming buffer has
1346 * not been given to the system, we just set the empty indicator,
1347 * effectively tossing the packet.
1348 */
1349 static int
fec_enet_rx_queue(struct net_device * ndev,int budget,u16 queue_id)1350 fec_enet_rx_queue(struct net_device *ndev, int budget, u16 queue_id)
1351 {
1352 struct fec_enet_private *fep = netdev_priv(ndev);
1353 const struct platform_device_id *id_entry =
1354 platform_get_device_id(fep->pdev);
1355 struct fec_enet_priv_rx_q *rxq;
1356 struct bufdesc *bdp;
1357 unsigned short status;
1358 struct sk_buff *skb_new = NULL;
1359 struct sk_buff *skb;
1360 ushort pkt_len;
1361 __u8 *data;
1362 int pkt_received = 0;
1363 struct bufdesc_ex *ebdp = NULL;
1364 bool vlan_packet_rcvd = false;
1365 u16 vlan_tag;
1366 int index = 0;
1367 bool is_copybreak;
1368 bool need_swap = id_entry->driver_data & FEC_QUIRK_SWAP_FRAME;
1369
1370 #ifdef CONFIG_M532x
1371 flush_cache_all();
1372 #endif
1373 queue_id = FEC_ENET_GET_QUQUE(queue_id);
1374 rxq = fep->rx_queue[queue_id];
1375
1376 /* First, grab all of the stats for the incoming packet.
1377 * These get messed up if we get called due to a busy condition.
1378 */
1379 bdp = rxq->cur_rx;
1380
1381 while (!((status = bdp->cbd_sc) & BD_ENET_RX_EMPTY)) {
1382
1383 if (pkt_received >= budget)
1384 break;
1385 pkt_received++;
1386
1387 /* Since we have allocated space to hold a complete frame,
1388 * the last indicator should be set.
1389 */
1390 if ((status & BD_ENET_RX_LAST) == 0)
1391 netdev_err(ndev, "rcv is not +last\n");
1392
1393
1394 /* Check for errors. */
1395 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO |
1396 BD_ENET_RX_CR | BD_ENET_RX_OV)) {
1397 ndev->stats.rx_errors++;
1398 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH)) {
1399 /* Frame too long or too short. */
1400 ndev->stats.rx_length_errors++;
1401 }
1402 if (status & BD_ENET_RX_NO) /* Frame alignment */
1403 ndev->stats.rx_frame_errors++;
1404 if (status & BD_ENET_RX_CR) /* CRC Error */
1405 ndev->stats.rx_crc_errors++;
1406 if (status & BD_ENET_RX_OV) /* FIFO overrun */
1407 ndev->stats.rx_fifo_errors++;
1408 }
1409
1410 /* Report late collisions as a frame error.
1411 * On this error, the BD is closed, but we don't know what we
1412 * have in the buffer. So, just drop this frame on the floor.
1413 */
1414 if (status & BD_ENET_RX_CL) {
1415 ndev->stats.rx_errors++;
1416 ndev->stats.rx_frame_errors++;
1417 goto rx_processing_done;
1418 }
1419
1420 /* Process the incoming frame. */
1421 ndev->stats.rx_packets++;
1422 pkt_len = bdp->cbd_datlen;
1423 ndev->stats.rx_bytes += pkt_len;
1424
1425 index = fec_enet_get_bd_index(rxq->rx_bd_base, bdp, fep);
1426 skb = rxq->rx_skbuff[index];
1427
1428 /* The packet length includes FCS, but we don't want to
1429 * include that when passing upstream as it messes up
1430 * bridging applications.
1431 */
1432 is_copybreak = fec_enet_copybreak(ndev, &skb, bdp, pkt_len - 4,
1433 need_swap);
1434 if (!is_copybreak) {
1435 skb_new = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE);
1436 if (unlikely(!skb_new)) {
1437 ndev->stats.rx_dropped++;
1438 goto rx_processing_done;
1439 }
1440 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
1441 FEC_ENET_RX_FRSIZE - fep->rx_align,
1442 DMA_FROM_DEVICE);
1443 }
1444
1445 prefetch(skb->data - NET_IP_ALIGN);
1446 skb_put(skb, pkt_len - 4);
1447 data = skb->data;
1448 if (!is_copybreak && need_swap)
1449 swap_buffer(data, pkt_len);
1450
1451 /* Extract the enhanced buffer descriptor */
1452 ebdp = NULL;
1453 if (fep->bufdesc_ex)
1454 ebdp = (struct bufdesc_ex *)bdp;
1455
1456 /* If this is a VLAN packet remove the VLAN Tag */
1457 vlan_packet_rcvd = false;
1458 if ((ndev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
1459 fep->bufdesc_ex && (ebdp->cbd_esc & BD_ENET_RX_VLAN)) {
1460 /* Push and remove the vlan tag */
1461 struct vlan_hdr *vlan_header =
1462 (struct vlan_hdr *) (data + ETH_HLEN);
1463 vlan_tag = ntohs(vlan_header->h_vlan_TCI);
1464
1465 vlan_packet_rcvd = true;
1466
1467 memmove(skb->data + VLAN_HLEN, data, ETH_ALEN * 2);
1468 skb_pull(skb, VLAN_HLEN);
1469 }
1470
1471 skb->protocol = eth_type_trans(skb, ndev);
1472
1473 /* Get receive timestamp from the skb */
1474 if (fep->hwts_rx_en && fep->bufdesc_ex)
1475 fec_enet_hwtstamp(fep, ebdp->ts,
1476 skb_hwtstamps(skb));
1477
1478 if (fep->bufdesc_ex &&
1479 (fep->csum_flags & FLAG_RX_CSUM_ENABLED)) {
1480 if (!(ebdp->cbd_esc & FLAG_RX_CSUM_ERROR)) {
1481 /* don't check it */
1482 skb->ip_summed = CHECKSUM_UNNECESSARY;
1483 } else {
1484 skb_checksum_none_assert(skb);
1485 }
1486 }
1487
1488 /* Handle received VLAN packets */
1489 if (vlan_packet_rcvd)
1490 __vlan_hwaccel_put_tag(skb,
1491 htons(ETH_P_8021Q),
1492 vlan_tag);
1493
1494 napi_gro_receive(&fep->napi, skb);
1495
1496 if (is_copybreak) {
1497 dma_sync_single_for_device(&fep->pdev->dev, bdp->cbd_bufaddr,
1498 FEC_ENET_RX_FRSIZE - fep->rx_align,
1499 DMA_FROM_DEVICE);
1500 } else {
1501 rxq->rx_skbuff[index] = skb_new;
1502 fec_enet_new_rxbdp(ndev, bdp, skb_new);
1503 }
1504
1505 rx_processing_done:
1506 /* Clear the status flags for this buffer */
1507 status &= ~BD_ENET_RX_STATS;
1508
1509 /* Mark the buffer empty */
1510 status |= BD_ENET_RX_EMPTY;
1511 bdp->cbd_sc = status;
1512
1513 if (fep->bufdesc_ex) {
1514 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
1515
1516 ebdp->cbd_esc = BD_ENET_RX_INT;
1517 ebdp->cbd_prot = 0;
1518 ebdp->cbd_bdu = 0;
1519 }
1520
1521 /* Update BD pointer to next entry */
1522 bdp = fec_enet_get_nextdesc(bdp, fep, queue_id);
1523
1524 /* Doing this here will keep the FEC running while we process
1525 * incoming frames. On a heavily loaded network, we should be
1526 * able to keep up at the expense of system resources.
1527 */
1528 writel(0, fep->hwp + FEC_R_DES_ACTIVE(queue_id));
1529 }
1530 rxq->cur_rx = bdp;
1531 return pkt_received;
1532 }
1533
1534 static int
fec_enet_rx(struct net_device * ndev,int budget)1535 fec_enet_rx(struct net_device *ndev, int budget)
1536 {
1537 int pkt_received = 0;
1538 u16 queue_id;
1539 struct fec_enet_private *fep = netdev_priv(ndev);
1540
1541 for_each_set_bit(queue_id, &fep->work_rx, FEC_ENET_MAX_RX_QS) {
1542 int ret;
1543
1544 ret = fec_enet_rx_queue(ndev,
1545 budget - pkt_received, queue_id);
1546
1547 if (ret < budget - pkt_received)
1548 clear_bit(queue_id, &fep->work_rx);
1549
1550 pkt_received += ret;
1551 }
1552 return pkt_received;
1553 }
1554
1555 static bool
fec_enet_collect_events(struct fec_enet_private * fep,uint int_events)1556 fec_enet_collect_events(struct fec_enet_private *fep, uint int_events)
1557 {
1558 if (int_events == 0)
1559 return false;
1560
1561 if (int_events & FEC_ENET_RXF)
1562 fep->work_rx |= (1 << 2);
1563 if (int_events & FEC_ENET_RXF_1)
1564 fep->work_rx |= (1 << 0);
1565 if (int_events & FEC_ENET_RXF_2)
1566 fep->work_rx |= (1 << 1);
1567
1568 if (int_events & FEC_ENET_TXF)
1569 fep->work_tx |= (1 << 2);
1570 if (int_events & FEC_ENET_TXF_1)
1571 fep->work_tx |= (1 << 0);
1572 if (int_events & FEC_ENET_TXF_2)
1573 fep->work_tx |= (1 << 1);
1574
1575 return true;
1576 }
1577
1578 static irqreturn_t
fec_enet_interrupt(int irq,void * dev_id)1579 fec_enet_interrupt(int irq, void *dev_id)
1580 {
1581 struct net_device *ndev = dev_id;
1582 struct fec_enet_private *fep = netdev_priv(ndev);
1583 const unsigned napi_mask = FEC_ENET_RXF | FEC_ENET_TXF;
1584 uint int_events;
1585 irqreturn_t ret = IRQ_NONE;
1586
1587 int_events = readl(fep->hwp + FEC_IEVENT);
1588 writel(int_events & ~napi_mask, fep->hwp + FEC_IEVENT);
1589 fec_enet_collect_events(fep, int_events);
1590
1591 if (int_events & napi_mask) {
1592 ret = IRQ_HANDLED;
1593
1594 /* Disable the NAPI interrupts */
1595 writel(FEC_ENET_MII, fep->hwp + FEC_IMASK);
1596 napi_schedule(&fep->napi);
1597 }
1598
1599 if (int_events & FEC_ENET_MII) {
1600 ret = IRQ_HANDLED;
1601 complete(&fep->mdio_done);
1602 }
1603
1604 if (fep->ptp_clock)
1605 fec_ptp_check_pps_event(fep);
1606
1607 return ret;
1608 }
1609
fec_enet_rx_napi(struct napi_struct * napi,int budget)1610 static int fec_enet_rx_napi(struct napi_struct *napi, int budget)
1611 {
1612 struct net_device *ndev = napi->dev;
1613 struct fec_enet_private *fep = netdev_priv(ndev);
1614 int pkts;
1615
1616 /*
1617 * Clear any pending transmit or receive interrupts before
1618 * processing the rings to avoid racing with the hardware.
1619 */
1620 writel(FEC_ENET_RXF | FEC_ENET_TXF, fep->hwp + FEC_IEVENT);
1621
1622 pkts = fec_enet_rx(ndev, budget);
1623
1624 fec_enet_tx(ndev);
1625
1626 if (pkts < budget) {
1627 napi_complete(napi);
1628 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
1629 }
1630 return pkts;
1631 }
1632
1633 /* ------------------------------------------------------------------------- */
fec_get_mac(struct net_device * ndev)1634 static void fec_get_mac(struct net_device *ndev)
1635 {
1636 struct fec_enet_private *fep = netdev_priv(ndev);
1637 struct fec_platform_data *pdata = dev_get_platdata(&fep->pdev->dev);
1638 unsigned char *iap, tmpaddr[ETH_ALEN];
1639
1640 /*
1641 * try to get mac address in following order:
1642 *
1643 * 1) module parameter via kernel command line in form
1644 * fec.macaddr=0x00,0x04,0x9f,0x01,0x30,0xe0
1645 */
1646 iap = macaddr;
1647
1648 /*
1649 * 2) from device tree data
1650 */
1651 if (!is_valid_ether_addr(iap)) {
1652 struct device_node *np = fep->pdev->dev.of_node;
1653 if (np) {
1654 const char *mac = of_get_mac_address(np);
1655 if (mac)
1656 iap = (unsigned char *) mac;
1657 }
1658 }
1659
1660 /*
1661 * 3) from flash or fuse (via platform data)
1662 */
1663 if (!is_valid_ether_addr(iap)) {
1664 #ifdef CONFIG_M5272
1665 if (FEC_FLASHMAC)
1666 iap = (unsigned char *)FEC_FLASHMAC;
1667 #else
1668 if (pdata)
1669 iap = (unsigned char *)&pdata->mac;
1670 #endif
1671 }
1672
1673 /*
1674 * 4) FEC mac registers set by bootloader
1675 */
1676 if (!is_valid_ether_addr(iap)) {
1677 *((__be32 *) &tmpaddr[0]) =
1678 cpu_to_be32(readl(fep->hwp + FEC_ADDR_LOW));
1679 *((__be16 *) &tmpaddr[4]) =
1680 cpu_to_be16(readl(fep->hwp + FEC_ADDR_HIGH) >> 16);
1681 iap = &tmpaddr[0];
1682 }
1683
1684 /*
1685 * 5) random mac address
1686 */
1687 if (!is_valid_ether_addr(iap)) {
1688 /* Report it and use a random ethernet address instead */
1689 netdev_err(ndev, "Invalid MAC address: %pM\n", iap);
1690 eth_hw_addr_random(ndev);
1691 netdev_info(ndev, "Using random MAC address: %pM\n",
1692 ndev->dev_addr);
1693 return;
1694 }
1695
1696 memcpy(ndev->dev_addr, iap, ETH_ALEN);
1697
1698 /* Adjust MAC if using macaddr */
1699 if (iap == macaddr)
1700 ndev->dev_addr[ETH_ALEN-1] = macaddr[ETH_ALEN-1] + fep->dev_id;
1701 }
1702
1703 /* ------------------------------------------------------------------------- */
1704
1705 /*
1706 * Phy section
1707 */
fec_enet_adjust_link(struct net_device * ndev)1708 static void fec_enet_adjust_link(struct net_device *ndev)
1709 {
1710 struct fec_enet_private *fep = netdev_priv(ndev);
1711 struct phy_device *phy_dev = fep->phy_dev;
1712 int status_change = 0;
1713
1714 /* Prevent a state halted on mii error */
1715 if (fep->mii_timeout && phy_dev->state == PHY_HALTED) {
1716 phy_dev->state = PHY_RESUMING;
1717 return;
1718 }
1719
1720 /*
1721 * If the netdev is down, or is going down, we're not interested
1722 * in link state events, so just mark our idea of the link as down
1723 * and ignore the event.
1724 */
1725 if (!netif_running(ndev) || !netif_device_present(ndev)) {
1726 fep->link = 0;
1727 } else if (phy_dev->link) {
1728 if (!fep->link) {
1729 fep->link = phy_dev->link;
1730 status_change = 1;
1731 }
1732
1733 if (fep->full_duplex != phy_dev->duplex) {
1734 fep->full_duplex = phy_dev->duplex;
1735 status_change = 1;
1736 }
1737
1738 if (phy_dev->speed != fep->speed) {
1739 fep->speed = phy_dev->speed;
1740 status_change = 1;
1741 }
1742
1743 /* if any of the above changed restart the FEC */
1744 if (status_change) {
1745 napi_disable(&fep->napi);
1746 netif_tx_lock_bh(ndev);
1747 fec_restart(ndev);
1748 netif_wake_queue(ndev);
1749 netif_tx_unlock_bh(ndev);
1750 napi_enable(&fep->napi);
1751 }
1752 } else {
1753 if (fep->link) {
1754 napi_disable(&fep->napi);
1755 netif_tx_lock_bh(ndev);
1756 fec_stop(ndev);
1757 netif_tx_unlock_bh(ndev);
1758 napi_enable(&fep->napi);
1759 fep->link = phy_dev->link;
1760 status_change = 1;
1761 }
1762 }
1763
1764 if (status_change)
1765 phy_print_status(phy_dev);
1766 }
1767
fec_enet_mdio_read(struct mii_bus * bus,int mii_id,int regnum)1768 static int fec_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
1769 {
1770 struct fec_enet_private *fep = bus->priv;
1771 unsigned long time_left;
1772
1773 fep->mii_timeout = 0;
1774 init_completion(&fep->mdio_done);
1775
1776 /* start a read op */
1777 writel(FEC_MMFR_ST | FEC_MMFR_OP_READ |
1778 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
1779 FEC_MMFR_TA, fep->hwp + FEC_MII_DATA);
1780
1781 /* wait for end of transfer */
1782 time_left = wait_for_completion_timeout(&fep->mdio_done,
1783 usecs_to_jiffies(FEC_MII_TIMEOUT));
1784 if (time_left == 0) {
1785 fep->mii_timeout = 1;
1786 netdev_err(fep->netdev, "MDIO read timeout\n");
1787 return -ETIMEDOUT;
1788 }
1789
1790 /* return value */
1791 return FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA));
1792 }
1793
fec_enet_mdio_write(struct mii_bus * bus,int mii_id,int regnum,u16 value)1794 static int fec_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
1795 u16 value)
1796 {
1797 struct fec_enet_private *fep = bus->priv;
1798 unsigned long time_left;
1799
1800 fep->mii_timeout = 0;
1801 init_completion(&fep->mdio_done);
1802
1803 /* start a write op */
1804 writel(FEC_MMFR_ST | FEC_MMFR_OP_WRITE |
1805 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
1806 FEC_MMFR_TA | FEC_MMFR_DATA(value),
1807 fep->hwp + FEC_MII_DATA);
1808
1809 /* wait for end of transfer */
1810 time_left = wait_for_completion_timeout(&fep->mdio_done,
1811 usecs_to_jiffies(FEC_MII_TIMEOUT));
1812 if (time_left == 0) {
1813 fep->mii_timeout = 1;
1814 netdev_err(fep->netdev, "MDIO write timeout\n");
1815 return -ETIMEDOUT;
1816 }
1817
1818 return 0;
1819 }
1820
fec_enet_clk_enable(struct net_device * ndev,bool enable)1821 static int fec_enet_clk_enable(struct net_device *ndev, bool enable)
1822 {
1823 struct fec_enet_private *fep = netdev_priv(ndev);
1824 int ret;
1825
1826 if (enable) {
1827 ret = clk_prepare_enable(fep->clk_ahb);
1828 if (ret)
1829 return ret;
1830 ret = clk_prepare_enable(fep->clk_ipg);
1831 if (ret)
1832 goto failed_clk_ipg;
1833 if (fep->clk_enet_out) {
1834 ret = clk_prepare_enable(fep->clk_enet_out);
1835 if (ret)
1836 goto failed_clk_enet_out;
1837 }
1838 if (fep->clk_ptp) {
1839 mutex_lock(&fep->ptp_clk_mutex);
1840 ret = clk_prepare_enable(fep->clk_ptp);
1841 if (ret) {
1842 mutex_unlock(&fep->ptp_clk_mutex);
1843 goto failed_clk_ptp;
1844 } else {
1845 fep->ptp_clk_on = true;
1846 }
1847 mutex_unlock(&fep->ptp_clk_mutex);
1848 }
1849 if (fep->clk_ref) {
1850 ret = clk_prepare_enable(fep->clk_ref);
1851 if (ret)
1852 goto failed_clk_ref;
1853 }
1854 } else {
1855 clk_disable_unprepare(fep->clk_ahb);
1856 clk_disable_unprepare(fep->clk_ipg);
1857 if (fep->clk_enet_out)
1858 clk_disable_unprepare(fep->clk_enet_out);
1859 if (fep->clk_ptp) {
1860 mutex_lock(&fep->ptp_clk_mutex);
1861 clk_disable_unprepare(fep->clk_ptp);
1862 fep->ptp_clk_on = false;
1863 mutex_unlock(&fep->ptp_clk_mutex);
1864 }
1865 if (fep->clk_ref)
1866 clk_disable_unprepare(fep->clk_ref);
1867 }
1868
1869 return 0;
1870
1871 failed_clk_ref:
1872 if (fep->clk_ref)
1873 clk_disable_unprepare(fep->clk_ref);
1874 failed_clk_ptp:
1875 if (fep->clk_enet_out)
1876 clk_disable_unprepare(fep->clk_enet_out);
1877 failed_clk_enet_out:
1878 clk_disable_unprepare(fep->clk_ipg);
1879 failed_clk_ipg:
1880 clk_disable_unprepare(fep->clk_ahb);
1881
1882 return ret;
1883 }
1884
fec_enet_mii_probe(struct net_device * ndev)1885 static int fec_enet_mii_probe(struct net_device *ndev)
1886 {
1887 struct fec_enet_private *fep = netdev_priv(ndev);
1888 const struct platform_device_id *id_entry =
1889 platform_get_device_id(fep->pdev);
1890 struct phy_device *phy_dev = NULL;
1891 char mdio_bus_id[MII_BUS_ID_SIZE];
1892 char phy_name[MII_BUS_ID_SIZE + 3];
1893 int phy_id;
1894 int dev_id = fep->dev_id;
1895
1896 fep->phy_dev = NULL;
1897
1898 if (fep->phy_node) {
1899 phy_dev = of_phy_connect(ndev, fep->phy_node,
1900 &fec_enet_adjust_link, 0,
1901 fep->phy_interface);
1902 } else {
1903 /* check for attached phy */
1904 for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) {
1905 if ((fep->mii_bus->phy_mask & (1 << phy_id)))
1906 continue;
1907 if (fep->mii_bus->phy_map[phy_id] == NULL)
1908 continue;
1909 if (fep->mii_bus->phy_map[phy_id]->phy_id == 0)
1910 continue;
1911 if (dev_id--)
1912 continue;
1913 strlcpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE);
1914 break;
1915 }
1916
1917 if (phy_id >= PHY_MAX_ADDR) {
1918 netdev_info(ndev, "no PHY, assuming direct connection to switch\n");
1919 strlcpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE);
1920 phy_id = 0;
1921 }
1922
1923 snprintf(phy_name, sizeof(phy_name),
1924 PHY_ID_FMT, mdio_bus_id, phy_id);
1925 phy_dev = phy_connect(ndev, phy_name, &fec_enet_adjust_link,
1926 fep->phy_interface);
1927 }
1928
1929 if (IS_ERR(phy_dev)) {
1930 netdev_err(ndev, "could not attach to PHY\n");
1931 return PTR_ERR(phy_dev);
1932 }
1933
1934 /* mask with MAC supported features */
1935 if (id_entry->driver_data & FEC_QUIRK_HAS_GBIT) {
1936 phy_dev->supported &= PHY_GBIT_FEATURES;
1937 phy_dev->supported &= ~SUPPORTED_1000baseT_Half;
1938 #if !defined(CONFIG_M5272)
1939 phy_dev->supported |= SUPPORTED_Pause;
1940 #endif
1941 }
1942 else
1943 phy_dev->supported &= PHY_BASIC_FEATURES;
1944
1945 phy_dev->advertising = phy_dev->supported;
1946
1947 fep->phy_dev = phy_dev;
1948 fep->link = 0;
1949 fep->full_duplex = 0;
1950
1951 netdev_info(ndev, "Freescale FEC PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n",
1952 fep->phy_dev->drv->name, dev_name(&fep->phy_dev->dev),
1953 fep->phy_dev->irq);
1954
1955 return 0;
1956 }
1957
fec_enet_mii_init(struct platform_device * pdev)1958 static int fec_enet_mii_init(struct platform_device *pdev)
1959 {
1960 static struct mii_bus *fec0_mii_bus;
1961 struct net_device *ndev = platform_get_drvdata(pdev);
1962 struct fec_enet_private *fep = netdev_priv(ndev);
1963 const struct platform_device_id *id_entry =
1964 platform_get_device_id(fep->pdev);
1965 struct device_node *node;
1966 int err = -ENXIO, i;
1967
1968 /*
1969 * The dual fec interfaces are not equivalent with enet-mac.
1970 * Here are the differences:
1971 *
1972 * - fec0 supports MII & RMII modes while fec1 only supports RMII
1973 * - fec0 acts as the 1588 time master while fec1 is slave
1974 * - external phys can only be configured by fec0
1975 *
1976 * That is to say fec1 can not work independently. It only works
1977 * when fec0 is working. The reason behind this design is that the
1978 * second interface is added primarily for Switch mode.
1979 *
1980 * Because of the last point above, both phys are attached on fec0
1981 * mdio interface in board design, and need to be configured by
1982 * fec0 mii_bus.
1983 */
1984 if ((id_entry->driver_data & FEC_QUIRK_ENET_MAC) && fep->dev_id > 0) {
1985 /* fec1 uses fec0 mii_bus */
1986 if (mii_cnt && fec0_mii_bus) {
1987 fep->mii_bus = fec0_mii_bus;
1988 mii_cnt++;
1989 return 0;
1990 }
1991 return -ENOENT;
1992 }
1993
1994 fep->mii_timeout = 0;
1995
1996 /*
1997 * Set MII speed to 2.5 MHz (= clk_get_rate() / 2 * phy_speed)
1998 *
1999 * The formula for FEC MDC is 'ref_freq / (MII_SPEED x 2)' while
2000 * for ENET-MAC is 'ref_freq / ((MII_SPEED + 1) x 2)'. The i.MX28
2001 * Reference Manual has an error on this, and gets fixed on i.MX6Q
2002 * document.
2003 */
2004 fep->phy_speed = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), 5000000);
2005 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC)
2006 fep->phy_speed--;
2007 fep->phy_speed <<= 1;
2008 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
2009
2010 fep->mii_bus = mdiobus_alloc();
2011 if (fep->mii_bus == NULL) {
2012 err = -ENOMEM;
2013 goto err_out;
2014 }
2015
2016 fep->mii_bus->name = "fec_enet_mii_bus";
2017 fep->mii_bus->read = fec_enet_mdio_read;
2018 fep->mii_bus->write = fec_enet_mdio_write;
2019 snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
2020 pdev->name, fep->dev_id + 1);
2021 fep->mii_bus->priv = fep;
2022 fep->mii_bus->parent = &pdev->dev;
2023
2024 fep->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL);
2025 if (!fep->mii_bus->irq) {
2026 err = -ENOMEM;
2027 goto err_out_free_mdiobus;
2028 }
2029
2030 for (i = 0; i < PHY_MAX_ADDR; i++)
2031 fep->mii_bus->irq[i] = PHY_POLL;
2032
2033 node = of_get_child_by_name(pdev->dev.of_node, "mdio");
2034 if (node) {
2035 err = of_mdiobus_register(fep->mii_bus, node);
2036 of_node_put(node);
2037 } else {
2038 err = mdiobus_register(fep->mii_bus);
2039 }
2040
2041 if (err)
2042 goto err_out_free_mdio_irq;
2043
2044 mii_cnt++;
2045
2046 /* save fec0 mii_bus */
2047 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC)
2048 fec0_mii_bus = fep->mii_bus;
2049
2050 return 0;
2051
2052 err_out_free_mdio_irq:
2053 kfree(fep->mii_bus->irq);
2054 err_out_free_mdiobus:
2055 mdiobus_free(fep->mii_bus);
2056 err_out:
2057 return err;
2058 }
2059
fec_enet_mii_remove(struct fec_enet_private * fep)2060 static void fec_enet_mii_remove(struct fec_enet_private *fep)
2061 {
2062 if (--mii_cnt == 0) {
2063 mdiobus_unregister(fep->mii_bus);
2064 kfree(fep->mii_bus->irq);
2065 mdiobus_free(fep->mii_bus);
2066 }
2067 }
2068
fec_enet_get_settings(struct net_device * ndev,struct ethtool_cmd * cmd)2069 static int fec_enet_get_settings(struct net_device *ndev,
2070 struct ethtool_cmd *cmd)
2071 {
2072 struct fec_enet_private *fep = netdev_priv(ndev);
2073 struct phy_device *phydev = fep->phy_dev;
2074
2075 if (!phydev)
2076 return -ENODEV;
2077
2078 return phy_ethtool_gset(phydev, cmd);
2079 }
2080
fec_enet_set_settings(struct net_device * ndev,struct ethtool_cmd * cmd)2081 static int fec_enet_set_settings(struct net_device *ndev,
2082 struct ethtool_cmd *cmd)
2083 {
2084 struct fec_enet_private *fep = netdev_priv(ndev);
2085 struct phy_device *phydev = fep->phy_dev;
2086
2087 if (!phydev)
2088 return -ENODEV;
2089
2090 return phy_ethtool_sset(phydev, cmd);
2091 }
2092
fec_enet_get_drvinfo(struct net_device * ndev,struct ethtool_drvinfo * info)2093 static void fec_enet_get_drvinfo(struct net_device *ndev,
2094 struct ethtool_drvinfo *info)
2095 {
2096 struct fec_enet_private *fep = netdev_priv(ndev);
2097
2098 strlcpy(info->driver, fep->pdev->dev.driver->name,
2099 sizeof(info->driver));
2100 strlcpy(info->version, "Revision: 1.0", sizeof(info->version));
2101 strlcpy(info->bus_info, dev_name(&ndev->dev), sizeof(info->bus_info));
2102 }
2103
fec_enet_get_ts_info(struct net_device * ndev,struct ethtool_ts_info * info)2104 static int fec_enet_get_ts_info(struct net_device *ndev,
2105 struct ethtool_ts_info *info)
2106 {
2107 struct fec_enet_private *fep = netdev_priv(ndev);
2108
2109 if (fep->bufdesc_ex) {
2110
2111 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
2112 SOF_TIMESTAMPING_RX_SOFTWARE |
2113 SOF_TIMESTAMPING_SOFTWARE |
2114 SOF_TIMESTAMPING_TX_HARDWARE |
2115 SOF_TIMESTAMPING_RX_HARDWARE |
2116 SOF_TIMESTAMPING_RAW_HARDWARE;
2117 if (fep->ptp_clock)
2118 info->phc_index = ptp_clock_index(fep->ptp_clock);
2119 else
2120 info->phc_index = -1;
2121
2122 info->tx_types = (1 << HWTSTAMP_TX_OFF) |
2123 (1 << HWTSTAMP_TX_ON);
2124
2125 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
2126 (1 << HWTSTAMP_FILTER_ALL);
2127 return 0;
2128 } else {
2129 return ethtool_op_get_ts_info(ndev, info);
2130 }
2131 }
2132
2133 #if !defined(CONFIG_M5272)
2134
fec_enet_get_pauseparam(struct net_device * ndev,struct ethtool_pauseparam * pause)2135 static void fec_enet_get_pauseparam(struct net_device *ndev,
2136 struct ethtool_pauseparam *pause)
2137 {
2138 struct fec_enet_private *fep = netdev_priv(ndev);
2139
2140 pause->autoneg = (fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) != 0;
2141 pause->tx_pause = (fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) != 0;
2142 pause->rx_pause = pause->tx_pause;
2143 }
2144
fec_enet_set_pauseparam(struct net_device * ndev,struct ethtool_pauseparam * pause)2145 static int fec_enet_set_pauseparam(struct net_device *ndev,
2146 struct ethtool_pauseparam *pause)
2147 {
2148 struct fec_enet_private *fep = netdev_priv(ndev);
2149
2150 if (!fep->phy_dev)
2151 return -ENODEV;
2152
2153 if (pause->tx_pause != pause->rx_pause) {
2154 netdev_info(ndev,
2155 "hardware only support enable/disable both tx and rx");
2156 return -EINVAL;
2157 }
2158
2159 fep->pause_flag = 0;
2160
2161 /* tx pause must be same as rx pause */
2162 fep->pause_flag |= pause->rx_pause ? FEC_PAUSE_FLAG_ENABLE : 0;
2163 fep->pause_flag |= pause->autoneg ? FEC_PAUSE_FLAG_AUTONEG : 0;
2164
2165 if (pause->rx_pause || pause->autoneg) {
2166 fep->phy_dev->supported |= ADVERTISED_Pause;
2167 fep->phy_dev->advertising |= ADVERTISED_Pause;
2168 } else {
2169 fep->phy_dev->supported &= ~ADVERTISED_Pause;
2170 fep->phy_dev->advertising &= ~ADVERTISED_Pause;
2171 }
2172
2173 if (pause->autoneg) {
2174 if (netif_running(ndev))
2175 fec_stop(ndev);
2176 phy_start_aneg(fep->phy_dev);
2177 }
2178 if (netif_running(ndev)) {
2179 napi_disable(&fep->napi);
2180 netif_tx_lock_bh(ndev);
2181 fec_restart(ndev);
2182 netif_wake_queue(ndev);
2183 netif_tx_unlock_bh(ndev);
2184 napi_enable(&fep->napi);
2185 }
2186
2187 return 0;
2188 }
2189
2190 static const struct fec_stat {
2191 char name[ETH_GSTRING_LEN];
2192 u16 offset;
2193 } fec_stats[] = {
2194 /* RMON TX */
2195 { "tx_dropped", RMON_T_DROP },
2196 { "tx_packets", RMON_T_PACKETS },
2197 { "tx_broadcast", RMON_T_BC_PKT },
2198 { "tx_multicast", RMON_T_MC_PKT },
2199 { "tx_crc_errors", RMON_T_CRC_ALIGN },
2200 { "tx_undersize", RMON_T_UNDERSIZE },
2201 { "tx_oversize", RMON_T_OVERSIZE },
2202 { "tx_fragment", RMON_T_FRAG },
2203 { "tx_jabber", RMON_T_JAB },
2204 { "tx_collision", RMON_T_COL },
2205 { "tx_64byte", RMON_T_P64 },
2206 { "tx_65to127byte", RMON_T_P65TO127 },
2207 { "tx_128to255byte", RMON_T_P128TO255 },
2208 { "tx_256to511byte", RMON_T_P256TO511 },
2209 { "tx_512to1023byte", RMON_T_P512TO1023 },
2210 { "tx_1024to2047byte", RMON_T_P1024TO2047 },
2211 { "tx_GTE2048byte", RMON_T_P_GTE2048 },
2212 { "tx_octets", RMON_T_OCTETS },
2213
2214 /* IEEE TX */
2215 { "IEEE_tx_drop", IEEE_T_DROP },
2216 { "IEEE_tx_frame_ok", IEEE_T_FRAME_OK },
2217 { "IEEE_tx_1col", IEEE_T_1COL },
2218 { "IEEE_tx_mcol", IEEE_T_MCOL },
2219 { "IEEE_tx_def", IEEE_T_DEF },
2220 { "IEEE_tx_lcol", IEEE_T_LCOL },
2221 { "IEEE_tx_excol", IEEE_T_EXCOL },
2222 { "IEEE_tx_macerr", IEEE_T_MACERR },
2223 { "IEEE_tx_cserr", IEEE_T_CSERR },
2224 { "IEEE_tx_sqe", IEEE_T_SQE },
2225 { "IEEE_tx_fdxfc", IEEE_T_FDXFC },
2226 { "IEEE_tx_octets_ok", IEEE_T_OCTETS_OK },
2227
2228 /* RMON RX */
2229 { "rx_packets", RMON_R_PACKETS },
2230 { "rx_broadcast", RMON_R_BC_PKT },
2231 { "rx_multicast", RMON_R_MC_PKT },
2232 { "rx_crc_errors", RMON_R_CRC_ALIGN },
2233 { "rx_undersize", RMON_R_UNDERSIZE },
2234 { "rx_oversize", RMON_R_OVERSIZE },
2235 { "rx_fragment", RMON_R_FRAG },
2236 { "rx_jabber", RMON_R_JAB },
2237 { "rx_64byte", RMON_R_P64 },
2238 { "rx_65to127byte", RMON_R_P65TO127 },
2239 { "rx_128to255byte", RMON_R_P128TO255 },
2240 { "rx_256to511byte", RMON_R_P256TO511 },
2241 { "rx_512to1023byte", RMON_R_P512TO1023 },
2242 { "rx_1024to2047byte", RMON_R_P1024TO2047 },
2243 { "rx_GTE2048byte", RMON_R_P_GTE2048 },
2244 { "rx_octets", RMON_R_OCTETS },
2245
2246 /* IEEE RX */
2247 { "IEEE_rx_drop", IEEE_R_DROP },
2248 { "IEEE_rx_frame_ok", IEEE_R_FRAME_OK },
2249 { "IEEE_rx_crc", IEEE_R_CRC },
2250 { "IEEE_rx_align", IEEE_R_ALIGN },
2251 { "IEEE_rx_macerr", IEEE_R_MACERR },
2252 { "IEEE_rx_fdxfc", IEEE_R_FDXFC },
2253 { "IEEE_rx_octets_ok", IEEE_R_OCTETS_OK },
2254 };
2255
fec_enet_get_ethtool_stats(struct net_device * dev,struct ethtool_stats * stats,u64 * data)2256 static void fec_enet_get_ethtool_stats(struct net_device *dev,
2257 struct ethtool_stats *stats, u64 *data)
2258 {
2259 struct fec_enet_private *fep = netdev_priv(dev);
2260 int i;
2261
2262 for (i = 0; i < ARRAY_SIZE(fec_stats); i++)
2263 data[i] = readl(fep->hwp + fec_stats[i].offset);
2264 }
2265
fec_enet_get_strings(struct net_device * netdev,u32 stringset,u8 * data)2266 static void fec_enet_get_strings(struct net_device *netdev,
2267 u32 stringset, u8 *data)
2268 {
2269 int i;
2270 switch (stringset) {
2271 case ETH_SS_STATS:
2272 for (i = 0; i < ARRAY_SIZE(fec_stats); i++)
2273 memcpy(data + i * ETH_GSTRING_LEN,
2274 fec_stats[i].name, ETH_GSTRING_LEN);
2275 break;
2276 }
2277 }
2278
fec_enet_get_sset_count(struct net_device * dev,int sset)2279 static int fec_enet_get_sset_count(struct net_device *dev, int sset)
2280 {
2281 switch (sset) {
2282 case ETH_SS_STATS:
2283 return ARRAY_SIZE(fec_stats);
2284 default:
2285 return -EOPNOTSUPP;
2286 }
2287 }
2288 #endif /* !defined(CONFIG_M5272) */
2289
fec_enet_nway_reset(struct net_device * dev)2290 static int fec_enet_nway_reset(struct net_device *dev)
2291 {
2292 struct fec_enet_private *fep = netdev_priv(dev);
2293 struct phy_device *phydev = fep->phy_dev;
2294
2295 if (!phydev)
2296 return -ENODEV;
2297
2298 return genphy_restart_aneg(phydev);
2299 }
2300
2301 /* ITR clock source is enet system clock (clk_ahb).
2302 * TCTT unit is cycle_ns * 64 cycle
2303 * So, the ICTT value = X us / (cycle_ns * 64)
2304 */
fec_enet_us_to_itr_clock(struct net_device * ndev,int us)2305 static int fec_enet_us_to_itr_clock(struct net_device *ndev, int us)
2306 {
2307 struct fec_enet_private *fep = netdev_priv(ndev);
2308
2309 return us * (fep->itr_clk_rate / 64000) / 1000;
2310 }
2311
2312 /* Set threshold for interrupt coalescing */
fec_enet_itr_coal_set(struct net_device * ndev)2313 static void fec_enet_itr_coal_set(struct net_device *ndev)
2314 {
2315 struct fec_enet_private *fep = netdev_priv(ndev);
2316 const struct platform_device_id *id_entry =
2317 platform_get_device_id(fep->pdev);
2318 int rx_itr, tx_itr;
2319
2320 if (!(id_entry->driver_data & FEC_QUIRK_HAS_AVB))
2321 return;
2322
2323 /* Must be greater than zero to avoid unpredictable behavior */
2324 if (!fep->rx_time_itr || !fep->rx_pkts_itr ||
2325 !fep->tx_time_itr || !fep->tx_pkts_itr)
2326 return;
2327
2328 /* Select enet system clock as Interrupt Coalescing
2329 * timer Clock Source
2330 */
2331 rx_itr = FEC_ITR_CLK_SEL;
2332 tx_itr = FEC_ITR_CLK_SEL;
2333
2334 /* set ICFT and ICTT */
2335 rx_itr |= FEC_ITR_ICFT(fep->rx_pkts_itr);
2336 rx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->rx_time_itr));
2337 tx_itr |= FEC_ITR_ICFT(fep->tx_pkts_itr);
2338 tx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->tx_time_itr));
2339
2340 rx_itr |= FEC_ITR_EN;
2341 tx_itr |= FEC_ITR_EN;
2342
2343 writel(tx_itr, fep->hwp + FEC_TXIC0);
2344 writel(rx_itr, fep->hwp + FEC_RXIC0);
2345 writel(tx_itr, fep->hwp + FEC_TXIC1);
2346 writel(rx_itr, fep->hwp + FEC_RXIC1);
2347 writel(tx_itr, fep->hwp + FEC_TXIC2);
2348 writel(rx_itr, fep->hwp + FEC_RXIC2);
2349 }
2350
2351 static int
fec_enet_get_coalesce(struct net_device * ndev,struct ethtool_coalesce * ec)2352 fec_enet_get_coalesce(struct net_device *ndev, struct ethtool_coalesce *ec)
2353 {
2354 struct fec_enet_private *fep = netdev_priv(ndev);
2355 const struct platform_device_id *id_entry =
2356 platform_get_device_id(fep->pdev);
2357
2358 if (!(id_entry->driver_data & FEC_QUIRK_HAS_AVB))
2359 return -EOPNOTSUPP;
2360
2361 ec->rx_coalesce_usecs = fep->rx_time_itr;
2362 ec->rx_max_coalesced_frames = fep->rx_pkts_itr;
2363
2364 ec->tx_coalesce_usecs = fep->tx_time_itr;
2365 ec->tx_max_coalesced_frames = fep->tx_pkts_itr;
2366
2367 return 0;
2368 }
2369
2370 static int
fec_enet_set_coalesce(struct net_device * ndev,struct ethtool_coalesce * ec)2371 fec_enet_set_coalesce(struct net_device *ndev, struct ethtool_coalesce *ec)
2372 {
2373 struct fec_enet_private *fep = netdev_priv(ndev);
2374 const struct platform_device_id *id_entry =
2375 platform_get_device_id(fep->pdev);
2376
2377 unsigned int cycle;
2378
2379 if (!(id_entry->driver_data & FEC_QUIRK_HAS_AVB))
2380 return -EOPNOTSUPP;
2381
2382 if (ec->rx_max_coalesced_frames > 255) {
2383 pr_err("Rx coalesced frames exceed hardware limiation");
2384 return -EINVAL;
2385 }
2386
2387 if (ec->tx_max_coalesced_frames > 255) {
2388 pr_err("Tx coalesced frame exceed hardware limiation");
2389 return -EINVAL;
2390 }
2391
2392 cycle = fec_enet_us_to_itr_clock(ndev, fep->rx_time_itr);
2393 if (cycle > 0xFFFF) {
2394 pr_err("Rx coalesed usec exceeed hardware limiation");
2395 return -EINVAL;
2396 }
2397
2398 cycle = fec_enet_us_to_itr_clock(ndev, fep->tx_time_itr);
2399 if (cycle > 0xFFFF) {
2400 pr_err("Rx coalesed usec exceeed hardware limiation");
2401 return -EINVAL;
2402 }
2403
2404 fep->rx_time_itr = ec->rx_coalesce_usecs;
2405 fep->rx_pkts_itr = ec->rx_max_coalesced_frames;
2406
2407 fep->tx_time_itr = ec->tx_coalesce_usecs;
2408 fep->tx_pkts_itr = ec->tx_max_coalesced_frames;
2409
2410 fec_enet_itr_coal_set(ndev);
2411
2412 return 0;
2413 }
2414
fec_enet_itr_coal_init(struct net_device * ndev)2415 static void fec_enet_itr_coal_init(struct net_device *ndev)
2416 {
2417 struct ethtool_coalesce ec;
2418
2419 ec.rx_coalesce_usecs = FEC_ITR_ICTT_DEFAULT;
2420 ec.rx_max_coalesced_frames = FEC_ITR_ICFT_DEFAULT;
2421
2422 ec.tx_coalesce_usecs = FEC_ITR_ICTT_DEFAULT;
2423 ec.tx_max_coalesced_frames = FEC_ITR_ICFT_DEFAULT;
2424
2425 fec_enet_set_coalesce(ndev, &ec);
2426 }
2427
fec_enet_get_tunable(struct net_device * netdev,const struct ethtool_tunable * tuna,void * data)2428 static int fec_enet_get_tunable(struct net_device *netdev,
2429 const struct ethtool_tunable *tuna,
2430 void *data)
2431 {
2432 struct fec_enet_private *fep = netdev_priv(netdev);
2433 int ret = 0;
2434
2435 switch (tuna->id) {
2436 case ETHTOOL_RX_COPYBREAK:
2437 *(u32 *)data = fep->rx_copybreak;
2438 break;
2439 default:
2440 ret = -EINVAL;
2441 break;
2442 }
2443
2444 return ret;
2445 }
2446
fec_enet_set_tunable(struct net_device * netdev,const struct ethtool_tunable * tuna,const void * data)2447 static int fec_enet_set_tunable(struct net_device *netdev,
2448 const struct ethtool_tunable *tuna,
2449 const void *data)
2450 {
2451 struct fec_enet_private *fep = netdev_priv(netdev);
2452 int ret = 0;
2453
2454 switch (tuna->id) {
2455 case ETHTOOL_RX_COPYBREAK:
2456 fep->rx_copybreak = *(u32 *)data;
2457 break;
2458 default:
2459 ret = -EINVAL;
2460 break;
2461 }
2462
2463 return ret;
2464 }
2465
2466 static const struct ethtool_ops fec_enet_ethtool_ops = {
2467 .get_settings = fec_enet_get_settings,
2468 .set_settings = fec_enet_set_settings,
2469 .get_drvinfo = fec_enet_get_drvinfo,
2470 .nway_reset = fec_enet_nway_reset,
2471 .get_link = ethtool_op_get_link,
2472 .get_coalesce = fec_enet_get_coalesce,
2473 .set_coalesce = fec_enet_set_coalesce,
2474 #ifndef CONFIG_M5272
2475 .get_pauseparam = fec_enet_get_pauseparam,
2476 .set_pauseparam = fec_enet_set_pauseparam,
2477 .get_strings = fec_enet_get_strings,
2478 .get_ethtool_stats = fec_enet_get_ethtool_stats,
2479 .get_sset_count = fec_enet_get_sset_count,
2480 #endif
2481 .get_ts_info = fec_enet_get_ts_info,
2482 .get_tunable = fec_enet_get_tunable,
2483 .set_tunable = fec_enet_set_tunable,
2484 };
2485
fec_enet_ioctl(struct net_device * ndev,struct ifreq * rq,int cmd)2486 static int fec_enet_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
2487 {
2488 struct fec_enet_private *fep = netdev_priv(ndev);
2489 struct phy_device *phydev = fep->phy_dev;
2490
2491 if (!netif_running(ndev))
2492 return -EINVAL;
2493
2494 if (!phydev)
2495 return -ENODEV;
2496
2497 if (fep->bufdesc_ex) {
2498 if (cmd == SIOCSHWTSTAMP)
2499 return fec_ptp_set(ndev, rq);
2500 if (cmd == SIOCGHWTSTAMP)
2501 return fec_ptp_get(ndev, rq);
2502 }
2503
2504 return phy_mii_ioctl(phydev, rq, cmd);
2505 }
2506
fec_enet_free_buffers(struct net_device * ndev)2507 static void fec_enet_free_buffers(struct net_device *ndev)
2508 {
2509 struct fec_enet_private *fep = netdev_priv(ndev);
2510 unsigned int i;
2511 struct sk_buff *skb;
2512 struct bufdesc *bdp;
2513 struct fec_enet_priv_tx_q *txq;
2514 struct fec_enet_priv_rx_q *rxq;
2515 unsigned int q;
2516
2517 for (q = 0; q < fep->num_rx_queues; q++) {
2518 rxq = fep->rx_queue[q];
2519 bdp = rxq->rx_bd_base;
2520 for (i = 0; i < rxq->rx_ring_size; i++) {
2521 skb = rxq->rx_skbuff[i];
2522 rxq->rx_skbuff[i] = NULL;
2523 if (skb) {
2524 dma_unmap_single(&fep->pdev->dev,
2525 bdp->cbd_bufaddr,
2526 FEC_ENET_RX_FRSIZE - fep->rx_align,
2527 DMA_FROM_DEVICE);
2528 dev_kfree_skb(skb);
2529 }
2530 bdp = fec_enet_get_nextdesc(bdp, fep, q);
2531 }
2532 }
2533
2534 for (q = 0; q < fep->num_tx_queues; q++) {
2535 txq = fep->tx_queue[q];
2536 bdp = txq->tx_bd_base;
2537 for (i = 0; i < txq->tx_ring_size; i++) {
2538 kfree(txq->tx_bounce[i]);
2539 txq->tx_bounce[i] = NULL;
2540 skb = txq->tx_skbuff[i];
2541 txq->tx_skbuff[i] = NULL;
2542 dev_kfree_skb(skb);
2543 }
2544 }
2545 }
2546
fec_enet_free_queue(struct net_device * ndev)2547 static void fec_enet_free_queue(struct net_device *ndev)
2548 {
2549 struct fec_enet_private *fep = netdev_priv(ndev);
2550 int i;
2551 struct fec_enet_priv_tx_q *txq;
2552
2553 for (i = 0; i < fep->num_tx_queues; i++)
2554 if (fep->tx_queue[i] && fep->tx_queue[i]->tso_hdrs) {
2555 txq = fep->tx_queue[i];
2556 dma_free_coherent(NULL,
2557 txq->tx_ring_size * TSO_HEADER_SIZE,
2558 txq->tso_hdrs,
2559 txq->tso_hdrs_dma);
2560 }
2561
2562 for (i = 0; i < fep->num_rx_queues; i++)
2563 if (fep->rx_queue[i])
2564 kfree(fep->rx_queue[i]);
2565
2566 for (i = 0; i < fep->num_tx_queues; i++)
2567 if (fep->tx_queue[i])
2568 kfree(fep->tx_queue[i]);
2569 }
2570
fec_enet_alloc_queue(struct net_device * ndev)2571 static int fec_enet_alloc_queue(struct net_device *ndev)
2572 {
2573 struct fec_enet_private *fep = netdev_priv(ndev);
2574 int i;
2575 int ret = 0;
2576 struct fec_enet_priv_tx_q *txq;
2577
2578 for (i = 0; i < fep->num_tx_queues; i++) {
2579 txq = kzalloc(sizeof(*txq), GFP_KERNEL);
2580 if (!txq) {
2581 ret = -ENOMEM;
2582 goto alloc_failed;
2583 }
2584
2585 fep->tx_queue[i] = txq;
2586 txq->tx_ring_size = TX_RING_SIZE;
2587 fep->total_tx_ring_size += fep->tx_queue[i]->tx_ring_size;
2588
2589 txq->tx_stop_threshold = FEC_MAX_SKB_DESCS;
2590 txq->tx_wake_threshold =
2591 (txq->tx_ring_size - txq->tx_stop_threshold) / 2;
2592
2593 txq->tso_hdrs = dma_alloc_coherent(NULL,
2594 txq->tx_ring_size * TSO_HEADER_SIZE,
2595 &txq->tso_hdrs_dma,
2596 GFP_KERNEL);
2597 if (!txq->tso_hdrs) {
2598 ret = -ENOMEM;
2599 goto alloc_failed;
2600 }
2601 }
2602
2603 for (i = 0; i < fep->num_rx_queues; i++) {
2604 fep->rx_queue[i] = kzalloc(sizeof(*fep->rx_queue[i]),
2605 GFP_KERNEL);
2606 if (!fep->rx_queue[i]) {
2607 ret = -ENOMEM;
2608 goto alloc_failed;
2609 }
2610
2611 fep->rx_queue[i]->rx_ring_size = RX_RING_SIZE;
2612 fep->total_rx_ring_size += fep->rx_queue[i]->rx_ring_size;
2613 }
2614 return ret;
2615
2616 alloc_failed:
2617 fec_enet_free_queue(ndev);
2618 return ret;
2619 }
2620
2621 static int
fec_enet_alloc_rxq_buffers(struct net_device * ndev,unsigned int queue)2622 fec_enet_alloc_rxq_buffers(struct net_device *ndev, unsigned int queue)
2623 {
2624 struct fec_enet_private *fep = netdev_priv(ndev);
2625 unsigned int i;
2626 struct sk_buff *skb;
2627 struct bufdesc *bdp;
2628 struct fec_enet_priv_rx_q *rxq;
2629
2630 rxq = fep->rx_queue[queue];
2631 bdp = rxq->rx_bd_base;
2632 for (i = 0; i < rxq->rx_ring_size; i++) {
2633 skb = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE);
2634 if (!skb)
2635 goto err_alloc;
2636
2637 if (fec_enet_new_rxbdp(ndev, bdp, skb)) {
2638 dev_kfree_skb(skb);
2639 goto err_alloc;
2640 }
2641
2642 rxq->rx_skbuff[i] = skb;
2643 bdp->cbd_sc = BD_ENET_RX_EMPTY;
2644
2645 if (fep->bufdesc_ex) {
2646 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
2647 ebdp->cbd_esc = BD_ENET_RX_INT;
2648 }
2649
2650 bdp = fec_enet_get_nextdesc(bdp, fep, queue);
2651 }
2652
2653 /* Set the last buffer to wrap. */
2654 bdp = fec_enet_get_prevdesc(bdp, fep, queue);
2655 bdp->cbd_sc |= BD_SC_WRAP;
2656 return 0;
2657
2658 err_alloc:
2659 fec_enet_free_buffers(ndev);
2660 return -ENOMEM;
2661 }
2662
2663 static int
fec_enet_alloc_txq_buffers(struct net_device * ndev,unsigned int queue)2664 fec_enet_alloc_txq_buffers(struct net_device *ndev, unsigned int queue)
2665 {
2666 struct fec_enet_private *fep = netdev_priv(ndev);
2667 unsigned int i;
2668 struct bufdesc *bdp;
2669 struct fec_enet_priv_tx_q *txq;
2670
2671 txq = fep->tx_queue[queue];
2672 bdp = txq->tx_bd_base;
2673 for (i = 0; i < txq->tx_ring_size; i++) {
2674 txq->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL);
2675 if (!txq->tx_bounce[i])
2676 goto err_alloc;
2677
2678 bdp->cbd_sc = 0;
2679 bdp->cbd_bufaddr = 0;
2680
2681 if (fep->bufdesc_ex) {
2682 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
2683 ebdp->cbd_esc = BD_ENET_TX_INT;
2684 }
2685
2686 bdp = fec_enet_get_nextdesc(bdp, fep, queue);
2687 }
2688
2689 /* Set the last buffer to wrap. */
2690 bdp = fec_enet_get_prevdesc(bdp, fep, queue);
2691 bdp->cbd_sc |= BD_SC_WRAP;
2692
2693 return 0;
2694
2695 err_alloc:
2696 fec_enet_free_buffers(ndev);
2697 return -ENOMEM;
2698 }
2699
fec_enet_alloc_buffers(struct net_device * ndev)2700 static int fec_enet_alloc_buffers(struct net_device *ndev)
2701 {
2702 struct fec_enet_private *fep = netdev_priv(ndev);
2703 unsigned int i;
2704
2705 for (i = 0; i < fep->num_rx_queues; i++)
2706 if (fec_enet_alloc_rxq_buffers(ndev, i))
2707 return -ENOMEM;
2708
2709 for (i = 0; i < fep->num_tx_queues; i++)
2710 if (fec_enet_alloc_txq_buffers(ndev, i))
2711 return -ENOMEM;
2712 return 0;
2713 }
2714
2715 static int
fec_enet_open(struct net_device * ndev)2716 fec_enet_open(struct net_device *ndev)
2717 {
2718 struct fec_enet_private *fep = netdev_priv(ndev);
2719 int ret;
2720
2721 pinctrl_pm_select_default_state(&fep->pdev->dev);
2722 ret = fec_enet_clk_enable(ndev, true);
2723 if (ret)
2724 return ret;
2725
2726 /* I should reset the ring buffers here, but I don't yet know
2727 * a simple way to do that.
2728 */
2729
2730 ret = fec_enet_alloc_buffers(ndev);
2731 if (ret)
2732 goto err_enet_alloc;
2733
2734 /* Probe and connect to PHY when open the interface */
2735 ret = fec_enet_mii_probe(ndev);
2736 if (ret)
2737 goto err_enet_mii_probe;
2738
2739 fec_restart(ndev);
2740 napi_enable(&fep->napi);
2741 phy_start(fep->phy_dev);
2742 netif_tx_start_all_queues(ndev);
2743
2744 return 0;
2745
2746 err_enet_mii_probe:
2747 fec_enet_free_buffers(ndev);
2748 err_enet_alloc:
2749 fec_enet_clk_enable(ndev, false);
2750 pinctrl_pm_select_sleep_state(&fep->pdev->dev);
2751 return ret;
2752 }
2753
2754 static int
fec_enet_close(struct net_device * ndev)2755 fec_enet_close(struct net_device *ndev)
2756 {
2757 struct fec_enet_private *fep = netdev_priv(ndev);
2758
2759 phy_stop(fep->phy_dev);
2760
2761 if (netif_device_present(ndev)) {
2762 napi_disable(&fep->napi);
2763 netif_tx_disable(ndev);
2764 fec_stop(ndev);
2765 }
2766
2767 phy_disconnect(fep->phy_dev);
2768 fep->phy_dev = NULL;
2769
2770 fec_enet_clk_enable(ndev, false);
2771 pinctrl_pm_select_sleep_state(&fep->pdev->dev);
2772 fec_enet_free_buffers(ndev);
2773
2774 return 0;
2775 }
2776
2777 /* Set or clear the multicast filter for this adaptor.
2778 * Skeleton taken from sunlance driver.
2779 * The CPM Ethernet implementation allows Multicast as well as individual
2780 * MAC address filtering. Some of the drivers check to make sure it is
2781 * a group multicast address, and discard those that are not. I guess I
2782 * will do the same for now, but just remove the test if you want
2783 * individual filtering as well (do the upper net layers want or support
2784 * this kind of feature?).
2785 */
2786
2787 #define HASH_BITS 6 /* #bits in hash */
2788 #define CRC32_POLY 0xEDB88320
2789
set_multicast_list(struct net_device * ndev)2790 static void set_multicast_list(struct net_device *ndev)
2791 {
2792 struct fec_enet_private *fep = netdev_priv(ndev);
2793 struct netdev_hw_addr *ha;
2794 unsigned int i, bit, data, crc, tmp;
2795 unsigned char hash;
2796 unsigned int hash_high = 0, hash_low = 0;
2797
2798 if (ndev->flags & IFF_PROMISC) {
2799 tmp = readl(fep->hwp + FEC_R_CNTRL);
2800 tmp |= 0x8;
2801 writel(tmp, fep->hwp + FEC_R_CNTRL);
2802 return;
2803 }
2804
2805 tmp = readl(fep->hwp + FEC_R_CNTRL);
2806 tmp &= ~0x8;
2807 writel(tmp, fep->hwp + FEC_R_CNTRL);
2808
2809 if (ndev->flags & IFF_ALLMULTI) {
2810 /* Catch all multicast addresses, so set the
2811 * filter to all 1's
2812 */
2813 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
2814 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
2815
2816 return;
2817 }
2818
2819 /* Add the addresses in hash register */
2820 netdev_for_each_mc_addr(ha, ndev) {
2821 /* calculate crc32 value of mac address */
2822 crc = 0xffffffff;
2823
2824 for (i = 0; i < ndev->addr_len; i++) {
2825 data = ha->addr[i];
2826 for (bit = 0; bit < 8; bit++, data >>= 1) {
2827 crc = (crc >> 1) ^
2828 (((crc ^ data) & 1) ? CRC32_POLY : 0);
2829 }
2830 }
2831
2832 /* only upper 6 bits (HASH_BITS) are used
2833 * which point to specific bit in he hash registers
2834 */
2835 hash = (crc >> (32 - HASH_BITS)) & 0x3f;
2836
2837 if (hash > 31)
2838 hash_high |= 1 << (hash - 32);
2839 else
2840 hash_low |= 1 << hash;
2841 }
2842
2843 writel(hash_high, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
2844 writel(hash_low, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
2845 }
2846
2847 /* Set a MAC change in hardware. */
2848 static int
fec_set_mac_address(struct net_device * ndev,void * p)2849 fec_set_mac_address(struct net_device *ndev, void *p)
2850 {
2851 struct fec_enet_private *fep = netdev_priv(ndev);
2852 struct sockaddr *addr = p;
2853
2854 if (addr) {
2855 if (!is_valid_ether_addr(addr->sa_data))
2856 return -EADDRNOTAVAIL;
2857 memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
2858 }
2859
2860 writel(ndev->dev_addr[3] | (ndev->dev_addr[2] << 8) |
2861 (ndev->dev_addr[1] << 16) | (ndev->dev_addr[0] << 24),
2862 fep->hwp + FEC_ADDR_LOW);
2863 writel((ndev->dev_addr[5] << 16) | (ndev->dev_addr[4] << 24),
2864 fep->hwp + FEC_ADDR_HIGH);
2865 return 0;
2866 }
2867
2868 #ifdef CONFIG_NET_POLL_CONTROLLER
2869 /**
2870 * fec_poll_controller - FEC Poll controller function
2871 * @dev: The FEC network adapter
2872 *
2873 * Polled functionality used by netconsole and others in non interrupt mode
2874 *
2875 */
fec_poll_controller(struct net_device * dev)2876 static void fec_poll_controller(struct net_device *dev)
2877 {
2878 int i;
2879 struct fec_enet_private *fep = netdev_priv(dev);
2880
2881 for (i = 0; i < FEC_IRQ_NUM; i++) {
2882 if (fep->irq[i] > 0) {
2883 disable_irq(fep->irq[i]);
2884 fec_enet_interrupt(fep->irq[i], dev);
2885 enable_irq(fep->irq[i]);
2886 }
2887 }
2888 }
2889 #endif
2890
2891 #define FEATURES_NEED_QUIESCE NETIF_F_RXCSUM
fec_enet_set_netdev_features(struct net_device * netdev,netdev_features_t features)2892 static inline void fec_enet_set_netdev_features(struct net_device *netdev,
2893 netdev_features_t features)
2894 {
2895 struct fec_enet_private *fep = netdev_priv(netdev);
2896 netdev_features_t changed = features ^ netdev->features;
2897
2898 netdev->features = features;
2899
2900 /* Receive checksum has been changed */
2901 if (changed & NETIF_F_RXCSUM) {
2902 if (features & NETIF_F_RXCSUM)
2903 fep->csum_flags |= FLAG_RX_CSUM_ENABLED;
2904 else
2905 fep->csum_flags &= ~FLAG_RX_CSUM_ENABLED;
2906 }
2907 }
2908
fec_set_features(struct net_device * netdev,netdev_features_t features)2909 static int fec_set_features(struct net_device *netdev,
2910 netdev_features_t features)
2911 {
2912 struct fec_enet_private *fep = netdev_priv(netdev);
2913 netdev_features_t changed = features ^ netdev->features;
2914
2915 if (netif_running(netdev) && changed & FEATURES_NEED_QUIESCE) {
2916 napi_disable(&fep->napi);
2917 netif_tx_lock_bh(netdev);
2918 fec_stop(netdev);
2919 fec_enet_set_netdev_features(netdev, features);
2920 fec_restart(netdev);
2921 netif_tx_wake_all_queues(netdev);
2922 netif_tx_unlock_bh(netdev);
2923 napi_enable(&fep->napi);
2924 } else {
2925 fec_enet_set_netdev_features(netdev, features);
2926 }
2927
2928 return 0;
2929 }
2930
2931 static const struct net_device_ops fec_netdev_ops = {
2932 .ndo_open = fec_enet_open,
2933 .ndo_stop = fec_enet_close,
2934 .ndo_start_xmit = fec_enet_start_xmit,
2935 .ndo_set_rx_mode = set_multicast_list,
2936 .ndo_change_mtu = eth_change_mtu,
2937 .ndo_validate_addr = eth_validate_addr,
2938 .ndo_tx_timeout = fec_timeout,
2939 .ndo_set_mac_address = fec_set_mac_address,
2940 .ndo_do_ioctl = fec_enet_ioctl,
2941 #ifdef CONFIG_NET_POLL_CONTROLLER
2942 .ndo_poll_controller = fec_poll_controller,
2943 #endif
2944 .ndo_set_features = fec_set_features,
2945 };
2946
2947 /*
2948 * XXX: We need to clean up on failure exits here.
2949 *
2950 */
fec_enet_init(struct net_device * ndev)2951 static int fec_enet_init(struct net_device *ndev)
2952 {
2953 struct fec_enet_private *fep = netdev_priv(ndev);
2954 const struct platform_device_id *id_entry =
2955 platform_get_device_id(fep->pdev);
2956 struct fec_enet_priv_tx_q *txq;
2957 struct fec_enet_priv_rx_q *rxq;
2958 struct bufdesc *cbd_base;
2959 dma_addr_t bd_dma;
2960 int bd_size;
2961 unsigned int i;
2962
2963 #if defined(CONFIG_ARM)
2964 fep->rx_align = 0xf;
2965 fep->tx_align = 0xf;
2966 #else
2967 fep->rx_align = 0x3;
2968 fep->tx_align = 0x3;
2969 #endif
2970
2971 fec_enet_alloc_queue(ndev);
2972
2973 if (fep->bufdesc_ex)
2974 fep->bufdesc_size = sizeof(struct bufdesc_ex);
2975 else
2976 fep->bufdesc_size = sizeof(struct bufdesc);
2977 bd_size = (fep->total_tx_ring_size + fep->total_rx_ring_size) *
2978 fep->bufdesc_size;
2979
2980 /* Allocate memory for buffer descriptors. */
2981 cbd_base = dma_alloc_coherent(NULL, bd_size, &bd_dma,
2982 GFP_KERNEL);
2983 if (!cbd_base) {
2984 return -ENOMEM;
2985 }
2986
2987 memset(cbd_base, 0, bd_size);
2988
2989 /* Get the Ethernet address */
2990 fec_get_mac(ndev);
2991 /* make sure MAC we just acquired is programmed into the hw */
2992 fec_set_mac_address(ndev, NULL);
2993
2994 /* Set receive and transmit descriptor base. */
2995 for (i = 0; i < fep->num_rx_queues; i++) {
2996 rxq = fep->rx_queue[i];
2997 rxq->index = i;
2998 rxq->rx_bd_base = (struct bufdesc *)cbd_base;
2999 rxq->bd_dma = bd_dma;
3000 if (fep->bufdesc_ex) {
3001 bd_dma += sizeof(struct bufdesc_ex) * rxq->rx_ring_size;
3002 cbd_base = (struct bufdesc *)
3003 (((struct bufdesc_ex *)cbd_base) + rxq->rx_ring_size);
3004 } else {
3005 bd_dma += sizeof(struct bufdesc) * rxq->rx_ring_size;
3006 cbd_base += rxq->rx_ring_size;
3007 }
3008 }
3009
3010 for (i = 0; i < fep->num_tx_queues; i++) {
3011 txq = fep->tx_queue[i];
3012 txq->index = i;
3013 txq->tx_bd_base = (struct bufdesc *)cbd_base;
3014 txq->bd_dma = bd_dma;
3015 if (fep->bufdesc_ex) {
3016 bd_dma += sizeof(struct bufdesc_ex) * txq->tx_ring_size;
3017 cbd_base = (struct bufdesc *)
3018 (((struct bufdesc_ex *)cbd_base) + txq->tx_ring_size);
3019 } else {
3020 bd_dma += sizeof(struct bufdesc) * txq->tx_ring_size;
3021 cbd_base += txq->tx_ring_size;
3022 }
3023 }
3024
3025
3026 /* The FEC Ethernet specific entries in the device structure */
3027 ndev->watchdog_timeo = TX_TIMEOUT;
3028 ndev->netdev_ops = &fec_netdev_ops;
3029 ndev->ethtool_ops = &fec_enet_ethtool_ops;
3030
3031 writel(FEC_RX_DISABLED_IMASK, fep->hwp + FEC_IMASK);
3032 netif_napi_add(ndev, &fep->napi, fec_enet_rx_napi, NAPI_POLL_WEIGHT);
3033
3034 if (id_entry->driver_data & FEC_QUIRK_HAS_VLAN)
3035 /* enable hw VLAN support */
3036 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX;
3037
3038 if (id_entry->driver_data & FEC_QUIRK_HAS_CSUM) {
3039 ndev->gso_max_segs = FEC_MAX_TSO_SEGS;
3040
3041 /* enable hw accelerator */
3042 ndev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM
3043 | NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_TSO);
3044 fep->csum_flags |= FLAG_RX_CSUM_ENABLED;
3045 }
3046
3047 if (id_entry->driver_data & FEC_QUIRK_HAS_AVB) {
3048 fep->tx_align = 0;
3049 fep->rx_align = 0x3f;
3050 }
3051
3052 ndev->hw_features = ndev->features;
3053
3054 fec_restart(ndev);
3055
3056 return 0;
3057 }
3058
3059 #ifdef CONFIG_OF
fec_reset_phy(struct platform_device * pdev)3060 static void fec_reset_phy(struct platform_device *pdev)
3061 {
3062 int err, phy_reset;
3063 int msec = 1;
3064 struct device_node *np = pdev->dev.of_node;
3065
3066 if (!np)
3067 return;
3068
3069 of_property_read_u32(np, "phy-reset-duration", &msec);
3070 /* A sane reset duration should not be longer than 1s */
3071 if (msec > 1000)
3072 msec = 1;
3073
3074 phy_reset = of_get_named_gpio(np, "phy-reset-gpios", 0);
3075 if (!gpio_is_valid(phy_reset))
3076 return;
3077
3078 err = devm_gpio_request_one(&pdev->dev, phy_reset,
3079 GPIOF_OUT_INIT_LOW, "phy-reset");
3080 if (err) {
3081 dev_err(&pdev->dev, "failed to get phy-reset-gpios: %d\n", err);
3082 return;
3083 }
3084 msleep(msec);
3085 gpio_set_value(phy_reset, 1);
3086 }
3087 #else /* CONFIG_OF */
fec_reset_phy(struct platform_device * pdev)3088 static void fec_reset_phy(struct platform_device *pdev)
3089 {
3090 /*
3091 * In case of platform probe, the reset has been done
3092 * by machine code.
3093 */
3094 }
3095 #endif /* CONFIG_OF */
3096
3097 static void
fec_enet_get_queue_num(struct platform_device * pdev,int * num_tx,int * num_rx)3098 fec_enet_get_queue_num(struct platform_device *pdev, int *num_tx, int *num_rx)
3099 {
3100 struct device_node *np = pdev->dev.of_node;
3101 int err;
3102
3103 *num_tx = *num_rx = 1;
3104
3105 if (!np || !of_device_is_available(np))
3106 return;
3107
3108 /* parse the num of tx and rx queues */
3109 err = of_property_read_u32(np, "fsl,num-tx-queues", num_tx);
3110 if (err)
3111 *num_tx = 1;
3112
3113 err = of_property_read_u32(np, "fsl,num-rx-queues", num_rx);
3114 if (err)
3115 *num_rx = 1;
3116
3117 if (*num_tx < 1 || *num_tx > FEC_ENET_MAX_TX_QS) {
3118 dev_warn(&pdev->dev, "Invalid num_tx(=%d), fall back to 1\n",
3119 *num_tx);
3120 *num_tx = 1;
3121 return;
3122 }
3123
3124 if (*num_rx < 1 || *num_rx > FEC_ENET_MAX_RX_QS) {
3125 dev_warn(&pdev->dev, "Invalid num_rx(=%d), fall back to 1\n",
3126 *num_rx);
3127 *num_rx = 1;
3128 return;
3129 }
3130
3131 }
3132
3133 static int
fec_probe(struct platform_device * pdev)3134 fec_probe(struct platform_device *pdev)
3135 {
3136 struct fec_enet_private *fep;
3137 struct fec_platform_data *pdata;
3138 struct net_device *ndev;
3139 int i, irq, ret = 0;
3140 struct resource *r;
3141 const struct of_device_id *of_id;
3142 static int dev_id;
3143 struct device_node *np = pdev->dev.of_node, *phy_node;
3144 int num_tx_qs;
3145 int num_rx_qs;
3146
3147 of_id = of_match_device(fec_dt_ids, &pdev->dev);
3148 if (of_id)
3149 pdev->id_entry = of_id->data;
3150
3151 fec_enet_get_queue_num(pdev, &num_tx_qs, &num_rx_qs);
3152
3153 /* Init network device */
3154 ndev = alloc_etherdev_mqs(sizeof(struct fec_enet_private),
3155 num_tx_qs, num_rx_qs);
3156 if (!ndev)
3157 return -ENOMEM;
3158
3159 SET_NETDEV_DEV(ndev, &pdev->dev);
3160
3161 /* setup board info structure */
3162 fep = netdev_priv(ndev);
3163
3164 fep->netdev = ndev;
3165 fep->num_rx_queues = num_rx_qs;
3166 fep->num_tx_queues = num_tx_qs;
3167
3168 #if !defined(CONFIG_M5272)
3169 /* default enable pause frame auto negotiation */
3170 if (pdev->id_entry &&
3171 (pdev->id_entry->driver_data & FEC_QUIRK_HAS_GBIT))
3172 fep->pause_flag |= FEC_PAUSE_FLAG_AUTONEG;
3173 #endif
3174
3175 /* Select default pin state */
3176 pinctrl_pm_select_default_state(&pdev->dev);
3177
3178 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3179 fep->hwp = devm_ioremap_resource(&pdev->dev, r);
3180 if (IS_ERR(fep->hwp)) {
3181 ret = PTR_ERR(fep->hwp);
3182 goto failed_ioremap;
3183 }
3184
3185 fep->pdev = pdev;
3186 fep->dev_id = dev_id++;
3187
3188 fep->bufdesc_ex = 0;
3189
3190 platform_set_drvdata(pdev, ndev);
3191
3192 phy_node = of_parse_phandle(np, "phy-handle", 0);
3193 if (!phy_node && of_phy_is_fixed_link(np)) {
3194 ret = of_phy_register_fixed_link(np);
3195 if (ret < 0) {
3196 dev_err(&pdev->dev,
3197 "broken fixed-link specification\n");
3198 goto failed_phy;
3199 }
3200 phy_node = of_node_get(np);
3201 }
3202 fep->phy_node = phy_node;
3203
3204 ret = of_get_phy_mode(pdev->dev.of_node);
3205 if (ret < 0) {
3206 pdata = dev_get_platdata(&pdev->dev);
3207 if (pdata)
3208 fep->phy_interface = pdata->phy;
3209 else
3210 fep->phy_interface = PHY_INTERFACE_MODE_MII;
3211 } else {
3212 fep->phy_interface = ret;
3213 }
3214
3215 fep->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
3216 if (IS_ERR(fep->clk_ipg)) {
3217 ret = PTR_ERR(fep->clk_ipg);
3218 goto failed_clk;
3219 }
3220
3221 fep->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
3222 if (IS_ERR(fep->clk_ahb)) {
3223 ret = PTR_ERR(fep->clk_ahb);
3224 goto failed_clk;
3225 }
3226
3227 fep->itr_clk_rate = clk_get_rate(fep->clk_ahb);
3228
3229 /* enet_out is optional, depends on board */
3230 fep->clk_enet_out = devm_clk_get(&pdev->dev, "enet_out");
3231 if (IS_ERR(fep->clk_enet_out))
3232 fep->clk_enet_out = NULL;
3233
3234 fep->ptp_clk_on = false;
3235 mutex_init(&fep->ptp_clk_mutex);
3236
3237 /* clk_ref is optional, depends on board */
3238 fep->clk_ref = devm_clk_get(&pdev->dev, "enet_clk_ref");
3239 if (IS_ERR(fep->clk_ref))
3240 fep->clk_ref = NULL;
3241
3242 fep->clk_ptp = devm_clk_get(&pdev->dev, "ptp");
3243 fep->bufdesc_ex =
3244 pdev->id_entry->driver_data & FEC_QUIRK_HAS_BUFDESC_EX;
3245 if (IS_ERR(fep->clk_ptp)) {
3246 fep->clk_ptp = NULL;
3247 fep->bufdesc_ex = 0;
3248 }
3249
3250 ret = fec_enet_clk_enable(ndev, true);
3251 if (ret)
3252 goto failed_clk;
3253
3254 fep->reg_phy = devm_regulator_get(&pdev->dev, "phy");
3255 if (!IS_ERR(fep->reg_phy)) {
3256 ret = regulator_enable(fep->reg_phy);
3257 if (ret) {
3258 dev_err(&pdev->dev,
3259 "Failed to enable phy regulator: %d\n", ret);
3260 goto failed_regulator;
3261 }
3262 } else {
3263 fep->reg_phy = NULL;
3264 }
3265
3266 fec_reset_phy(pdev);
3267
3268 if (fep->bufdesc_ex)
3269 fec_ptp_init(pdev);
3270
3271 ret = fec_enet_init(ndev);
3272 if (ret)
3273 goto failed_init;
3274
3275 for (i = 0; i < FEC_IRQ_NUM; i++) {
3276 irq = platform_get_irq(pdev, i);
3277 if (irq < 0) {
3278 if (i)
3279 break;
3280 ret = irq;
3281 goto failed_irq;
3282 }
3283 ret = devm_request_irq(&pdev->dev, irq, fec_enet_interrupt,
3284 0, pdev->name, ndev);
3285 if (ret)
3286 goto failed_irq;
3287 }
3288
3289 init_completion(&fep->mdio_done);
3290 ret = fec_enet_mii_init(pdev);
3291 if (ret)
3292 goto failed_mii_init;
3293
3294 /* Carrier starts down, phylib will bring it up */
3295 netif_carrier_off(ndev);
3296 fec_enet_clk_enable(ndev, false);
3297 pinctrl_pm_select_sleep_state(&pdev->dev);
3298
3299 ret = register_netdev(ndev);
3300 if (ret)
3301 goto failed_register;
3302
3303 if (fep->bufdesc_ex && fep->ptp_clock)
3304 netdev_info(ndev, "registered PHC device %d\n", fep->dev_id);
3305
3306 fep->rx_copybreak = COPYBREAK_DEFAULT;
3307 INIT_WORK(&fep->tx_timeout_work, fec_enet_timeout_work);
3308 return 0;
3309
3310 failed_register:
3311 fec_enet_mii_remove(fep);
3312 failed_mii_init:
3313 failed_irq:
3314 failed_init:
3315 if (fep->reg_phy)
3316 regulator_disable(fep->reg_phy);
3317 failed_regulator:
3318 fec_enet_clk_enable(ndev, false);
3319 failed_clk:
3320 failed_phy:
3321 of_node_put(phy_node);
3322 failed_ioremap:
3323 free_netdev(ndev);
3324
3325 return ret;
3326 }
3327
3328 static int
fec_drv_remove(struct platform_device * pdev)3329 fec_drv_remove(struct platform_device *pdev)
3330 {
3331 struct net_device *ndev = platform_get_drvdata(pdev);
3332 struct fec_enet_private *fep = netdev_priv(ndev);
3333
3334 cancel_delayed_work_sync(&fep->time_keep);
3335 cancel_work_sync(&fep->tx_timeout_work);
3336 unregister_netdev(ndev);
3337 fec_enet_mii_remove(fep);
3338 if (fep->reg_phy)
3339 regulator_disable(fep->reg_phy);
3340 if (fep->ptp_clock)
3341 ptp_clock_unregister(fep->ptp_clock);
3342 fec_enet_clk_enable(ndev, false);
3343 of_node_put(fep->phy_node);
3344 free_netdev(ndev);
3345
3346 return 0;
3347 }
3348
fec_suspend(struct device * dev)3349 static int __maybe_unused fec_suspend(struct device *dev)
3350 {
3351 struct net_device *ndev = dev_get_drvdata(dev);
3352 struct fec_enet_private *fep = netdev_priv(ndev);
3353
3354 rtnl_lock();
3355 if (netif_running(ndev)) {
3356 phy_stop(fep->phy_dev);
3357 napi_disable(&fep->napi);
3358 netif_tx_lock_bh(ndev);
3359 netif_device_detach(ndev);
3360 netif_tx_unlock_bh(ndev);
3361 fec_stop(ndev);
3362 fec_enet_clk_enable(ndev, false);
3363 pinctrl_pm_select_sleep_state(&fep->pdev->dev);
3364 }
3365 rtnl_unlock();
3366
3367 if (fep->reg_phy)
3368 regulator_disable(fep->reg_phy);
3369
3370 return 0;
3371 }
3372
fec_resume(struct device * dev)3373 static int __maybe_unused fec_resume(struct device *dev)
3374 {
3375 struct net_device *ndev = dev_get_drvdata(dev);
3376 struct fec_enet_private *fep = netdev_priv(ndev);
3377 int ret;
3378
3379 if (fep->reg_phy) {
3380 ret = regulator_enable(fep->reg_phy);
3381 if (ret)
3382 return ret;
3383 }
3384
3385 rtnl_lock();
3386 if (netif_running(ndev)) {
3387 pinctrl_pm_select_default_state(&fep->pdev->dev);
3388 ret = fec_enet_clk_enable(ndev, true);
3389 if (ret) {
3390 rtnl_unlock();
3391 goto failed_clk;
3392 }
3393 fec_restart(ndev);
3394 netif_tx_lock_bh(ndev);
3395 netif_device_attach(ndev);
3396 netif_tx_unlock_bh(ndev);
3397 napi_enable(&fep->napi);
3398 phy_start(fep->phy_dev);
3399 }
3400 rtnl_unlock();
3401
3402 return 0;
3403
3404 failed_clk:
3405 if (fep->reg_phy)
3406 regulator_disable(fep->reg_phy);
3407 return ret;
3408 }
3409
3410 static SIMPLE_DEV_PM_OPS(fec_pm_ops, fec_suspend, fec_resume);
3411
3412 static struct platform_driver fec_driver = {
3413 .driver = {
3414 .name = DRIVER_NAME,
3415 .owner = THIS_MODULE,
3416 .pm = &fec_pm_ops,
3417 .of_match_table = fec_dt_ids,
3418 },
3419 .id_table = fec_devtype,
3420 .probe = fec_probe,
3421 .remove = fec_drv_remove,
3422 };
3423
3424 module_platform_driver(fec_driver);
3425
3426 MODULE_ALIAS("platform:"DRIVER_NAME);
3427 MODULE_LICENSE("GPL");
3428