1 /* Intel PRO/1000 Linux driver
2 * Copyright(c) 1999 - 2014 Intel Corporation.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * The full GNU General Public License is included in this distribution in
14 * the file called "COPYING".
15 *
16 * Contact Information:
17 * Linux NICS <linux.nics@intel.com>
18 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
19 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
20 */
21
22 /* 82562G 10/100 Network Connection
23 * 82562G-2 10/100 Network Connection
24 * 82562GT 10/100 Network Connection
25 * 82562GT-2 10/100 Network Connection
26 * 82562V 10/100 Network Connection
27 * 82562V-2 10/100 Network Connection
28 * 82566DC-2 Gigabit Network Connection
29 * 82566DC Gigabit Network Connection
30 * 82566DM-2 Gigabit Network Connection
31 * 82566DM Gigabit Network Connection
32 * 82566MC Gigabit Network Connection
33 * 82566MM Gigabit Network Connection
34 * 82567LM Gigabit Network Connection
35 * 82567LF Gigabit Network Connection
36 * 82567V Gigabit Network Connection
37 * 82567LM-2 Gigabit Network Connection
38 * 82567LF-2 Gigabit Network Connection
39 * 82567V-2 Gigabit Network Connection
40 * 82567LF-3 Gigabit Network Connection
41 * 82567LM-3 Gigabit Network Connection
42 * 82567LM-4 Gigabit Network Connection
43 * 82577LM Gigabit Network Connection
44 * 82577LC Gigabit Network Connection
45 * 82578DM Gigabit Network Connection
46 * 82578DC Gigabit Network Connection
47 * 82579LM Gigabit Network Connection
48 * 82579V Gigabit Network Connection
49 * Ethernet Connection I217-LM
50 * Ethernet Connection I217-V
51 * Ethernet Connection I218-V
52 * Ethernet Connection I218-LM
53 * Ethernet Connection (2) I218-LM
54 * Ethernet Connection (2) I218-V
55 * Ethernet Connection (3) I218-LM
56 * Ethernet Connection (3) I218-V
57 */
58
59 #include "e1000.h"
60
61 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
62 /* Offset 04h HSFSTS */
63 union ich8_hws_flash_status {
64 struct ich8_hsfsts {
65 u16 flcdone:1; /* bit 0 Flash Cycle Done */
66 u16 flcerr:1; /* bit 1 Flash Cycle Error */
67 u16 dael:1; /* bit 2 Direct Access error Log */
68 u16 berasesz:2; /* bit 4:3 Sector Erase Size */
69 u16 flcinprog:1; /* bit 5 flash cycle in Progress */
70 u16 reserved1:2; /* bit 13:6 Reserved */
71 u16 reserved2:6; /* bit 13:6 Reserved */
72 u16 fldesvalid:1; /* bit 14 Flash Descriptor Valid */
73 u16 flockdn:1; /* bit 15 Flash Config Lock-Down */
74 } hsf_status;
75 u16 regval;
76 };
77
78 /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
79 /* Offset 06h FLCTL */
80 union ich8_hws_flash_ctrl {
81 struct ich8_hsflctl {
82 u16 flcgo:1; /* 0 Flash Cycle Go */
83 u16 flcycle:2; /* 2:1 Flash Cycle */
84 u16 reserved:5; /* 7:3 Reserved */
85 u16 fldbcount:2; /* 9:8 Flash Data Byte Count */
86 u16 flockdn:6; /* 15:10 Reserved */
87 } hsf_ctrl;
88 u16 regval;
89 };
90
91 /* ICH Flash Region Access Permissions */
92 union ich8_hws_flash_regacc {
93 struct ich8_flracc {
94 u32 grra:8; /* 0:7 GbE region Read Access */
95 u32 grwa:8; /* 8:15 GbE region Write Access */
96 u32 gmrag:8; /* 23:16 GbE Master Read Access Grant */
97 u32 gmwag:8; /* 31:24 GbE Master Write Access Grant */
98 } hsf_flregacc;
99 u16 regval;
100 };
101
102 /* ICH Flash Protected Region */
103 union ich8_flash_protected_range {
104 struct ich8_pr {
105 u32 base:13; /* 0:12 Protected Range Base */
106 u32 reserved1:2; /* 13:14 Reserved */
107 u32 rpe:1; /* 15 Read Protection Enable */
108 u32 limit:13; /* 16:28 Protected Range Limit */
109 u32 reserved2:2; /* 29:30 Reserved */
110 u32 wpe:1; /* 31 Write Protection Enable */
111 } range;
112 u32 regval;
113 };
114
115 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
116 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
117 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
118 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
119 u32 offset, u8 byte);
120 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
121 u8 *data);
122 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
123 u16 *data);
124 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
125 u8 size, u16 *data);
126 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
127 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
128 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw);
129 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw);
130 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);
131 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw);
132 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw);
133 static s32 e1000_led_on_pchlan(struct e1000_hw *hw);
134 static s32 e1000_led_off_pchlan(struct e1000_hw *hw);
135 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);
136 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);
137 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw);
138 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);
139 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw);
140 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw);
141 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw);
142 static int e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index);
143 static int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index);
144 static u32 e1000_rar_get_count_pch_lpt(struct e1000_hw *hw);
145 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw);
146 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate);
147 static s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force);
148 static s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw);
149 static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state);
150
__er16flash(struct e1000_hw * hw,unsigned long reg)151 static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg)
152 {
153 return readw(hw->flash_address + reg);
154 }
155
__er32flash(struct e1000_hw * hw,unsigned long reg)156 static inline u32 __er32flash(struct e1000_hw *hw, unsigned long reg)
157 {
158 return readl(hw->flash_address + reg);
159 }
160
__ew16flash(struct e1000_hw * hw,unsigned long reg,u16 val)161 static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val)
162 {
163 writew(val, hw->flash_address + reg);
164 }
165
__ew32flash(struct e1000_hw * hw,unsigned long reg,u32 val)166 static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val)
167 {
168 writel(val, hw->flash_address + reg);
169 }
170
171 #define er16flash(reg) __er16flash(hw, (reg))
172 #define er32flash(reg) __er32flash(hw, (reg))
173 #define ew16flash(reg, val) __ew16flash(hw, (reg), (val))
174 #define ew32flash(reg, val) __ew32flash(hw, (reg), (val))
175
176 /**
177 * e1000_phy_is_accessible_pchlan - Check if able to access PHY registers
178 * @hw: pointer to the HW structure
179 *
180 * Test access to the PHY registers by reading the PHY ID registers. If
181 * the PHY ID is already known (e.g. resume path) compare it with known ID,
182 * otherwise assume the read PHY ID is correct if it is valid.
183 *
184 * Assumes the sw/fw/hw semaphore is already acquired.
185 **/
e1000_phy_is_accessible_pchlan(struct e1000_hw * hw)186 static bool e1000_phy_is_accessible_pchlan(struct e1000_hw *hw)
187 {
188 u16 phy_reg = 0;
189 u32 phy_id = 0;
190 s32 ret_val = 0;
191 u16 retry_count;
192 u32 mac_reg = 0;
193
194 for (retry_count = 0; retry_count < 2; retry_count++) {
195 ret_val = e1e_rphy_locked(hw, MII_PHYSID1, &phy_reg);
196 if (ret_val || (phy_reg == 0xFFFF))
197 continue;
198 phy_id = (u32)(phy_reg << 16);
199
200 ret_val = e1e_rphy_locked(hw, MII_PHYSID2, &phy_reg);
201 if (ret_val || (phy_reg == 0xFFFF)) {
202 phy_id = 0;
203 continue;
204 }
205 phy_id |= (u32)(phy_reg & PHY_REVISION_MASK);
206 break;
207 }
208
209 if (hw->phy.id) {
210 if (hw->phy.id == phy_id)
211 goto out;
212 } else if (phy_id) {
213 hw->phy.id = phy_id;
214 hw->phy.revision = (u32)(phy_reg & ~PHY_REVISION_MASK);
215 goto out;
216 }
217
218 /* In case the PHY needs to be in mdio slow mode,
219 * set slow mode and try to get the PHY id again.
220 */
221 if (hw->mac.type < e1000_pch_lpt) {
222 hw->phy.ops.release(hw);
223 ret_val = e1000_set_mdio_slow_mode_hv(hw);
224 if (!ret_val)
225 ret_val = e1000e_get_phy_id(hw);
226 hw->phy.ops.acquire(hw);
227 }
228
229 if (ret_val)
230 return false;
231 out:
232 if (hw->mac.type == e1000_pch_lpt) {
233 /* Unforce SMBus mode in PHY */
234 e1e_rphy_locked(hw, CV_SMB_CTRL, &phy_reg);
235 phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
236 e1e_wphy_locked(hw, CV_SMB_CTRL, phy_reg);
237
238 /* Unforce SMBus mode in MAC */
239 mac_reg = er32(CTRL_EXT);
240 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
241 ew32(CTRL_EXT, mac_reg);
242 }
243
244 return true;
245 }
246
247 /**
248 * e1000_toggle_lanphypc_pch_lpt - toggle the LANPHYPC pin value
249 * @hw: pointer to the HW structure
250 *
251 * Toggling the LANPHYPC pin value fully power-cycles the PHY and is
252 * used to reset the PHY to a quiescent state when necessary.
253 **/
e1000_toggle_lanphypc_pch_lpt(struct e1000_hw * hw)254 static void e1000_toggle_lanphypc_pch_lpt(struct e1000_hw *hw)
255 {
256 u32 mac_reg;
257
258 /* Set Phy Config Counter to 50msec */
259 mac_reg = er32(FEXTNVM3);
260 mac_reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
261 mac_reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
262 ew32(FEXTNVM3, mac_reg);
263
264 /* Toggle LANPHYPC Value bit */
265 mac_reg = er32(CTRL);
266 mac_reg |= E1000_CTRL_LANPHYPC_OVERRIDE;
267 mac_reg &= ~E1000_CTRL_LANPHYPC_VALUE;
268 ew32(CTRL, mac_reg);
269 e1e_flush();
270 usleep_range(10, 20);
271 mac_reg &= ~E1000_CTRL_LANPHYPC_OVERRIDE;
272 ew32(CTRL, mac_reg);
273 e1e_flush();
274
275 if (hw->mac.type < e1000_pch_lpt) {
276 msleep(50);
277 } else {
278 u16 count = 20;
279
280 do {
281 usleep_range(5000, 10000);
282 } while (!(er32(CTRL_EXT) & E1000_CTRL_EXT_LPCD) && count--);
283
284 msleep(30);
285 }
286 }
287
288 /**
289 * e1000_init_phy_workarounds_pchlan - PHY initialization workarounds
290 * @hw: pointer to the HW structure
291 *
292 * Workarounds/flow necessary for PHY initialization during driver load
293 * and resume paths.
294 **/
e1000_init_phy_workarounds_pchlan(struct e1000_hw * hw)295 static s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw)
296 {
297 struct e1000_adapter *adapter = hw->adapter;
298 u32 mac_reg, fwsm = er32(FWSM);
299 s32 ret_val;
300
301 /* Gate automatic PHY configuration by hardware on managed and
302 * non-managed 82579 and newer adapters.
303 */
304 e1000_gate_hw_phy_config_ich8lan(hw, true);
305
306 /* It is not possible to be certain of the current state of ULP
307 * so forcibly disable it.
308 */
309 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_unknown;
310 e1000_disable_ulp_lpt_lp(hw, true);
311
312 ret_val = hw->phy.ops.acquire(hw);
313 if (ret_val) {
314 e_dbg("Failed to initialize PHY flow\n");
315 goto out;
316 }
317
318 /* The MAC-PHY interconnect may be in SMBus mode. If the PHY is
319 * inaccessible and resetting the PHY is not blocked, toggle the
320 * LANPHYPC Value bit to force the interconnect to PCIe mode.
321 */
322 switch (hw->mac.type) {
323 case e1000_pch_lpt:
324 if (e1000_phy_is_accessible_pchlan(hw))
325 break;
326
327 /* Before toggling LANPHYPC, see if PHY is accessible by
328 * forcing MAC to SMBus mode first.
329 */
330 mac_reg = er32(CTRL_EXT);
331 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
332 ew32(CTRL_EXT, mac_reg);
333
334 /* Wait 50 milliseconds for MAC to finish any retries
335 * that it might be trying to perform from previous
336 * attempts to acknowledge any phy read requests.
337 */
338 msleep(50);
339
340 /* fall-through */
341 case e1000_pch2lan:
342 if (e1000_phy_is_accessible_pchlan(hw))
343 break;
344
345 /* fall-through */
346 case e1000_pchlan:
347 if ((hw->mac.type == e1000_pchlan) &&
348 (fwsm & E1000_ICH_FWSM_FW_VALID))
349 break;
350
351 if (hw->phy.ops.check_reset_block(hw)) {
352 e_dbg("Required LANPHYPC toggle blocked by ME\n");
353 ret_val = -E1000_ERR_PHY;
354 break;
355 }
356
357 /* Toggle LANPHYPC Value bit */
358 e1000_toggle_lanphypc_pch_lpt(hw);
359 if (hw->mac.type >= e1000_pch_lpt) {
360 if (e1000_phy_is_accessible_pchlan(hw))
361 break;
362
363 /* Toggling LANPHYPC brings the PHY out of SMBus mode
364 * so ensure that the MAC is also out of SMBus mode
365 */
366 mac_reg = er32(CTRL_EXT);
367 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
368 ew32(CTRL_EXT, mac_reg);
369
370 if (e1000_phy_is_accessible_pchlan(hw))
371 break;
372
373 ret_val = -E1000_ERR_PHY;
374 }
375 break;
376 default:
377 break;
378 }
379
380 hw->phy.ops.release(hw);
381 if (!ret_val) {
382
383 /* Check to see if able to reset PHY. Print error if not */
384 if (hw->phy.ops.check_reset_block(hw)) {
385 e_err("Reset blocked by ME\n");
386 goto out;
387 }
388
389 /* Reset the PHY before any access to it. Doing so, ensures
390 * that the PHY is in a known good state before we read/write
391 * PHY registers. The generic reset is sufficient here,
392 * because we haven't determined the PHY type yet.
393 */
394 ret_val = e1000e_phy_hw_reset_generic(hw);
395 if (ret_val)
396 goto out;
397
398 /* On a successful reset, possibly need to wait for the PHY
399 * to quiesce to an accessible state before returning control
400 * to the calling function. If the PHY does not quiesce, then
401 * return E1000E_BLK_PHY_RESET, as this is the condition that
402 * the PHY is in.
403 */
404 ret_val = hw->phy.ops.check_reset_block(hw);
405 if (ret_val)
406 e_err("ME blocked access to PHY after reset\n");
407 }
408
409 out:
410 /* Ungate automatic PHY configuration on non-managed 82579 */
411 if ((hw->mac.type == e1000_pch2lan) &&
412 !(fwsm & E1000_ICH_FWSM_FW_VALID)) {
413 usleep_range(10000, 20000);
414 e1000_gate_hw_phy_config_ich8lan(hw, false);
415 }
416
417 return ret_val;
418 }
419
420 /**
421 * e1000_init_phy_params_pchlan - Initialize PHY function pointers
422 * @hw: pointer to the HW structure
423 *
424 * Initialize family-specific PHY parameters and function pointers.
425 **/
e1000_init_phy_params_pchlan(struct e1000_hw * hw)426 static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
427 {
428 struct e1000_phy_info *phy = &hw->phy;
429 s32 ret_val;
430
431 phy->addr = 1;
432 phy->reset_delay_us = 100;
433
434 phy->ops.set_page = e1000_set_page_igp;
435 phy->ops.read_reg = e1000_read_phy_reg_hv;
436 phy->ops.read_reg_locked = e1000_read_phy_reg_hv_locked;
437 phy->ops.read_reg_page = e1000_read_phy_reg_page_hv;
438 phy->ops.set_d0_lplu_state = e1000_set_lplu_state_pchlan;
439 phy->ops.set_d3_lplu_state = e1000_set_lplu_state_pchlan;
440 phy->ops.write_reg = e1000_write_phy_reg_hv;
441 phy->ops.write_reg_locked = e1000_write_phy_reg_hv_locked;
442 phy->ops.write_reg_page = e1000_write_phy_reg_page_hv;
443 phy->ops.power_up = e1000_power_up_phy_copper;
444 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
445 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
446
447 phy->id = e1000_phy_unknown;
448
449 ret_val = e1000_init_phy_workarounds_pchlan(hw);
450 if (ret_val)
451 return ret_val;
452
453 if (phy->id == e1000_phy_unknown)
454 switch (hw->mac.type) {
455 default:
456 ret_val = e1000e_get_phy_id(hw);
457 if (ret_val)
458 return ret_val;
459 if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK))
460 break;
461 /* fall-through */
462 case e1000_pch2lan:
463 case e1000_pch_lpt:
464 /* In case the PHY needs to be in mdio slow mode,
465 * set slow mode and try to get the PHY id again.
466 */
467 ret_val = e1000_set_mdio_slow_mode_hv(hw);
468 if (ret_val)
469 return ret_val;
470 ret_val = e1000e_get_phy_id(hw);
471 if (ret_val)
472 return ret_val;
473 break;
474 }
475 phy->type = e1000e_get_phy_type_from_id(phy->id);
476
477 switch (phy->type) {
478 case e1000_phy_82577:
479 case e1000_phy_82579:
480 case e1000_phy_i217:
481 phy->ops.check_polarity = e1000_check_polarity_82577;
482 phy->ops.force_speed_duplex =
483 e1000_phy_force_speed_duplex_82577;
484 phy->ops.get_cable_length = e1000_get_cable_length_82577;
485 phy->ops.get_info = e1000_get_phy_info_82577;
486 phy->ops.commit = e1000e_phy_sw_reset;
487 break;
488 case e1000_phy_82578:
489 phy->ops.check_polarity = e1000_check_polarity_m88;
490 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
491 phy->ops.get_cable_length = e1000e_get_cable_length_m88;
492 phy->ops.get_info = e1000e_get_phy_info_m88;
493 break;
494 default:
495 ret_val = -E1000_ERR_PHY;
496 break;
497 }
498
499 return ret_val;
500 }
501
502 /**
503 * e1000_init_phy_params_ich8lan - Initialize PHY function pointers
504 * @hw: pointer to the HW structure
505 *
506 * Initialize family-specific PHY parameters and function pointers.
507 **/
e1000_init_phy_params_ich8lan(struct e1000_hw * hw)508 static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
509 {
510 struct e1000_phy_info *phy = &hw->phy;
511 s32 ret_val;
512 u16 i = 0;
513
514 phy->addr = 1;
515 phy->reset_delay_us = 100;
516
517 phy->ops.power_up = e1000_power_up_phy_copper;
518 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
519
520 /* We may need to do this twice - once for IGP and if that fails,
521 * we'll set BM func pointers and try again
522 */
523 ret_val = e1000e_determine_phy_address(hw);
524 if (ret_val) {
525 phy->ops.write_reg = e1000e_write_phy_reg_bm;
526 phy->ops.read_reg = e1000e_read_phy_reg_bm;
527 ret_val = e1000e_determine_phy_address(hw);
528 if (ret_val) {
529 e_dbg("Cannot determine PHY addr. Erroring out\n");
530 return ret_val;
531 }
532 }
533
534 phy->id = 0;
535 while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy->id)) &&
536 (i++ < 100)) {
537 usleep_range(1000, 2000);
538 ret_val = e1000e_get_phy_id(hw);
539 if (ret_val)
540 return ret_val;
541 }
542
543 /* Verify phy id */
544 switch (phy->id) {
545 case IGP03E1000_E_PHY_ID:
546 phy->type = e1000_phy_igp_3;
547 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
548 phy->ops.read_reg_locked = e1000e_read_phy_reg_igp_locked;
549 phy->ops.write_reg_locked = e1000e_write_phy_reg_igp_locked;
550 phy->ops.get_info = e1000e_get_phy_info_igp;
551 phy->ops.check_polarity = e1000_check_polarity_igp;
552 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_igp;
553 break;
554 case IFE_E_PHY_ID:
555 case IFE_PLUS_E_PHY_ID:
556 case IFE_C_E_PHY_ID:
557 phy->type = e1000_phy_ife;
558 phy->autoneg_mask = E1000_ALL_NOT_GIG;
559 phy->ops.get_info = e1000_get_phy_info_ife;
560 phy->ops.check_polarity = e1000_check_polarity_ife;
561 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife;
562 break;
563 case BME1000_E_PHY_ID:
564 phy->type = e1000_phy_bm;
565 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
566 phy->ops.read_reg = e1000e_read_phy_reg_bm;
567 phy->ops.write_reg = e1000e_write_phy_reg_bm;
568 phy->ops.commit = e1000e_phy_sw_reset;
569 phy->ops.get_info = e1000e_get_phy_info_m88;
570 phy->ops.check_polarity = e1000_check_polarity_m88;
571 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
572 break;
573 default:
574 return -E1000_ERR_PHY;
575 }
576
577 return 0;
578 }
579
580 /**
581 * e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
582 * @hw: pointer to the HW structure
583 *
584 * Initialize family-specific NVM parameters and function
585 * pointers.
586 **/
e1000_init_nvm_params_ich8lan(struct e1000_hw * hw)587 static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
588 {
589 struct e1000_nvm_info *nvm = &hw->nvm;
590 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
591 u32 gfpreg, sector_base_addr, sector_end_addr;
592 u16 i;
593
594 /* Can't read flash registers if the register set isn't mapped. */
595 if (!hw->flash_address) {
596 e_dbg("ERROR: Flash registers not mapped\n");
597 return -E1000_ERR_CONFIG;
598 }
599
600 nvm->type = e1000_nvm_flash_sw;
601
602 gfpreg = er32flash(ICH_FLASH_GFPREG);
603
604 /* sector_X_addr is a "sector"-aligned address (4096 bytes)
605 * Add 1 to sector_end_addr since this sector is included in
606 * the overall size.
607 */
608 sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
609 sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
610
611 /* flash_base_addr is byte-aligned */
612 nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT;
613
614 /* find total size of the NVM, then cut in half since the total
615 * size represents two separate NVM banks.
616 */
617 nvm->flash_bank_size = ((sector_end_addr - sector_base_addr)
618 << FLASH_SECTOR_ADDR_SHIFT);
619 nvm->flash_bank_size /= 2;
620 /* Adjust to word count */
621 nvm->flash_bank_size /= sizeof(u16);
622
623 nvm->word_size = E1000_ICH8_SHADOW_RAM_WORDS;
624
625 /* Clear shadow ram */
626 for (i = 0; i < nvm->word_size; i++) {
627 dev_spec->shadow_ram[i].modified = false;
628 dev_spec->shadow_ram[i].value = 0xFFFF;
629 }
630
631 return 0;
632 }
633
634 /**
635 * e1000_init_mac_params_ich8lan - Initialize MAC function pointers
636 * @hw: pointer to the HW structure
637 *
638 * Initialize family-specific MAC parameters and function
639 * pointers.
640 **/
e1000_init_mac_params_ich8lan(struct e1000_hw * hw)641 static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw)
642 {
643 struct e1000_mac_info *mac = &hw->mac;
644
645 /* Set media type function pointer */
646 hw->phy.media_type = e1000_media_type_copper;
647
648 /* Set mta register count */
649 mac->mta_reg_count = 32;
650 /* Set rar entry count */
651 mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;
652 if (mac->type == e1000_ich8lan)
653 mac->rar_entry_count--;
654 /* FWSM register */
655 mac->has_fwsm = true;
656 /* ARC subsystem not supported */
657 mac->arc_subsystem_valid = false;
658 /* Adaptive IFS supported */
659 mac->adaptive_ifs = true;
660
661 /* LED and other operations */
662 switch (mac->type) {
663 case e1000_ich8lan:
664 case e1000_ich9lan:
665 case e1000_ich10lan:
666 /* check management mode */
667 mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan;
668 /* ID LED init */
669 mac->ops.id_led_init = e1000e_id_led_init_generic;
670 /* blink LED */
671 mac->ops.blink_led = e1000e_blink_led_generic;
672 /* setup LED */
673 mac->ops.setup_led = e1000e_setup_led_generic;
674 /* cleanup LED */
675 mac->ops.cleanup_led = e1000_cleanup_led_ich8lan;
676 /* turn on/off LED */
677 mac->ops.led_on = e1000_led_on_ich8lan;
678 mac->ops.led_off = e1000_led_off_ich8lan;
679 break;
680 case e1000_pch2lan:
681 mac->rar_entry_count = E1000_PCH2_RAR_ENTRIES;
682 mac->ops.rar_set = e1000_rar_set_pch2lan;
683 /* fall-through */
684 case e1000_pch_lpt:
685 case e1000_pchlan:
686 /* check management mode */
687 mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan;
688 /* ID LED init */
689 mac->ops.id_led_init = e1000_id_led_init_pchlan;
690 /* setup LED */
691 mac->ops.setup_led = e1000_setup_led_pchlan;
692 /* cleanup LED */
693 mac->ops.cleanup_led = e1000_cleanup_led_pchlan;
694 /* turn on/off LED */
695 mac->ops.led_on = e1000_led_on_pchlan;
696 mac->ops.led_off = e1000_led_off_pchlan;
697 break;
698 default:
699 break;
700 }
701
702 if (mac->type == e1000_pch_lpt) {
703 mac->rar_entry_count = E1000_PCH_LPT_RAR_ENTRIES;
704 mac->ops.rar_set = e1000_rar_set_pch_lpt;
705 mac->ops.setup_physical_interface =
706 e1000_setup_copper_link_pch_lpt;
707 mac->ops.rar_get_count = e1000_rar_get_count_pch_lpt;
708 }
709
710 /* Enable PCS Lock-loss workaround for ICH8 */
711 if (mac->type == e1000_ich8lan)
712 e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, true);
713
714 return 0;
715 }
716
717 /**
718 * __e1000_access_emi_reg_locked - Read/write EMI register
719 * @hw: pointer to the HW structure
720 * @addr: EMI address to program
721 * @data: pointer to value to read/write from/to the EMI address
722 * @read: boolean flag to indicate read or write
723 *
724 * This helper function assumes the SW/FW/HW Semaphore is already acquired.
725 **/
__e1000_access_emi_reg_locked(struct e1000_hw * hw,u16 address,u16 * data,bool read)726 static s32 __e1000_access_emi_reg_locked(struct e1000_hw *hw, u16 address,
727 u16 *data, bool read)
728 {
729 s32 ret_val;
730
731 ret_val = e1e_wphy_locked(hw, I82579_EMI_ADDR, address);
732 if (ret_val)
733 return ret_val;
734
735 if (read)
736 ret_val = e1e_rphy_locked(hw, I82579_EMI_DATA, data);
737 else
738 ret_val = e1e_wphy_locked(hw, I82579_EMI_DATA, *data);
739
740 return ret_val;
741 }
742
743 /**
744 * e1000_read_emi_reg_locked - Read Extended Management Interface register
745 * @hw: pointer to the HW structure
746 * @addr: EMI address to program
747 * @data: value to be read from the EMI address
748 *
749 * Assumes the SW/FW/HW Semaphore is already acquired.
750 **/
e1000_read_emi_reg_locked(struct e1000_hw * hw,u16 addr,u16 * data)751 s32 e1000_read_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 *data)
752 {
753 return __e1000_access_emi_reg_locked(hw, addr, data, true);
754 }
755
756 /**
757 * e1000_write_emi_reg_locked - Write Extended Management Interface register
758 * @hw: pointer to the HW structure
759 * @addr: EMI address to program
760 * @data: value to be written to the EMI address
761 *
762 * Assumes the SW/FW/HW Semaphore is already acquired.
763 **/
e1000_write_emi_reg_locked(struct e1000_hw * hw,u16 addr,u16 data)764 s32 e1000_write_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 data)
765 {
766 return __e1000_access_emi_reg_locked(hw, addr, &data, false);
767 }
768
769 /**
770 * e1000_set_eee_pchlan - Enable/disable EEE support
771 * @hw: pointer to the HW structure
772 *
773 * Enable/disable EEE based on setting in dev_spec structure, the duplex of
774 * the link and the EEE capabilities of the link partner. The LPI Control
775 * register bits will remain set only if/when link is up.
776 *
777 * EEE LPI must not be asserted earlier than one second after link is up.
778 * On 82579, EEE LPI should not be enabled until such time otherwise there
779 * can be link issues with some switches. Other devices can have EEE LPI
780 * enabled immediately upon link up since they have a timer in hardware which
781 * prevents LPI from being asserted too early.
782 **/
e1000_set_eee_pchlan(struct e1000_hw * hw)783 s32 e1000_set_eee_pchlan(struct e1000_hw *hw)
784 {
785 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
786 s32 ret_val;
787 u16 lpa, pcs_status, adv, adv_addr, lpi_ctrl, data;
788
789 switch (hw->phy.type) {
790 case e1000_phy_82579:
791 lpa = I82579_EEE_LP_ABILITY;
792 pcs_status = I82579_EEE_PCS_STATUS;
793 adv_addr = I82579_EEE_ADVERTISEMENT;
794 break;
795 case e1000_phy_i217:
796 lpa = I217_EEE_LP_ABILITY;
797 pcs_status = I217_EEE_PCS_STATUS;
798 adv_addr = I217_EEE_ADVERTISEMENT;
799 break;
800 default:
801 return 0;
802 }
803
804 ret_val = hw->phy.ops.acquire(hw);
805 if (ret_val)
806 return ret_val;
807
808 ret_val = e1e_rphy_locked(hw, I82579_LPI_CTRL, &lpi_ctrl);
809 if (ret_val)
810 goto release;
811
812 /* Clear bits that enable EEE in various speeds */
813 lpi_ctrl &= ~I82579_LPI_CTRL_ENABLE_MASK;
814
815 /* Enable EEE if not disabled by user */
816 if (!dev_spec->eee_disable) {
817 /* Save off link partner's EEE ability */
818 ret_val = e1000_read_emi_reg_locked(hw, lpa,
819 &dev_spec->eee_lp_ability);
820 if (ret_val)
821 goto release;
822
823 /* Read EEE advertisement */
824 ret_val = e1000_read_emi_reg_locked(hw, adv_addr, &adv);
825 if (ret_val)
826 goto release;
827
828 /* Enable EEE only for speeds in which the link partner is
829 * EEE capable and for which we advertise EEE.
830 */
831 if (adv & dev_spec->eee_lp_ability & I82579_EEE_1000_SUPPORTED)
832 lpi_ctrl |= I82579_LPI_CTRL_1000_ENABLE;
833
834 if (adv & dev_spec->eee_lp_ability & I82579_EEE_100_SUPPORTED) {
835 e1e_rphy_locked(hw, MII_LPA, &data);
836 if (data & LPA_100FULL)
837 lpi_ctrl |= I82579_LPI_CTRL_100_ENABLE;
838 else
839 /* EEE is not supported in 100Half, so ignore
840 * partner's EEE in 100 ability if full-duplex
841 * is not advertised.
842 */
843 dev_spec->eee_lp_ability &=
844 ~I82579_EEE_100_SUPPORTED;
845 }
846 }
847
848 if (hw->phy.type == e1000_phy_82579) {
849 ret_val = e1000_read_emi_reg_locked(hw, I82579_LPI_PLL_SHUT,
850 &data);
851 if (ret_val)
852 goto release;
853
854 data &= ~I82579_LPI_100_PLL_SHUT;
855 ret_val = e1000_write_emi_reg_locked(hw, I82579_LPI_PLL_SHUT,
856 data);
857 }
858
859 /* R/Clr IEEE MMD 3.1 bits 11:10 - Tx/Rx LPI Received */
860 ret_val = e1000_read_emi_reg_locked(hw, pcs_status, &data);
861 if (ret_val)
862 goto release;
863
864 ret_val = e1e_wphy_locked(hw, I82579_LPI_CTRL, lpi_ctrl);
865 release:
866 hw->phy.ops.release(hw);
867
868 return ret_val;
869 }
870
871 /**
872 * e1000_k1_workaround_lpt_lp - K1 workaround on Lynxpoint-LP
873 * @hw: pointer to the HW structure
874 * @link: link up bool flag
875 *
876 * When K1 is enabled for 1Gbps, the MAC can miss 2 DMA completion indications
877 * preventing further DMA write requests. Workaround the issue by disabling
878 * the de-assertion of the clock request when in 1Gpbs mode.
879 * Also, set appropriate Tx re-transmission timeouts for 10 and 100Half link
880 * speeds in order to avoid Tx hangs.
881 **/
e1000_k1_workaround_lpt_lp(struct e1000_hw * hw,bool link)882 static s32 e1000_k1_workaround_lpt_lp(struct e1000_hw *hw, bool link)
883 {
884 u32 fextnvm6 = er32(FEXTNVM6);
885 u32 status = er32(STATUS);
886 s32 ret_val = 0;
887 u16 reg;
888
889 if (link && (status & E1000_STATUS_SPEED_1000)) {
890 ret_val = hw->phy.ops.acquire(hw);
891 if (ret_val)
892 return ret_val;
893
894 ret_val =
895 e1000e_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
896 ®);
897 if (ret_val)
898 goto release;
899
900 ret_val =
901 e1000e_write_kmrn_reg_locked(hw,
902 E1000_KMRNCTRLSTA_K1_CONFIG,
903 reg &
904 ~E1000_KMRNCTRLSTA_K1_ENABLE);
905 if (ret_val)
906 goto release;
907
908 usleep_range(10, 20);
909
910 ew32(FEXTNVM6, fextnvm6 | E1000_FEXTNVM6_REQ_PLL_CLK);
911
912 ret_val =
913 e1000e_write_kmrn_reg_locked(hw,
914 E1000_KMRNCTRLSTA_K1_CONFIG,
915 reg);
916 release:
917 hw->phy.ops.release(hw);
918 } else {
919 /* clear FEXTNVM6 bit 8 on link down or 10/100 */
920 fextnvm6 &= ~E1000_FEXTNVM6_REQ_PLL_CLK;
921
922 if (!link || ((status & E1000_STATUS_SPEED_100) &&
923 (status & E1000_STATUS_FD)))
924 goto update_fextnvm6;
925
926 ret_val = e1e_rphy(hw, I217_INBAND_CTRL, ®);
927 if (ret_val)
928 return ret_val;
929
930 /* Clear link status transmit timeout */
931 reg &= ~I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_MASK;
932
933 if (status & E1000_STATUS_SPEED_100) {
934 /* Set inband Tx timeout to 5x10us for 100Half */
935 reg |= 5 << I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT;
936
937 /* Do not extend the K1 entry latency for 100Half */
938 fextnvm6 &= ~E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION;
939 } else {
940 /* Set inband Tx timeout to 50x10us for 10Full/Half */
941 reg |= 50 <<
942 I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT;
943
944 /* Extend the K1 entry latency for 10 Mbps */
945 fextnvm6 |= E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION;
946 }
947
948 ret_val = e1e_wphy(hw, I217_INBAND_CTRL, reg);
949 if (ret_val)
950 return ret_val;
951
952 update_fextnvm6:
953 ew32(FEXTNVM6, fextnvm6);
954 }
955
956 return ret_val;
957 }
958
959 /**
960 * e1000_platform_pm_pch_lpt - Set platform power management values
961 * @hw: pointer to the HW structure
962 * @link: bool indicating link status
963 *
964 * Set the Latency Tolerance Reporting (LTR) values for the "PCIe-like"
965 * GbE MAC in the Lynx Point PCH based on Rx buffer size and link speed
966 * when link is up (which must not exceed the maximum latency supported
967 * by the platform), otherwise specify there is no LTR requirement.
968 * Unlike true-PCIe devices which set the LTR maximum snoop/no-snoop
969 * latencies in the LTR Extended Capability Structure in the PCIe Extended
970 * Capability register set, on this device LTR is set by writing the
971 * equivalent snoop/no-snoop latencies in the LTRV register in the MAC and
972 * set the SEND bit to send an Intel On-chip System Fabric sideband (IOSF-SB)
973 * message to the PMC.
974 **/
e1000_platform_pm_pch_lpt(struct e1000_hw * hw,bool link)975 static s32 e1000_platform_pm_pch_lpt(struct e1000_hw *hw, bool link)
976 {
977 u32 reg = link << (E1000_LTRV_REQ_SHIFT + E1000_LTRV_NOSNOOP_SHIFT) |
978 link << E1000_LTRV_REQ_SHIFT | E1000_LTRV_SEND;
979 u16 lat_enc = 0; /* latency encoded */
980
981 if (link) {
982 u16 speed, duplex, scale = 0;
983 u16 max_snoop, max_nosnoop;
984 u16 max_ltr_enc; /* max LTR latency encoded */
985 s64 lat_ns; /* latency (ns) */
986 u64 value;
987 u32 rxa;
988
989 if (!hw->adapter->max_frame_size) {
990 e_dbg("max_frame_size not set.\n");
991 return -E1000_ERR_CONFIG;
992 }
993
994 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
995 if (!speed) {
996 e_dbg("Speed not set.\n");
997 return -E1000_ERR_CONFIG;
998 }
999
1000 /* Rx Packet Buffer Allocation size (KB) */
1001 rxa = er32(PBA) & E1000_PBA_RXA_MASK;
1002
1003 /* Determine the maximum latency tolerated by the device.
1004 *
1005 * Per the PCIe spec, the tolerated latencies are encoded as
1006 * a 3-bit encoded scale (only 0-5 are valid) multiplied by
1007 * a 10-bit value (0-1023) to provide a range from 1 ns to
1008 * 2^25*(2^10-1) ns. The scale is encoded as 0=2^0ns,
1009 * 1=2^5ns, 2=2^10ns,...5=2^25ns.
1010 */
1011 lat_ns = ((s64)rxa * 1024 -
1012 (2 * (s64)hw->adapter->max_frame_size)) * 8 * 1000;
1013 if (lat_ns < 0) {
1014 value = 0;
1015 } else {
1016 value = lat_ns;
1017 do_div(value, speed);
1018 }
1019
1020 while (value > PCI_LTR_VALUE_MASK) {
1021 scale++;
1022 value = DIV_ROUND_UP(value, (1 << 5));
1023 }
1024 if (scale > E1000_LTRV_SCALE_MAX) {
1025 e_dbg("Invalid LTR latency scale %d\n", scale);
1026 return -E1000_ERR_CONFIG;
1027 }
1028 lat_enc = (u16)((scale << PCI_LTR_SCALE_SHIFT) | value);
1029
1030 /* Determine the maximum latency tolerated by the platform */
1031 pci_read_config_word(hw->adapter->pdev, E1000_PCI_LTR_CAP_LPT,
1032 &max_snoop);
1033 pci_read_config_word(hw->adapter->pdev,
1034 E1000_PCI_LTR_CAP_LPT + 2, &max_nosnoop);
1035 max_ltr_enc = max_t(u16, max_snoop, max_nosnoop);
1036
1037 if (lat_enc > max_ltr_enc)
1038 lat_enc = max_ltr_enc;
1039 }
1040
1041 /* Set Snoop and No-Snoop latencies the same */
1042 reg |= lat_enc | (lat_enc << E1000_LTRV_NOSNOOP_SHIFT);
1043 ew32(LTRV, reg);
1044
1045 return 0;
1046 }
1047
1048 /**
1049 * e1000_enable_ulp_lpt_lp - configure Ultra Low Power mode for LynxPoint-LP
1050 * @hw: pointer to the HW structure
1051 * @to_sx: boolean indicating a system power state transition to Sx
1052 *
1053 * When link is down, configure ULP mode to significantly reduce the power
1054 * to the PHY. If on a Manageability Engine (ME) enabled system, tell the
1055 * ME firmware to start the ULP configuration. If not on an ME enabled
1056 * system, configure the ULP mode by software.
1057 */
e1000_enable_ulp_lpt_lp(struct e1000_hw * hw,bool to_sx)1058 s32 e1000_enable_ulp_lpt_lp(struct e1000_hw *hw, bool to_sx)
1059 {
1060 u32 mac_reg;
1061 s32 ret_val = 0;
1062 u16 phy_reg;
1063
1064 if ((hw->mac.type < e1000_pch_lpt) ||
1065 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_LM) ||
1066 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_V) ||
1067 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM2) ||
1068 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V2) ||
1069 (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_on))
1070 return 0;
1071
1072 if (er32(FWSM) & E1000_ICH_FWSM_FW_VALID) {
1073 /* Request ME configure ULP mode in the PHY */
1074 mac_reg = er32(H2ME);
1075 mac_reg |= E1000_H2ME_ULP | E1000_H2ME_ENFORCE_SETTINGS;
1076 ew32(H2ME, mac_reg);
1077
1078 goto out;
1079 }
1080
1081 if (!to_sx) {
1082 int i = 0;
1083
1084 /* Poll up to 5 seconds for Cable Disconnected indication */
1085 while (!(er32(FEXT) & E1000_FEXT_PHY_CABLE_DISCONNECTED)) {
1086 /* Bail if link is re-acquired */
1087 if (er32(STATUS) & E1000_STATUS_LU)
1088 return -E1000_ERR_PHY;
1089
1090 if (i++ == 100)
1091 break;
1092
1093 msleep(50);
1094 }
1095 e_dbg("CABLE_DISCONNECTED %s set after %dmsec\n",
1096 (er32(FEXT) &
1097 E1000_FEXT_PHY_CABLE_DISCONNECTED) ? "" : "not", i * 50);
1098 }
1099
1100 ret_val = hw->phy.ops.acquire(hw);
1101 if (ret_val)
1102 goto out;
1103
1104 /* Force SMBus mode in PHY */
1105 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg);
1106 if (ret_val)
1107 goto release;
1108 phy_reg |= CV_SMB_CTRL_FORCE_SMBUS;
1109 e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg);
1110
1111 /* Force SMBus mode in MAC */
1112 mac_reg = er32(CTRL_EXT);
1113 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
1114 ew32(CTRL_EXT, mac_reg);
1115
1116 /* Set Inband ULP Exit, Reset to SMBus mode and
1117 * Disable SMBus Release on PERST# in PHY
1118 */
1119 ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg);
1120 if (ret_val)
1121 goto release;
1122 phy_reg |= (I218_ULP_CONFIG1_RESET_TO_SMBUS |
1123 I218_ULP_CONFIG1_DISABLE_SMB_PERST);
1124 if (to_sx) {
1125 if (er32(WUFC) & E1000_WUFC_LNKC)
1126 phy_reg |= I218_ULP_CONFIG1_WOL_HOST;
1127
1128 phy_reg |= I218_ULP_CONFIG1_STICKY_ULP;
1129 } else {
1130 phy_reg |= I218_ULP_CONFIG1_INBAND_EXIT;
1131 }
1132 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1133
1134 /* Set Disable SMBus Release on PERST# in MAC */
1135 mac_reg = er32(FEXTNVM7);
1136 mac_reg |= E1000_FEXTNVM7_DISABLE_SMB_PERST;
1137 ew32(FEXTNVM7, mac_reg);
1138
1139 /* Commit ULP changes in PHY by starting auto ULP configuration */
1140 phy_reg |= I218_ULP_CONFIG1_START;
1141 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1142 release:
1143 hw->phy.ops.release(hw);
1144 out:
1145 if (ret_val)
1146 e_dbg("Error in ULP enable flow: %d\n", ret_val);
1147 else
1148 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_on;
1149
1150 return ret_val;
1151 }
1152
1153 /**
1154 * e1000_disable_ulp_lpt_lp - unconfigure Ultra Low Power mode for LynxPoint-LP
1155 * @hw: pointer to the HW structure
1156 * @force: boolean indicating whether or not to force disabling ULP
1157 *
1158 * Un-configure ULP mode when link is up, the system is transitioned from
1159 * Sx or the driver is unloaded. If on a Manageability Engine (ME) enabled
1160 * system, poll for an indication from ME that ULP has been un-configured.
1161 * If not on an ME enabled system, un-configure the ULP mode by software.
1162 *
1163 * During nominal operation, this function is called when link is acquired
1164 * to disable ULP mode (force=false); otherwise, for example when unloading
1165 * the driver or during Sx->S0 transitions, this is called with force=true
1166 * to forcibly disable ULP.
1167 */
e1000_disable_ulp_lpt_lp(struct e1000_hw * hw,bool force)1168 static s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force)
1169 {
1170 s32 ret_val = 0;
1171 u32 mac_reg;
1172 u16 phy_reg;
1173 int i = 0;
1174
1175 if ((hw->mac.type < e1000_pch_lpt) ||
1176 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_LM) ||
1177 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_V) ||
1178 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM2) ||
1179 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V2) ||
1180 (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_off))
1181 return 0;
1182
1183 if (er32(FWSM) & E1000_ICH_FWSM_FW_VALID) {
1184 if (force) {
1185 /* Request ME un-configure ULP mode in the PHY */
1186 mac_reg = er32(H2ME);
1187 mac_reg &= ~E1000_H2ME_ULP;
1188 mac_reg |= E1000_H2ME_ENFORCE_SETTINGS;
1189 ew32(H2ME, mac_reg);
1190 }
1191
1192 /* Poll up to 100msec for ME to clear ULP_CFG_DONE */
1193 while (er32(FWSM) & E1000_FWSM_ULP_CFG_DONE) {
1194 if (i++ == 10) {
1195 ret_val = -E1000_ERR_PHY;
1196 goto out;
1197 }
1198
1199 usleep_range(10000, 20000);
1200 }
1201 e_dbg("ULP_CONFIG_DONE cleared after %dmsec\n", i * 10);
1202
1203 if (force) {
1204 mac_reg = er32(H2ME);
1205 mac_reg &= ~E1000_H2ME_ENFORCE_SETTINGS;
1206 ew32(H2ME, mac_reg);
1207 } else {
1208 /* Clear H2ME.ULP after ME ULP configuration */
1209 mac_reg = er32(H2ME);
1210 mac_reg &= ~E1000_H2ME_ULP;
1211 ew32(H2ME, mac_reg);
1212 }
1213
1214 goto out;
1215 }
1216
1217 ret_val = hw->phy.ops.acquire(hw);
1218 if (ret_val)
1219 goto out;
1220
1221 if (force)
1222 /* Toggle LANPHYPC Value bit */
1223 e1000_toggle_lanphypc_pch_lpt(hw);
1224
1225 /* Unforce SMBus mode in PHY */
1226 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg);
1227 if (ret_val) {
1228 /* The MAC might be in PCIe mode, so temporarily force to
1229 * SMBus mode in order to access the PHY.
1230 */
1231 mac_reg = er32(CTRL_EXT);
1232 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
1233 ew32(CTRL_EXT, mac_reg);
1234
1235 msleep(50);
1236
1237 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL,
1238 &phy_reg);
1239 if (ret_val)
1240 goto release;
1241 }
1242 phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
1243 e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg);
1244
1245 /* Unforce SMBus mode in MAC */
1246 mac_reg = er32(CTRL_EXT);
1247 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
1248 ew32(CTRL_EXT, mac_reg);
1249
1250 /* When ULP mode was previously entered, K1 was disabled by the
1251 * hardware. Re-Enable K1 in the PHY when exiting ULP.
1252 */
1253 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_PM_CTRL, &phy_reg);
1254 if (ret_val)
1255 goto release;
1256 phy_reg |= HV_PM_CTRL_K1_ENABLE;
1257 e1000_write_phy_reg_hv_locked(hw, HV_PM_CTRL, phy_reg);
1258
1259 /* Clear ULP enabled configuration */
1260 ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg);
1261 if (ret_val)
1262 goto release;
1263 phy_reg &= ~(I218_ULP_CONFIG1_IND |
1264 I218_ULP_CONFIG1_STICKY_ULP |
1265 I218_ULP_CONFIG1_RESET_TO_SMBUS |
1266 I218_ULP_CONFIG1_WOL_HOST |
1267 I218_ULP_CONFIG1_INBAND_EXIT |
1268 I218_ULP_CONFIG1_DISABLE_SMB_PERST);
1269 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1270
1271 /* Commit ULP changes by starting auto ULP configuration */
1272 phy_reg |= I218_ULP_CONFIG1_START;
1273 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1274
1275 /* Clear Disable SMBus Release on PERST# in MAC */
1276 mac_reg = er32(FEXTNVM7);
1277 mac_reg &= ~E1000_FEXTNVM7_DISABLE_SMB_PERST;
1278 ew32(FEXTNVM7, mac_reg);
1279
1280 release:
1281 hw->phy.ops.release(hw);
1282 if (force) {
1283 e1000_phy_hw_reset(hw);
1284 msleep(50);
1285 }
1286 out:
1287 if (ret_val)
1288 e_dbg("Error in ULP disable flow: %d\n", ret_val);
1289 else
1290 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_off;
1291
1292 return ret_val;
1293 }
1294
1295 /**
1296 * e1000_check_for_copper_link_ich8lan - Check for link (Copper)
1297 * @hw: pointer to the HW structure
1298 *
1299 * Checks to see of the link status of the hardware has changed. If a
1300 * change in link status has been detected, then we read the PHY registers
1301 * to get the current speed/duplex if link exists.
1302 *
1303 * Returns a negative error code (-E1000_ERR_*) or 0 (link down) or 1 (link
1304 * up).
1305 **/
e1000_check_for_copper_link_ich8lan(struct e1000_hw * hw)1306 static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
1307 {
1308 struct e1000_mac_info *mac = &hw->mac;
1309 s32 ret_val;
1310 bool link;
1311 u16 phy_reg;
1312
1313 /* We only want to go out to the PHY registers to see if Auto-Neg
1314 * has completed and/or if our link status has changed. The
1315 * get_link_status flag is set upon receiving a Link Status
1316 * Change or Rx Sequence Error interrupt.
1317 */
1318 if (!mac->get_link_status)
1319 return 1;
1320
1321 /* First we want to see if the MII Status Register reports
1322 * link. If so, then we want to get the current speed/duplex
1323 * of the PHY.
1324 */
1325 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
1326 if (ret_val)
1327 return ret_val;
1328
1329 if (hw->mac.type == e1000_pchlan) {
1330 ret_val = e1000_k1_gig_workaround_hv(hw, link);
1331 if (ret_val)
1332 return ret_val;
1333 }
1334
1335 /* When connected at 10Mbps half-duplex, some parts are excessively
1336 * aggressive resulting in many collisions. To avoid this, increase
1337 * the IPG and reduce Rx latency in the PHY.
1338 */
1339 if (((hw->mac.type == e1000_pch2lan) ||
1340 (hw->mac.type == e1000_pch_lpt)) && link) {
1341 u32 reg;
1342
1343 reg = er32(STATUS);
1344 if (!(reg & (E1000_STATUS_FD | E1000_STATUS_SPEED_MASK))) {
1345 u16 emi_addr;
1346
1347 reg = er32(TIPG);
1348 reg &= ~E1000_TIPG_IPGT_MASK;
1349 reg |= 0xFF;
1350 ew32(TIPG, reg);
1351
1352 /* Reduce Rx latency in analog PHY */
1353 ret_val = hw->phy.ops.acquire(hw);
1354 if (ret_val)
1355 return ret_val;
1356
1357 if (hw->mac.type == e1000_pch2lan)
1358 emi_addr = I82579_RX_CONFIG;
1359 else
1360 emi_addr = I217_RX_CONFIG;
1361
1362 ret_val = e1000_write_emi_reg_locked(hw, emi_addr, 0);
1363
1364 hw->phy.ops.release(hw);
1365
1366 if (ret_val)
1367 return ret_val;
1368 }
1369 }
1370
1371 /* Work-around I218 hang issue */
1372 if ((hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||
1373 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPTLP_I218_V) ||
1374 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM3) ||
1375 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V3)) {
1376 ret_val = e1000_k1_workaround_lpt_lp(hw, link);
1377 if (ret_val)
1378 return ret_val;
1379 }
1380
1381 if (hw->mac.type == e1000_pch_lpt) {
1382 /* Set platform power management values for
1383 * Latency Tolerance Reporting (LTR)
1384 */
1385 ret_val = e1000_platform_pm_pch_lpt(hw, link);
1386 if (ret_val)
1387 return ret_val;
1388 }
1389
1390 /* Clear link partner's EEE ability */
1391 hw->dev_spec.ich8lan.eee_lp_ability = 0;
1392
1393 if (!link)
1394 return 0; /* No link detected */
1395
1396 mac->get_link_status = false;
1397
1398 switch (hw->mac.type) {
1399 case e1000_pch2lan:
1400 ret_val = e1000_k1_workaround_lv(hw);
1401 if (ret_val)
1402 return ret_val;
1403 /* fall-thru */
1404 case e1000_pchlan:
1405 if (hw->phy.type == e1000_phy_82578) {
1406 ret_val = e1000_link_stall_workaround_hv(hw);
1407 if (ret_val)
1408 return ret_val;
1409 }
1410
1411 /* Workaround for PCHx parts in half-duplex:
1412 * Set the number of preambles removed from the packet
1413 * when it is passed from the PHY to the MAC to prevent
1414 * the MAC from misinterpreting the packet type.
1415 */
1416 e1e_rphy(hw, HV_KMRN_FIFO_CTRLSTA, &phy_reg);
1417 phy_reg &= ~HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK;
1418
1419 if ((er32(STATUS) & E1000_STATUS_FD) != E1000_STATUS_FD)
1420 phy_reg |= (1 << HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT);
1421
1422 e1e_wphy(hw, HV_KMRN_FIFO_CTRLSTA, phy_reg);
1423 break;
1424 default:
1425 break;
1426 }
1427
1428 /* Check if there was DownShift, must be checked
1429 * immediately after link-up
1430 */
1431 e1000e_check_downshift(hw);
1432
1433 /* Enable/Disable EEE after link up */
1434 if (hw->phy.type > e1000_phy_82579) {
1435 ret_val = e1000_set_eee_pchlan(hw);
1436 if (ret_val)
1437 return ret_val;
1438 }
1439
1440 /* If we are forcing speed/duplex, then we simply return since
1441 * we have already determined whether we have link or not.
1442 */
1443 if (!mac->autoneg)
1444 return -E1000_ERR_CONFIG;
1445
1446 /* Auto-Neg is enabled. Auto Speed Detection takes care
1447 * of MAC speed/duplex configuration. So we only need to
1448 * configure Collision Distance in the MAC.
1449 */
1450 mac->ops.config_collision_dist(hw);
1451
1452 /* Configure Flow Control now that Auto-Neg has completed.
1453 * First, we need to restore the desired flow control
1454 * settings because we may have had to re-autoneg with a
1455 * different link partner.
1456 */
1457 ret_val = e1000e_config_fc_after_link_up(hw);
1458 if (ret_val) {
1459 e_dbg("Error configuring flow control\n");
1460 return ret_val;
1461 }
1462
1463 return 1;
1464 }
1465
e1000_get_variants_ich8lan(struct e1000_adapter * adapter)1466 static s32 e1000_get_variants_ich8lan(struct e1000_adapter *adapter)
1467 {
1468 struct e1000_hw *hw = &adapter->hw;
1469 s32 rc;
1470
1471 rc = e1000_init_mac_params_ich8lan(hw);
1472 if (rc)
1473 return rc;
1474
1475 rc = e1000_init_nvm_params_ich8lan(hw);
1476 if (rc)
1477 return rc;
1478
1479 switch (hw->mac.type) {
1480 case e1000_ich8lan:
1481 case e1000_ich9lan:
1482 case e1000_ich10lan:
1483 rc = e1000_init_phy_params_ich8lan(hw);
1484 break;
1485 case e1000_pchlan:
1486 case e1000_pch2lan:
1487 case e1000_pch_lpt:
1488 rc = e1000_init_phy_params_pchlan(hw);
1489 break;
1490 default:
1491 break;
1492 }
1493 if (rc)
1494 return rc;
1495
1496 /* Disable Jumbo Frame support on parts with Intel 10/100 PHY or
1497 * on parts with MACsec enabled in NVM (reflected in CTRL_EXT).
1498 */
1499 if ((adapter->hw.phy.type == e1000_phy_ife) ||
1500 ((adapter->hw.mac.type >= e1000_pch2lan) &&
1501 (!(er32(CTRL_EXT) & E1000_CTRL_EXT_LSECCK)))) {
1502 adapter->flags &= ~FLAG_HAS_JUMBO_FRAMES;
1503 adapter->max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN;
1504
1505 hw->mac.ops.blink_led = NULL;
1506 }
1507
1508 if ((adapter->hw.mac.type == e1000_ich8lan) &&
1509 (adapter->hw.phy.type != e1000_phy_ife))
1510 adapter->flags |= FLAG_LSC_GIG_SPEED_DROP;
1511
1512 /* Enable workaround for 82579 w/ ME enabled */
1513 if ((adapter->hw.mac.type == e1000_pch2lan) &&
1514 (er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
1515 adapter->flags2 |= FLAG2_PCIM2PCI_ARBITER_WA;
1516
1517 return 0;
1518 }
1519
1520 static DEFINE_MUTEX(nvm_mutex);
1521
1522 /**
1523 * e1000_acquire_nvm_ich8lan - Acquire NVM mutex
1524 * @hw: pointer to the HW structure
1525 *
1526 * Acquires the mutex for performing NVM operations.
1527 **/
e1000_acquire_nvm_ich8lan(struct e1000_hw __always_unused * hw)1528 static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw __always_unused *hw)
1529 {
1530 mutex_lock(&nvm_mutex);
1531
1532 return 0;
1533 }
1534
1535 /**
1536 * e1000_release_nvm_ich8lan - Release NVM mutex
1537 * @hw: pointer to the HW structure
1538 *
1539 * Releases the mutex used while performing NVM operations.
1540 **/
e1000_release_nvm_ich8lan(struct e1000_hw __always_unused * hw)1541 static void e1000_release_nvm_ich8lan(struct e1000_hw __always_unused *hw)
1542 {
1543 mutex_unlock(&nvm_mutex);
1544 }
1545
1546 /**
1547 * e1000_acquire_swflag_ich8lan - Acquire software control flag
1548 * @hw: pointer to the HW structure
1549 *
1550 * Acquires the software control flag for performing PHY and select
1551 * MAC CSR accesses.
1552 **/
e1000_acquire_swflag_ich8lan(struct e1000_hw * hw)1553 static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
1554 {
1555 u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT;
1556 s32 ret_val = 0;
1557
1558 if (test_and_set_bit(__E1000_ACCESS_SHARED_RESOURCE,
1559 &hw->adapter->state)) {
1560 e_dbg("contention for Phy access\n");
1561 return -E1000_ERR_PHY;
1562 }
1563
1564 while (timeout) {
1565 extcnf_ctrl = er32(EXTCNF_CTRL);
1566 if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG))
1567 break;
1568
1569 mdelay(1);
1570 timeout--;
1571 }
1572
1573 if (!timeout) {
1574 e_dbg("SW has already locked the resource.\n");
1575 ret_val = -E1000_ERR_CONFIG;
1576 goto out;
1577 }
1578
1579 timeout = SW_FLAG_TIMEOUT;
1580
1581 extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
1582 ew32(EXTCNF_CTRL, extcnf_ctrl);
1583
1584 while (timeout) {
1585 extcnf_ctrl = er32(EXTCNF_CTRL);
1586 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
1587 break;
1588
1589 mdelay(1);
1590 timeout--;
1591 }
1592
1593 if (!timeout) {
1594 e_dbg("Failed to acquire the semaphore, FW or HW has it: FWSM=0x%8.8x EXTCNF_CTRL=0x%8.8x)\n",
1595 er32(FWSM), extcnf_ctrl);
1596 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
1597 ew32(EXTCNF_CTRL, extcnf_ctrl);
1598 ret_val = -E1000_ERR_CONFIG;
1599 goto out;
1600 }
1601
1602 out:
1603 if (ret_val)
1604 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state);
1605
1606 return ret_val;
1607 }
1608
1609 /**
1610 * e1000_release_swflag_ich8lan - Release software control flag
1611 * @hw: pointer to the HW structure
1612 *
1613 * Releases the software control flag for performing PHY and select
1614 * MAC CSR accesses.
1615 **/
e1000_release_swflag_ich8lan(struct e1000_hw * hw)1616 static void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
1617 {
1618 u32 extcnf_ctrl;
1619
1620 extcnf_ctrl = er32(EXTCNF_CTRL);
1621
1622 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) {
1623 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
1624 ew32(EXTCNF_CTRL, extcnf_ctrl);
1625 } else {
1626 e_dbg("Semaphore unexpectedly released by sw/fw/hw\n");
1627 }
1628
1629 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state);
1630 }
1631
1632 /**
1633 * e1000_check_mng_mode_ich8lan - Checks management mode
1634 * @hw: pointer to the HW structure
1635 *
1636 * This checks if the adapter has any manageability enabled.
1637 * This is a function pointer entry point only called by read/write
1638 * routines for the PHY and NVM parts.
1639 **/
e1000_check_mng_mode_ich8lan(struct e1000_hw * hw)1640 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
1641 {
1642 u32 fwsm;
1643
1644 fwsm = er32(FWSM);
1645 return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
1646 ((fwsm & E1000_FWSM_MODE_MASK) ==
1647 (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
1648 }
1649
1650 /**
1651 * e1000_check_mng_mode_pchlan - Checks management mode
1652 * @hw: pointer to the HW structure
1653 *
1654 * This checks if the adapter has iAMT enabled.
1655 * This is a function pointer entry point only called by read/write
1656 * routines for the PHY and NVM parts.
1657 **/
e1000_check_mng_mode_pchlan(struct e1000_hw * hw)1658 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw)
1659 {
1660 u32 fwsm;
1661
1662 fwsm = er32(FWSM);
1663 return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
1664 (fwsm & (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
1665 }
1666
1667 /**
1668 * e1000_rar_set_pch2lan - Set receive address register
1669 * @hw: pointer to the HW structure
1670 * @addr: pointer to the receive address
1671 * @index: receive address array register
1672 *
1673 * Sets the receive address array register at index to the address passed
1674 * in by addr. For 82579, RAR[0] is the base address register that is to
1675 * contain the MAC address but RAR[1-6] are reserved for manageability (ME).
1676 * Use SHRA[0-3] in place of those reserved for ME.
1677 **/
e1000_rar_set_pch2lan(struct e1000_hw * hw,u8 * addr,u32 index)1678 static int e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index)
1679 {
1680 u32 rar_low, rar_high;
1681
1682 /* HW expects these in little endian so we reverse the byte order
1683 * from network order (big endian) to little endian
1684 */
1685 rar_low = ((u32)addr[0] |
1686 ((u32)addr[1] << 8) |
1687 ((u32)addr[2] << 16) | ((u32)addr[3] << 24));
1688
1689 rar_high = ((u32)addr[4] | ((u32)addr[5] << 8));
1690
1691 /* If MAC address zero, no need to set the AV bit */
1692 if (rar_low || rar_high)
1693 rar_high |= E1000_RAH_AV;
1694
1695 if (index == 0) {
1696 ew32(RAL(index), rar_low);
1697 e1e_flush();
1698 ew32(RAH(index), rar_high);
1699 e1e_flush();
1700 return 0;
1701 }
1702
1703 /* RAR[1-6] are owned by manageability. Skip those and program the
1704 * next address into the SHRA register array.
1705 */
1706 if (index < (u32)(hw->mac.rar_entry_count)) {
1707 s32 ret_val;
1708
1709 ret_val = e1000_acquire_swflag_ich8lan(hw);
1710 if (ret_val)
1711 goto out;
1712
1713 ew32(SHRAL(index - 1), rar_low);
1714 e1e_flush();
1715 ew32(SHRAH(index - 1), rar_high);
1716 e1e_flush();
1717
1718 e1000_release_swflag_ich8lan(hw);
1719
1720 /* verify the register updates */
1721 if ((er32(SHRAL(index - 1)) == rar_low) &&
1722 (er32(SHRAH(index - 1)) == rar_high))
1723 return 0;
1724
1725 e_dbg("SHRA[%d] might be locked by ME - FWSM=0x%8.8x\n",
1726 (index - 1), er32(FWSM));
1727 }
1728
1729 out:
1730 e_dbg("Failed to write receive address at index %d\n", index);
1731 return -E1000_ERR_CONFIG;
1732 }
1733
1734 /**
1735 * e1000_rar_get_count_pch_lpt - Get the number of available SHRA
1736 * @hw: pointer to the HW structure
1737 *
1738 * Get the number of available receive registers that the Host can
1739 * program. SHRA[0-10] are the shared receive address registers
1740 * that are shared between the Host and manageability engine (ME).
1741 * ME can reserve any number of addresses and the host needs to be
1742 * able to tell how many available registers it has access to.
1743 **/
e1000_rar_get_count_pch_lpt(struct e1000_hw * hw)1744 static u32 e1000_rar_get_count_pch_lpt(struct e1000_hw *hw)
1745 {
1746 u32 wlock_mac;
1747 u32 num_entries;
1748
1749 wlock_mac = er32(FWSM) & E1000_FWSM_WLOCK_MAC_MASK;
1750 wlock_mac >>= E1000_FWSM_WLOCK_MAC_SHIFT;
1751
1752 switch (wlock_mac) {
1753 case 0:
1754 /* All SHRA[0..10] and RAR[0] available */
1755 num_entries = hw->mac.rar_entry_count;
1756 break;
1757 case 1:
1758 /* Only RAR[0] available */
1759 num_entries = 1;
1760 break;
1761 default:
1762 /* SHRA[0..(wlock_mac - 1)] available + RAR[0] */
1763 num_entries = wlock_mac + 1;
1764 break;
1765 }
1766
1767 return num_entries;
1768 }
1769
1770 /**
1771 * e1000_rar_set_pch_lpt - Set receive address registers
1772 * @hw: pointer to the HW structure
1773 * @addr: pointer to the receive address
1774 * @index: receive address array register
1775 *
1776 * Sets the receive address register array at index to the address passed
1777 * in by addr. For LPT, RAR[0] is the base address register that is to
1778 * contain the MAC address. SHRA[0-10] are the shared receive address
1779 * registers that are shared between the Host and manageability engine (ME).
1780 **/
e1000_rar_set_pch_lpt(struct e1000_hw * hw,u8 * addr,u32 index)1781 static int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index)
1782 {
1783 u32 rar_low, rar_high;
1784 u32 wlock_mac;
1785
1786 /* HW expects these in little endian so we reverse the byte order
1787 * from network order (big endian) to little endian
1788 */
1789 rar_low = ((u32)addr[0] | ((u32)addr[1] << 8) |
1790 ((u32)addr[2] << 16) | ((u32)addr[3] << 24));
1791
1792 rar_high = ((u32)addr[4] | ((u32)addr[5] << 8));
1793
1794 /* If MAC address zero, no need to set the AV bit */
1795 if (rar_low || rar_high)
1796 rar_high |= E1000_RAH_AV;
1797
1798 if (index == 0) {
1799 ew32(RAL(index), rar_low);
1800 e1e_flush();
1801 ew32(RAH(index), rar_high);
1802 e1e_flush();
1803 return 0;
1804 }
1805
1806 /* The manageability engine (ME) can lock certain SHRAR registers that
1807 * it is using - those registers are unavailable for use.
1808 */
1809 if (index < hw->mac.rar_entry_count) {
1810 wlock_mac = er32(FWSM) & E1000_FWSM_WLOCK_MAC_MASK;
1811 wlock_mac >>= E1000_FWSM_WLOCK_MAC_SHIFT;
1812
1813 /* Check if all SHRAR registers are locked */
1814 if (wlock_mac == 1)
1815 goto out;
1816
1817 if ((wlock_mac == 0) || (index <= wlock_mac)) {
1818 s32 ret_val;
1819
1820 ret_val = e1000_acquire_swflag_ich8lan(hw);
1821
1822 if (ret_val)
1823 goto out;
1824
1825 ew32(SHRAL_PCH_LPT(index - 1), rar_low);
1826 e1e_flush();
1827 ew32(SHRAH_PCH_LPT(index - 1), rar_high);
1828 e1e_flush();
1829
1830 e1000_release_swflag_ich8lan(hw);
1831
1832 /* verify the register updates */
1833 if ((er32(SHRAL_PCH_LPT(index - 1)) == rar_low) &&
1834 (er32(SHRAH_PCH_LPT(index - 1)) == rar_high))
1835 return 0;
1836 }
1837 }
1838
1839 out:
1840 e_dbg("Failed to write receive address at index %d\n", index);
1841 return -E1000_ERR_CONFIG;
1842 }
1843
1844 /**
1845 * e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
1846 * @hw: pointer to the HW structure
1847 *
1848 * Checks if firmware is blocking the reset of the PHY.
1849 * This is a function pointer entry point only called by
1850 * reset routines.
1851 **/
e1000_check_reset_block_ich8lan(struct e1000_hw * hw)1852 static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
1853 {
1854 bool blocked = false;
1855 int i = 0;
1856
1857 while ((blocked = !(er32(FWSM) & E1000_ICH_FWSM_RSPCIPHY)) &&
1858 (i++ < 10))
1859 usleep_range(10000, 20000);
1860 return blocked ? E1000_BLK_PHY_RESET : 0;
1861 }
1862
1863 /**
1864 * e1000_write_smbus_addr - Write SMBus address to PHY needed during Sx states
1865 * @hw: pointer to the HW structure
1866 *
1867 * Assumes semaphore already acquired.
1868 *
1869 **/
e1000_write_smbus_addr(struct e1000_hw * hw)1870 static s32 e1000_write_smbus_addr(struct e1000_hw *hw)
1871 {
1872 u16 phy_data;
1873 u32 strap = er32(STRAP);
1874 u32 freq = (strap & E1000_STRAP_SMT_FREQ_MASK) >>
1875 E1000_STRAP_SMT_FREQ_SHIFT;
1876 s32 ret_val;
1877
1878 strap &= E1000_STRAP_SMBUS_ADDRESS_MASK;
1879
1880 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_SMB_ADDR, &phy_data);
1881 if (ret_val)
1882 return ret_val;
1883
1884 phy_data &= ~HV_SMB_ADDR_MASK;
1885 phy_data |= (strap >> E1000_STRAP_SMBUS_ADDRESS_SHIFT);
1886 phy_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID;
1887
1888 if (hw->phy.type == e1000_phy_i217) {
1889 /* Restore SMBus frequency */
1890 if (freq--) {
1891 phy_data &= ~HV_SMB_ADDR_FREQ_MASK;
1892 phy_data |= (freq & (1 << 0)) <<
1893 HV_SMB_ADDR_FREQ_LOW_SHIFT;
1894 phy_data |= (freq & (1 << 1)) <<
1895 (HV_SMB_ADDR_FREQ_HIGH_SHIFT - 1);
1896 } else {
1897 e_dbg("Unsupported SMB frequency in PHY\n");
1898 }
1899 }
1900
1901 return e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, phy_data);
1902 }
1903
1904 /**
1905 * e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration
1906 * @hw: pointer to the HW structure
1907 *
1908 * SW should configure the LCD from the NVM extended configuration region
1909 * as a workaround for certain parts.
1910 **/
e1000_sw_lcd_config_ich8lan(struct e1000_hw * hw)1911 static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
1912 {
1913 struct e1000_phy_info *phy = &hw->phy;
1914 u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask;
1915 s32 ret_val = 0;
1916 u16 word_addr, reg_data, reg_addr, phy_page = 0;
1917
1918 /* Initialize the PHY from the NVM on ICH platforms. This
1919 * is needed due to an issue where the NVM configuration is
1920 * not properly autoloaded after power transitions.
1921 * Therefore, after each PHY reset, we will load the
1922 * configuration data out of the NVM manually.
1923 */
1924 switch (hw->mac.type) {
1925 case e1000_ich8lan:
1926 if (phy->type != e1000_phy_igp_3)
1927 return ret_val;
1928
1929 if ((hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_AMT) ||
1930 (hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_C)) {
1931 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
1932 break;
1933 }
1934 /* Fall-thru */
1935 case e1000_pchlan:
1936 case e1000_pch2lan:
1937 case e1000_pch_lpt:
1938 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
1939 break;
1940 default:
1941 return ret_val;
1942 }
1943
1944 ret_val = hw->phy.ops.acquire(hw);
1945 if (ret_val)
1946 return ret_val;
1947
1948 data = er32(FEXTNVM);
1949 if (!(data & sw_cfg_mask))
1950 goto release;
1951
1952 /* Make sure HW does not configure LCD from PHY
1953 * extended configuration before SW configuration
1954 */
1955 data = er32(EXTCNF_CTRL);
1956 if ((hw->mac.type < e1000_pch2lan) &&
1957 (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE))
1958 goto release;
1959
1960 cnf_size = er32(EXTCNF_SIZE);
1961 cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
1962 cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
1963 if (!cnf_size)
1964 goto release;
1965
1966 cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
1967 cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
1968
1969 if (((hw->mac.type == e1000_pchlan) &&
1970 !(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)) ||
1971 (hw->mac.type > e1000_pchlan)) {
1972 /* HW configures the SMBus address and LEDs when the
1973 * OEM and LCD Write Enable bits are set in the NVM.
1974 * When both NVM bits are cleared, SW will configure
1975 * them instead.
1976 */
1977 ret_val = e1000_write_smbus_addr(hw);
1978 if (ret_val)
1979 goto release;
1980
1981 data = er32(LEDCTL);
1982 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_LED_CONFIG,
1983 (u16)data);
1984 if (ret_val)
1985 goto release;
1986 }
1987
1988 /* Configure LCD from extended configuration region. */
1989
1990 /* cnf_base_addr is in DWORD */
1991 word_addr = (u16)(cnf_base_addr << 1);
1992
1993 for (i = 0; i < cnf_size; i++) {
1994 ret_val = e1000_read_nvm(hw, (word_addr + i * 2), 1, ®_data);
1995 if (ret_val)
1996 goto release;
1997
1998 ret_val = e1000_read_nvm(hw, (word_addr + i * 2 + 1),
1999 1, ®_addr);
2000 if (ret_val)
2001 goto release;
2002
2003 /* Save off the PHY page for future writes. */
2004 if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
2005 phy_page = reg_data;
2006 continue;
2007 }
2008
2009 reg_addr &= PHY_REG_MASK;
2010 reg_addr |= phy_page;
2011
2012 ret_val = e1e_wphy_locked(hw, (u32)reg_addr, reg_data);
2013 if (ret_val)
2014 goto release;
2015 }
2016
2017 release:
2018 hw->phy.ops.release(hw);
2019 return ret_val;
2020 }
2021
2022 /**
2023 * e1000_k1_gig_workaround_hv - K1 Si workaround
2024 * @hw: pointer to the HW structure
2025 * @link: link up bool flag
2026 *
2027 * If K1 is enabled for 1Gbps, the MAC might stall when transitioning
2028 * from a lower speed. This workaround disables K1 whenever link is at 1Gig
2029 * If link is down, the function will restore the default K1 setting located
2030 * in the NVM.
2031 **/
e1000_k1_gig_workaround_hv(struct e1000_hw * hw,bool link)2032 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link)
2033 {
2034 s32 ret_val = 0;
2035 u16 status_reg = 0;
2036 bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled;
2037
2038 if (hw->mac.type != e1000_pchlan)
2039 return 0;
2040
2041 /* Wrap the whole flow with the sw flag */
2042 ret_val = hw->phy.ops.acquire(hw);
2043 if (ret_val)
2044 return ret_val;
2045
2046 /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */
2047 if (link) {
2048 if (hw->phy.type == e1000_phy_82578) {
2049 ret_val = e1e_rphy_locked(hw, BM_CS_STATUS,
2050 &status_reg);
2051 if (ret_val)
2052 goto release;
2053
2054 status_reg &= (BM_CS_STATUS_LINK_UP |
2055 BM_CS_STATUS_RESOLVED |
2056 BM_CS_STATUS_SPEED_MASK);
2057
2058 if (status_reg == (BM_CS_STATUS_LINK_UP |
2059 BM_CS_STATUS_RESOLVED |
2060 BM_CS_STATUS_SPEED_1000))
2061 k1_enable = false;
2062 }
2063
2064 if (hw->phy.type == e1000_phy_82577) {
2065 ret_val = e1e_rphy_locked(hw, HV_M_STATUS, &status_reg);
2066 if (ret_val)
2067 goto release;
2068
2069 status_reg &= (HV_M_STATUS_LINK_UP |
2070 HV_M_STATUS_AUTONEG_COMPLETE |
2071 HV_M_STATUS_SPEED_MASK);
2072
2073 if (status_reg == (HV_M_STATUS_LINK_UP |
2074 HV_M_STATUS_AUTONEG_COMPLETE |
2075 HV_M_STATUS_SPEED_1000))
2076 k1_enable = false;
2077 }
2078
2079 /* Link stall fix for link up */
2080 ret_val = e1e_wphy_locked(hw, PHY_REG(770, 19), 0x0100);
2081 if (ret_val)
2082 goto release;
2083
2084 } else {
2085 /* Link stall fix for link down */
2086 ret_val = e1e_wphy_locked(hw, PHY_REG(770, 19), 0x4100);
2087 if (ret_val)
2088 goto release;
2089 }
2090
2091 ret_val = e1000_configure_k1_ich8lan(hw, k1_enable);
2092
2093 release:
2094 hw->phy.ops.release(hw);
2095
2096 return ret_val;
2097 }
2098
2099 /**
2100 * e1000_configure_k1_ich8lan - Configure K1 power state
2101 * @hw: pointer to the HW structure
2102 * @enable: K1 state to configure
2103 *
2104 * Configure the K1 power state based on the provided parameter.
2105 * Assumes semaphore already acquired.
2106 *
2107 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
2108 **/
e1000_configure_k1_ich8lan(struct e1000_hw * hw,bool k1_enable)2109 s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable)
2110 {
2111 s32 ret_val;
2112 u32 ctrl_reg = 0;
2113 u32 ctrl_ext = 0;
2114 u32 reg = 0;
2115 u16 kmrn_reg = 0;
2116
2117 ret_val = e1000e_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
2118 &kmrn_reg);
2119 if (ret_val)
2120 return ret_val;
2121
2122 if (k1_enable)
2123 kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE;
2124 else
2125 kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE;
2126
2127 ret_val = e1000e_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
2128 kmrn_reg);
2129 if (ret_val)
2130 return ret_val;
2131
2132 usleep_range(20, 40);
2133 ctrl_ext = er32(CTRL_EXT);
2134 ctrl_reg = er32(CTRL);
2135
2136 reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
2137 reg |= E1000_CTRL_FRCSPD;
2138 ew32(CTRL, reg);
2139
2140 ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS);
2141 e1e_flush();
2142 usleep_range(20, 40);
2143 ew32(CTRL, ctrl_reg);
2144 ew32(CTRL_EXT, ctrl_ext);
2145 e1e_flush();
2146 usleep_range(20, 40);
2147
2148 return 0;
2149 }
2150
2151 /**
2152 * e1000_oem_bits_config_ich8lan - SW-based LCD Configuration
2153 * @hw: pointer to the HW structure
2154 * @d0_state: boolean if entering d0 or d3 device state
2155 *
2156 * SW will configure Gbe Disable and LPLU based on the NVM. The four bits are
2157 * collectively called OEM bits. The OEM Write Enable bit and SW Config bit
2158 * in NVM determines whether HW should configure LPLU and Gbe Disable.
2159 **/
e1000_oem_bits_config_ich8lan(struct e1000_hw * hw,bool d0_state)2160 static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)
2161 {
2162 s32 ret_val = 0;
2163 u32 mac_reg;
2164 u16 oem_reg;
2165
2166 if (hw->mac.type < e1000_pchlan)
2167 return ret_val;
2168
2169 ret_val = hw->phy.ops.acquire(hw);
2170 if (ret_val)
2171 return ret_val;
2172
2173 if (hw->mac.type == e1000_pchlan) {
2174 mac_reg = er32(EXTCNF_CTRL);
2175 if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)
2176 goto release;
2177 }
2178
2179 mac_reg = er32(FEXTNVM);
2180 if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M))
2181 goto release;
2182
2183 mac_reg = er32(PHY_CTRL);
2184
2185 ret_val = e1e_rphy_locked(hw, HV_OEM_BITS, &oem_reg);
2186 if (ret_val)
2187 goto release;
2188
2189 oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU);
2190
2191 if (d0_state) {
2192 if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE)
2193 oem_reg |= HV_OEM_BITS_GBE_DIS;
2194
2195 if (mac_reg & E1000_PHY_CTRL_D0A_LPLU)
2196 oem_reg |= HV_OEM_BITS_LPLU;
2197 } else {
2198 if (mac_reg & (E1000_PHY_CTRL_GBE_DISABLE |
2199 E1000_PHY_CTRL_NOND0A_GBE_DISABLE))
2200 oem_reg |= HV_OEM_BITS_GBE_DIS;
2201
2202 if (mac_reg & (E1000_PHY_CTRL_D0A_LPLU |
2203 E1000_PHY_CTRL_NOND0A_LPLU))
2204 oem_reg |= HV_OEM_BITS_LPLU;
2205 }
2206
2207 /* Set Restart auto-neg to activate the bits */
2208 if ((d0_state || (hw->mac.type != e1000_pchlan)) &&
2209 !hw->phy.ops.check_reset_block(hw))
2210 oem_reg |= HV_OEM_BITS_RESTART_AN;
2211
2212 ret_val = e1e_wphy_locked(hw, HV_OEM_BITS, oem_reg);
2213
2214 release:
2215 hw->phy.ops.release(hw);
2216
2217 return ret_val;
2218 }
2219
2220 /**
2221 * e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode
2222 * @hw: pointer to the HW structure
2223 **/
e1000_set_mdio_slow_mode_hv(struct e1000_hw * hw)2224 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw)
2225 {
2226 s32 ret_val;
2227 u16 data;
2228
2229 ret_val = e1e_rphy(hw, HV_KMRN_MODE_CTRL, &data);
2230 if (ret_val)
2231 return ret_val;
2232
2233 data |= HV_KMRN_MDIO_SLOW;
2234
2235 ret_val = e1e_wphy(hw, HV_KMRN_MODE_CTRL, data);
2236
2237 return ret_val;
2238 }
2239
2240 /**
2241 * e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be
2242 * done after every PHY reset.
2243 **/
e1000_hv_phy_workarounds_ich8lan(struct e1000_hw * hw)2244 static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
2245 {
2246 s32 ret_val = 0;
2247 u16 phy_data;
2248
2249 if (hw->mac.type != e1000_pchlan)
2250 return 0;
2251
2252 /* Set MDIO slow mode before any other MDIO access */
2253 if (hw->phy.type == e1000_phy_82577) {
2254 ret_val = e1000_set_mdio_slow_mode_hv(hw);
2255 if (ret_val)
2256 return ret_val;
2257 }
2258
2259 if (((hw->phy.type == e1000_phy_82577) &&
2260 ((hw->phy.revision == 1) || (hw->phy.revision == 2))) ||
2261 ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) {
2262 /* Disable generation of early preamble */
2263 ret_val = e1e_wphy(hw, PHY_REG(769, 25), 0x4431);
2264 if (ret_val)
2265 return ret_val;
2266
2267 /* Preamble tuning for SSC */
2268 ret_val = e1e_wphy(hw, HV_KMRN_FIFO_CTRLSTA, 0xA204);
2269 if (ret_val)
2270 return ret_val;
2271 }
2272
2273 if (hw->phy.type == e1000_phy_82578) {
2274 /* Return registers to default by doing a soft reset then
2275 * writing 0x3140 to the control register.
2276 */
2277 if (hw->phy.revision < 2) {
2278 e1000e_phy_sw_reset(hw);
2279 ret_val = e1e_wphy(hw, MII_BMCR, 0x3140);
2280 }
2281 }
2282
2283 /* Select page 0 */
2284 ret_val = hw->phy.ops.acquire(hw);
2285 if (ret_val)
2286 return ret_val;
2287
2288 hw->phy.addr = 1;
2289 ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
2290 hw->phy.ops.release(hw);
2291 if (ret_val)
2292 return ret_val;
2293
2294 /* Configure the K1 Si workaround during phy reset assuming there is
2295 * link so that it disables K1 if link is in 1Gbps.
2296 */
2297 ret_val = e1000_k1_gig_workaround_hv(hw, true);
2298 if (ret_val)
2299 return ret_val;
2300
2301 /* Workaround for link disconnects on a busy hub in half duplex */
2302 ret_val = hw->phy.ops.acquire(hw);
2303 if (ret_val)
2304 return ret_val;
2305 ret_val = e1e_rphy_locked(hw, BM_PORT_GEN_CFG, &phy_data);
2306 if (ret_val)
2307 goto release;
2308 ret_val = e1e_wphy_locked(hw, BM_PORT_GEN_CFG, phy_data & 0x00FF);
2309 if (ret_val)
2310 goto release;
2311
2312 /* set MSE higher to enable link to stay up when noise is high */
2313 ret_val = e1000_write_emi_reg_locked(hw, I82577_MSE_THRESHOLD, 0x0034);
2314 release:
2315 hw->phy.ops.release(hw);
2316
2317 return ret_val;
2318 }
2319
2320 /**
2321 * e1000_copy_rx_addrs_to_phy_ich8lan - Copy Rx addresses from MAC to PHY
2322 * @hw: pointer to the HW structure
2323 **/
e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw * hw)2324 void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw)
2325 {
2326 u32 mac_reg;
2327 u16 i, phy_reg = 0;
2328 s32 ret_val;
2329
2330 ret_val = hw->phy.ops.acquire(hw);
2331 if (ret_val)
2332 return;
2333 ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2334 if (ret_val)
2335 goto release;
2336
2337 /* Copy both RAL/H (rar_entry_count) and SHRAL/H to PHY */
2338 for (i = 0; i < (hw->mac.rar_entry_count); i++) {
2339 mac_reg = er32(RAL(i));
2340 hw->phy.ops.write_reg_page(hw, BM_RAR_L(i),
2341 (u16)(mac_reg & 0xFFFF));
2342 hw->phy.ops.write_reg_page(hw, BM_RAR_M(i),
2343 (u16)((mac_reg >> 16) & 0xFFFF));
2344
2345 mac_reg = er32(RAH(i));
2346 hw->phy.ops.write_reg_page(hw, BM_RAR_H(i),
2347 (u16)(mac_reg & 0xFFFF));
2348 hw->phy.ops.write_reg_page(hw, BM_RAR_CTRL(i),
2349 (u16)((mac_reg & E1000_RAH_AV)
2350 >> 16));
2351 }
2352
2353 e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2354
2355 release:
2356 hw->phy.ops.release(hw);
2357 }
2358
2359 /**
2360 * e1000_lv_jumbo_workaround_ich8lan - required for jumbo frame operation
2361 * with 82579 PHY
2362 * @hw: pointer to the HW structure
2363 * @enable: flag to enable/disable workaround when enabling/disabling jumbos
2364 **/
e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw * hw,bool enable)2365 s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable)
2366 {
2367 s32 ret_val = 0;
2368 u16 phy_reg, data;
2369 u32 mac_reg;
2370 u16 i;
2371
2372 if (hw->mac.type < e1000_pch2lan)
2373 return 0;
2374
2375 /* disable Rx path while enabling/disabling workaround */
2376 e1e_rphy(hw, PHY_REG(769, 20), &phy_reg);
2377 ret_val = e1e_wphy(hw, PHY_REG(769, 20), phy_reg | (1 << 14));
2378 if (ret_val)
2379 return ret_val;
2380
2381 if (enable) {
2382 /* Write Rx addresses (rar_entry_count for RAL/H, and
2383 * SHRAL/H) and initial CRC values to the MAC
2384 */
2385 for (i = 0; i < hw->mac.rar_entry_count; i++) {
2386 u8 mac_addr[ETH_ALEN] = { 0 };
2387 u32 addr_high, addr_low;
2388
2389 addr_high = er32(RAH(i));
2390 if (!(addr_high & E1000_RAH_AV))
2391 continue;
2392 addr_low = er32(RAL(i));
2393 mac_addr[0] = (addr_low & 0xFF);
2394 mac_addr[1] = ((addr_low >> 8) & 0xFF);
2395 mac_addr[2] = ((addr_low >> 16) & 0xFF);
2396 mac_addr[3] = ((addr_low >> 24) & 0xFF);
2397 mac_addr[4] = (addr_high & 0xFF);
2398 mac_addr[5] = ((addr_high >> 8) & 0xFF);
2399
2400 ew32(PCH_RAICC(i), ~ether_crc_le(ETH_ALEN, mac_addr));
2401 }
2402
2403 /* Write Rx addresses to the PHY */
2404 e1000_copy_rx_addrs_to_phy_ich8lan(hw);
2405
2406 /* Enable jumbo frame workaround in the MAC */
2407 mac_reg = er32(FFLT_DBG);
2408 mac_reg &= ~(1 << 14);
2409 mac_reg |= (7 << 15);
2410 ew32(FFLT_DBG, mac_reg);
2411
2412 mac_reg = er32(RCTL);
2413 mac_reg |= E1000_RCTL_SECRC;
2414 ew32(RCTL, mac_reg);
2415
2416 ret_val = e1000e_read_kmrn_reg(hw,
2417 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2418 &data);
2419 if (ret_val)
2420 return ret_val;
2421 ret_val = e1000e_write_kmrn_reg(hw,
2422 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2423 data | (1 << 0));
2424 if (ret_val)
2425 return ret_val;
2426 ret_val = e1000e_read_kmrn_reg(hw,
2427 E1000_KMRNCTRLSTA_HD_CTRL,
2428 &data);
2429 if (ret_val)
2430 return ret_val;
2431 data &= ~(0xF << 8);
2432 data |= (0xB << 8);
2433 ret_val = e1000e_write_kmrn_reg(hw,
2434 E1000_KMRNCTRLSTA_HD_CTRL,
2435 data);
2436 if (ret_val)
2437 return ret_val;
2438
2439 /* Enable jumbo frame workaround in the PHY */
2440 e1e_rphy(hw, PHY_REG(769, 23), &data);
2441 data &= ~(0x7F << 5);
2442 data |= (0x37 << 5);
2443 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data);
2444 if (ret_val)
2445 return ret_val;
2446 e1e_rphy(hw, PHY_REG(769, 16), &data);
2447 data &= ~(1 << 13);
2448 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
2449 if (ret_val)
2450 return ret_val;
2451 e1e_rphy(hw, PHY_REG(776, 20), &data);
2452 data &= ~(0x3FF << 2);
2453 data |= (E1000_TX_PTR_GAP << 2);
2454 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data);
2455 if (ret_val)
2456 return ret_val;
2457 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0xF100);
2458 if (ret_val)
2459 return ret_val;
2460 e1e_rphy(hw, HV_PM_CTRL, &data);
2461 ret_val = e1e_wphy(hw, HV_PM_CTRL, data | (1 << 10));
2462 if (ret_val)
2463 return ret_val;
2464 } else {
2465 /* Write MAC register values back to h/w defaults */
2466 mac_reg = er32(FFLT_DBG);
2467 mac_reg &= ~(0xF << 14);
2468 ew32(FFLT_DBG, mac_reg);
2469
2470 mac_reg = er32(RCTL);
2471 mac_reg &= ~E1000_RCTL_SECRC;
2472 ew32(RCTL, mac_reg);
2473
2474 ret_val = e1000e_read_kmrn_reg(hw,
2475 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2476 &data);
2477 if (ret_val)
2478 return ret_val;
2479 ret_val = e1000e_write_kmrn_reg(hw,
2480 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2481 data & ~(1 << 0));
2482 if (ret_val)
2483 return ret_val;
2484 ret_val = e1000e_read_kmrn_reg(hw,
2485 E1000_KMRNCTRLSTA_HD_CTRL,
2486 &data);
2487 if (ret_val)
2488 return ret_val;
2489 data &= ~(0xF << 8);
2490 data |= (0xB << 8);
2491 ret_val = e1000e_write_kmrn_reg(hw,
2492 E1000_KMRNCTRLSTA_HD_CTRL,
2493 data);
2494 if (ret_val)
2495 return ret_val;
2496
2497 /* Write PHY register values back to h/w defaults */
2498 e1e_rphy(hw, PHY_REG(769, 23), &data);
2499 data &= ~(0x7F << 5);
2500 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data);
2501 if (ret_val)
2502 return ret_val;
2503 e1e_rphy(hw, PHY_REG(769, 16), &data);
2504 data |= (1 << 13);
2505 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
2506 if (ret_val)
2507 return ret_val;
2508 e1e_rphy(hw, PHY_REG(776, 20), &data);
2509 data &= ~(0x3FF << 2);
2510 data |= (0x8 << 2);
2511 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data);
2512 if (ret_val)
2513 return ret_val;
2514 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0x7E00);
2515 if (ret_val)
2516 return ret_val;
2517 e1e_rphy(hw, HV_PM_CTRL, &data);
2518 ret_val = e1e_wphy(hw, HV_PM_CTRL, data & ~(1 << 10));
2519 if (ret_val)
2520 return ret_val;
2521 }
2522
2523 /* re-enable Rx path after enabling/disabling workaround */
2524 return e1e_wphy(hw, PHY_REG(769, 20), phy_reg & ~(1 << 14));
2525 }
2526
2527 /**
2528 * e1000_lv_phy_workarounds_ich8lan - A series of Phy workarounds to be
2529 * done after every PHY reset.
2530 **/
e1000_lv_phy_workarounds_ich8lan(struct e1000_hw * hw)2531 static s32 e1000_lv_phy_workarounds_ich8lan(struct e1000_hw *hw)
2532 {
2533 s32 ret_val = 0;
2534
2535 if (hw->mac.type != e1000_pch2lan)
2536 return 0;
2537
2538 /* Set MDIO slow mode before any other MDIO access */
2539 ret_val = e1000_set_mdio_slow_mode_hv(hw);
2540 if (ret_val)
2541 return ret_val;
2542
2543 ret_val = hw->phy.ops.acquire(hw);
2544 if (ret_val)
2545 return ret_val;
2546 /* set MSE higher to enable link to stay up when noise is high */
2547 ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_THRESHOLD, 0x0034);
2548 if (ret_val)
2549 goto release;
2550 /* drop link after 5 times MSE threshold was reached */
2551 ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_LINK_DOWN, 0x0005);
2552 release:
2553 hw->phy.ops.release(hw);
2554
2555 return ret_val;
2556 }
2557
2558 /**
2559 * e1000_k1_gig_workaround_lv - K1 Si workaround
2560 * @hw: pointer to the HW structure
2561 *
2562 * Workaround to set the K1 beacon duration for 82579 parts in 10Mbps
2563 * Disable K1 in 1000Mbps and 100Mbps
2564 **/
e1000_k1_workaround_lv(struct e1000_hw * hw)2565 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw)
2566 {
2567 s32 ret_val = 0;
2568 u16 status_reg = 0;
2569
2570 if (hw->mac.type != e1000_pch2lan)
2571 return 0;
2572
2573 /* Set K1 beacon duration based on 10Mbs speed */
2574 ret_val = e1e_rphy(hw, HV_M_STATUS, &status_reg);
2575 if (ret_val)
2576 return ret_val;
2577
2578 if ((status_reg & (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE))
2579 == (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) {
2580 if (status_reg &
2581 (HV_M_STATUS_SPEED_1000 | HV_M_STATUS_SPEED_100)) {
2582 u16 pm_phy_reg;
2583
2584 /* LV 1G/100 Packet drop issue wa */
2585 ret_val = e1e_rphy(hw, HV_PM_CTRL, &pm_phy_reg);
2586 if (ret_val)
2587 return ret_val;
2588 pm_phy_reg &= ~HV_PM_CTRL_K1_ENABLE;
2589 ret_val = e1e_wphy(hw, HV_PM_CTRL, pm_phy_reg);
2590 if (ret_val)
2591 return ret_val;
2592 } else {
2593 u32 mac_reg;
2594
2595 mac_reg = er32(FEXTNVM4);
2596 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
2597 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_16USEC;
2598 ew32(FEXTNVM4, mac_reg);
2599 }
2600 }
2601
2602 return ret_val;
2603 }
2604
2605 /**
2606 * e1000_gate_hw_phy_config_ich8lan - disable PHY config via hardware
2607 * @hw: pointer to the HW structure
2608 * @gate: boolean set to true to gate, false to ungate
2609 *
2610 * Gate/ungate the automatic PHY configuration via hardware; perform
2611 * the configuration via software instead.
2612 **/
e1000_gate_hw_phy_config_ich8lan(struct e1000_hw * hw,bool gate)2613 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate)
2614 {
2615 u32 extcnf_ctrl;
2616
2617 if (hw->mac.type < e1000_pch2lan)
2618 return;
2619
2620 extcnf_ctrl = er32(EXTCNF_CTRL);
2621
2622 if (gate)
2623 extcnf_ctrl |= E1000_EXTCNF_CTRL_GATE_PHY_CFG;
2624 else
2625 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_GATE_PHY_CFG;
2626
2627 ew32(EXTCNF_CTRL, extcnf_ctrl);
2628 }
2629
2630 /**
2631 * e1000_lan_init_done_ich8lan - Check for PHY config completion
2632 * @hw: pointer to the HW structure
2633 *
2634 * Check the appropriate indication the MAC has finished configuring the
2635 * PHY after a software reset.
2636 **/
e1000_lan_init_done_ich8lan(struct e1000_hw * hw)2637 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw)
2638 {
2639 u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT;
2640
2641 /* Wait for basic configuration completes before proceeding */
2642 do {
2643 data = er32(STATUS);
2644 data &= E1000_STATUS_LAN_INIT_DONE;
2645 usleep_range(100, 200);
2646 } while ((!data) && --loop);
2647
2648 /* If basic configuration is incomplete before the above loop
2649 * count reaches 0, loading the configuration from NVM will
2650 * leave the PHY in a bad state possibly resulting in no link.
2651 */
2652 if (loop == 0)
2653 e_dbg("LAN_INIT_DONE not set, increase timeout\n");
2654
2655 /* Clear the Init Done bit for the next init event */
2656 data = er32(STATUS);
2657 data &= ~E1000_STATUS_LAN_INIT_DONE;
2658 ew32(STATUS, data);
2659 }
2660
2661 /**
2662 * e1000_post_phy_reset_ich8lan - Perform steps required after a PHY reset
2663 * @hw: pointer to the HW structure
2664 **/
e1000_post_phy_reset_ich8lan(struct e1000_hw * hw)2665 static s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw)
2666 {
2667 s32 ret_val = 0;
2668 u16 reg;
2669
2670 if (hw->phy.ops.check_reset_block(hw))
2671 return 0;
2672
2673 /* Allow time for h/w to get to quiescent state after reset */
2674 usleep_range(10000, 20000);
2675
2676 /* Perform any necessary post-reset workarounds */
2677 switch (hw->mac.type) {
2678 case e1000_pchlan:
2679 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
2680 if (ret_val)
2681 return ret_val;
2682 break;
2683 case e1000_pch2lan:
2684 ret_val = e1000_lv_phy_workarounds_ich8lan(hw);
2685 if (ret_val)
2686 return ret_val;
2687 break;
2688 default:
2689 break;
2690 }
2691
2692 /* Clear the host wakeup bit after lcd reset */
2693 if (hw->mac.type >= e1000_pchlan) {
2694 e1e_rphy(hw, BM_PORT_GEN_CFG, ®);
2695 reg &= ~BM_WUC_HOST_WU_BIT;
2696 e1e_wphy(hw, BM_PORT_GEN_CFG, reg);
2697 }
2698
2699 /* Configure the LCD with the extended configuration region in NVM */
2700 ret_val = e1000_sw_lcd_config_ich8lan(hw);
2701 if (ret_val)
2702 return ret_val;
2703
2704 /* Configure the LCD with the OEM bits in NVM */
2705 ret_val = e1000_oem_bits_config_ich8lan(hw, true);
2706
2707 if (hw->mac.type == e1000_pch2lan) {
2708 /* Ungate automatic PHY configuration on non-managed 82579 */
2709 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
2710 usleep_range(10000, 20000);
2711 e1000_gate_hw_phy_config_ich8lan(hw, false);
2712 }
2713
2714 /* Set EEE LPI Update Timer to 200usec */
2715 ret_val = hw->phy.ops.acquire(hw);
2716 if (ret_val)
2717 return ret_val;
2718 ret_val = e1000_write_emi_reg_locked(hw,
2719 I82579_LPI_UPDATE_TIMER,
2720 0x1387);
2721 hw->phy.ops.release(hw);
2722 }
2723
2724 return ret_val;
2725 }
2726
2727 /**
2728 * e1000_phy_hw_reset_ich8lan - Performs a PHY reset
2729 * @hw: pointer to the HW structure
2730 *
2731 * Resets the PHY
2732 * This is a function pointer entry point called by drivers
2733 * or other shared routines.
2734 **/
e1000_phy_hw_reset_ich8lan(struct e1000_hw * hw)2735 static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
2736 {
2737 s32 ret_val = 0;
2738
2739 /* Gate automatic PHY configuration by hardware on non-managed 82579 */
2740 if ((hw->mac.type == e1000_pch2lan) &&
2741 !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
2742 e1000_gate_hw_phy_config_ich8lan(hw, true);
2743
2744 ret_val = e1000e_phy_hw_reset_generic(hw);
2745 if (ret_val)
2746 return ret_val;
2747
2748 return e1000_post_phy_reset_ich8lan(hw);
2749 }
2750
2751 /**
2752 * e1000_set_lplu_state_pchlan - Set Low Power Link Up state
2753 * @hw: pointer to the HW structure
2754 * @active: true to enable LPLU, false to disable
2755 *
2756 * Sets the LPLU state according to the active flag. For PCH, if OEM write
2757 * bit are disabled in the NVM, writing the LPLU bits in the MAC will not set
2758 * the phy speed. This function will manually set the LPLU bit and restart
2759 * auto-neg as hw would do. D3 and D0 LPLU will call the same function
2760 * since it configures the same bit.
2761 **/
e1000_set_lplu_state_pchlan(struct e1000_hw * hw,bool active)2762 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active)
2763 {
2764 s32 ret_val;
2765 u16 oem_reg;
2766
2767 ret_val = e1e_rphy(hw, HV_OEM_BITS, &oem_reg);
2768 if (ret_val)
2769 return ret_val;
2770
2771 if (active)
2772 oem_reg |= HV_OEM_BITS_LPLU;
2773 else
2774 oem_reg &= ~HV_OEM_BITS_LPLU;
2775
2776 if (!hw->phy.ops.check_reset_block(hw))
2777 oem_reg |= HV_OEM_BITS_RESTART_AN;
2778
2779 return e1e_wphy(hw, HV_OEM_BITS, oem_reg);
2780 }
2781
2782 /**
2783 * e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
2784 * @hw: pointer to the HW structure
2785 * @active: true to enable LPLU, false to disable
2786 *
2787 * Sets the LPLU D0 state according to the active flag. When
2788 * activating LPLU this function also disables smart speed
2789 * and vice versa. LPLU will not be activated unless the
2790 * device autonegotiation advertisement meets standards of
2791 * either 10 or 10/100 or 10/100/1000 at all duplexes.
2792 * This is a function pointer entry point only called by
2793 * PHY setup routines.
2794 **/
e1000_set_d0_lplu_state_ich8lan(struct e1000_hw * hw,bool active)2795 static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
2796 {
2797 struct e1000_phy_info *phy = &hw->phy;
2798 u32 phy_ctrl;
2799 s32 ret_val = 0;
2800 u16 data;
2801
2802 if (phy->type == e1000_phy_ife)
2803 return 0;
2804
2805 phy_ctrl = er32(PHY_CTRL);
2806
2807 if (active) {
2808 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
2809 ew32(PHY_CTRL, phy_ctrl);
2810
2811 if (phy->type != e1000_phy_igp_3)
2812 return 0;
2813
2814 /* Call gig speed drop workaround on LPLU before accessing
2815 * any PHY registers
2816 */
2817 if (hw->mac.type == e1000_ich8lan)
2818 e1000e_gig_downshift_workaround_ich8lan(hw);
2819
2820 /* When LPLU is enabled, we should disable SmartSpeed */
2821 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
2822 if (ret_val)
2823 return ret_val;
2824 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2825 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
2826 if (ret_val)
2827 return ret_val;
2828 } else {
2829 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
2830 ew32(PHY_CTRL, phy_ctrl);
2831
2832 if (phy->type != e1000_phy_igp_3)
2833 return 0;
2834
2835 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
2836 * during Dx states where the power conservation is most
2837 * important. During driver activity we should enable
2838 * SmartSpeed, so performance is maintained.
2839 */
2840 if (phy->smart_speed == e1000_smart_speed_on) {
2841 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2842 &data);
2843 if (ret_val)
2844 return ret_val;
2845
2846 data |= IGP01E1000_PSCFR_SMART_SPEED;
2847 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2848 data);
2849 if (ret_val)
2850 return ret_val;
2851 } else if (phy->smart_speed == e1000_smart_speed_off) {
2852 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2853 &data);
2854 if (ret_val)
2855 return ret_val;
2856
2857 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2858 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2859 data);
2860 if (ret_val)
2861 return ret_val;
2862 }
2863 }
2864
2865 return 0;
2866 }
2867
2868 /**
2869 * e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
2870 * @hw: pointer to the HW structure
2871 * @active: true to enable LPLU, false to disable
2872 *
2873 * Sets the LPLU D3 state according to the active flag. When
2874 * activating LPLU this function also disables smart speed
2875 * and vice versa. LPLU will not be activated unless the
2876 * device autonegotiation advertisement meets standards of
2877 * either 10 or 10/100 or 10/100/1000 at all duplexes.
2878 * This is a function pointer entry point only called by
2879 * PHY setup routines.
2880 **/
e1000_set_d3_lplu_state_ich8lan(struct e1000_hw * hw,bool active)2881 static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
2882 {
2883 struct e1000_phy_info *phy = &hw->phy;
2884 u32 phy_ctrl;
2885 s32 ret_val = 0;
2886 u16 data;
2887
2888 phy_ctrl = er32(PHY_CTRL);
2889
2890 if (!active) {
2891 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
2892 ew32(PHY_CTRL, phy_ctrl);
2893
2894 if (phy->type != e1000_phy_igp_3)
2895 return 0;
2896
2897 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
2898 * during Dx states where the power conservation is most
2899 * important. During driver activity we should enable
2900 * SmartSpeed, so performance is maintained.
2901 */
2902 if (phy->smart_speed == e1000_smart_speed_on) {
2903 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2904 &data);
2905 if (ret_val)
2906 return ret_val;
2907
2908 data |= IGP01E1000_PSCFR_SMART_SPEED;
2909 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2910 data);
2911 if (ret_val)
2912 return ret_val;
2913 } else if (phy->smart_speed == e1000_smart_speed_off) {
2914 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2915 &data);
2916 if (ret_val)
2917 return ret_val;
2918
2919 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2920 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2921 data);
2922 if (ret_val)
2923 return ret_val;
2924 }
2925 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
2926 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
2927 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
2928 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
2929 ew32(PHY_CTRL, phy_ctrl);
2930
2931 if (phy->type != e1000_phy_igp_3)
2932 return 0;
2933
2934 /* Call gig speed drop workaround on LPLU before accessing
2935 * any PHY registers
2936 */
2937 if (hw->mac.type == e1000_ich8lan)
2938 e1000e_gig_downshift_workaround_ich8lan(hw);
2939
2940 /* When LPLU is enabled, we should disable SmartSpeed */
2941 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
2942 if (ret_val)
2943 return ret_val;
2944
2945 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2946 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
2947 }
2948
2949 return ret_val;
2950 }
2951
2952 /**
2953 * e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
2954 * @hw: pointer to the HW structure
2955 * @bank: pointer to the variable that returns the active bank
2956 *
2957 * Reads signature byte from the NVM using the flash access registers.
2958 * Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank.
2959 **/
e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw * hw,u32 * bank)2960 static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
2961 {
2962 u32 eecd;
2963 struct e1000_nvm_info *nvm = &hw->nvm;
2964 u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);
2965 u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;
2966 u8 sig_byte = 0;
2967 s32 ret_val;
2968
2969 switch (hw->mac.type) {
2970 case e1000_ich8lan:
2971 case e1000_ich9lan:
2972 eecd = er32(EECD);
2973 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) ==
2974 E1000_EECD_SEC1VAL_VALID_MASK) {
2975 if (eecd & E1000_EECD_SEC1VAL)
2976 *bank = 1;
2977 else
2978 *bank = 0;
2979
2980 return 0;
2981 }
2982 e_dbg("Unable to determine valid NVM bank via EEC - reading flash signature\n");
2983 /* fall-thru */
2984 default:
2985 /* set bank to 0 in case flash read fails */
2986 *bank = 0;
2987
2988 /* Check bank 0 */
2989 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset,
2990 &sig_byte);
2991 if (ret_val)
2992 return ret_val;
2993 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
2994 E1000_ICH_NVM_SIG_VALUE) {
2995 *bank = 0;
2996 return 0;
2997 }
2998
2999 /* Check bank 1 */
3000 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset +
3001 bank1_offset,
3002 &sig_byte);
3003 if (ret_val)
3004 return ret_val;
3005 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3006 E1000_ICH_NVM_SIG_VALUE) {
3007 *bank = 1;
3008 return 0;
3009 }
3010
3011 e_dbg("ERROR: No valid NVM bank present\n");
3012 return -E1000_ERR_NVM;
3013 }
3014 }
3015
3016 /**
3017 * e1000_read_nvm_ich8lan - Read word(s) from the NVM
3018 * @hw: pointer to the HW structure
3019 * @offset: The offset (in bytes) of the word(s) to read.
3020 * @words: Size of data to read in words
3021 * @data: Pointer to the word(s) to read at offset.
3022 *
3023 * Reads a word(s) from the NVM using the flash access registers.
3024 **/
e1000_read_nvm_ich8lan(struct e1000_hw * hw,u16 offset,u16 words,u16 * data)3025 static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
3026 u16 *data)
3027 {
3028 struct e1000_nvm_info *nvm = &hw->nvm;
3029 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3030 u32 act_offset;
3031 s32 ret_val = 0;
3032 u32 bank = 0;
3033 u16 i, word;
3034
3035 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
3036 (words == 0)) {
3037 e_dbg("nvm parameter(s) out of bounds\n");
3038 ret_val = -E1000_ERR_NVM;
3039 goto out;
3040 }
3041
3042 nvm->ops.acquire(hw);
3043
3044 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3045 if (ret_val) {
3046 e_dbg("Could not detect valid bank, assuming bank 0\n");
3047 bank = 0;
3048 }
3049
3050 act_offset = (bank) ? nvm->flash_bank_size : 0;
3051 act_offset += offset;
3052
3053 ret_val = 0;
3054 for (i = 0; i < words; i++) {
3055 if (dev_spec->shadow_ram[offset + i].modified) {
3056 data[i] = dev_spec->shadow_ram[offset + i].value;
3057 } else {
3058 ret_val = e1000_read_flash_word_ich8lan(hw,
3059 act_offset + i,
3060 &word);
3061 if (ret_val)
3062 break;
3063 data[i] = word;
3064 }
3065 }
3066
3067 nvm->ops.release(hw);
3068
3069 out:
3070 if (ret_val)
3071 e_dbg("NVM read error: %d\n", ret_val);
3072
3073 return ret_val;
3074 }
3075
3076 /**
3077 * e1000_flash_cycle_init_ich8lan - Initialize flash
3078 * @hw: pointer to the HW structure
3079 *
3080 * This function does initial flash setup so that a new read/write/erase cycle
3081 * can be started.
3082 **/
e1000_flash_cycle_init_ich8lan(struct e1000_hw * hw)3083 static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
3084 {
3085 union ich8_hws_flash_status hsfsts;
3086 s32 ret_val = -E1000_ERR_NVM;
3087
3088 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3089
3090 /* Check if the flash descriptor is valid */
3091 if (!hsfsts.hsf_status.fldesvalid) {
3092 e_dbg("Flash descriptor invalid. SW Sequencing must be used.\n");
3093 return -E1000_ERR_NVM;
3094 }
3095
3096 /* Clear FCERR and DAEL in hw status by writing 1 */
3097 hsfsts.hsf_status.flcerr = 1;
3098 hsfsts.hsf_status.dael = 1;
3099
3100 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
3101
3102 /* Either we should have a hardware SPI cycle in progress
3103 * bit to check against, in order to start a new cycle or
3104 * FDONE bit should be changed in the hardware so that it
3105 * is 1 after hardware reset, which can then be used as an
3106 * indication whether a cycle is in progress or has been
3107 * completed.
3108 */
3109
3110 if (!hsfsts.hsf_status.flcinprog) {
3111 /* There is no cycle running at present,
3112 * so we can start a cycle.
3113 * Begin by setting Flash Cycle Done.
3114 */
3115 hsfsts.hsf_status.flcdone = 1;
3116 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
3117 ret_val = 0;
3118 } else {
3119 s32 i;
3120
3121 /* Otherwise poll for sometime so the current
3122 * cycle has a chance to end before giving up.
3123 */
3124 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
3125 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3126 if (!hsfsts.hsf_status.flcinprog) {
3127 ret_val = 0;
3128 break;
3129 }
3130 udelay(1);
3131 }
3132 if (!ret_val) {
3133 /* Successful in waiting for previous cycle to timeout,
3134 * now set the Flash Cycle Done.
3135 */
3136 hsfsts.hsf_status.flcdone = 1;
3137 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
3138 } else {
3139 e_dbg("Flash controller busy, cannot get access\n");
3140 }
3141 }
3142
3143 return ret_val;
3144 }
3145
3146 /**
3147 * e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
3148 * @hw: pointer to the HW structure
3149 * @timeout: maximum time to wait for completion
3150 *
3151 * This function starts a flash cycle and waits for its completion.
3152 **/
e1000_flash_cycle_ich8lan(struct e1000_hw * hw,u32 timeout)3153 static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
3154 {
3155 union ich8_hws_flash_ctrl hsflctl;
3156 union ich8_hws_flash_status hsfsts;
3157 u32 i = 0;
3158
3159 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
3160 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
3161 hsflctl.hsf_ctrl.flcgo = 1;
3162 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
3163
3164 /* wait till FDONE bit is set to 1 */
3165 do {
3166 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3167 if (hsfsts.hsf_status.flcdone)
3168 break;
3169 udelay(1);
3170 } while (i++ < timeout);
3171
3172 if (hsfsts.hsf_status.flcdone && !hsfsts.hsf_status.flcerr)
3173 return 0;
3174
3175 return -E1000_ERR_NVM;
3176 }
3177
3178 /**
3179 * e1000_read_flash_word_ich8lan - Read word from flash
3180 * @hw: pointer to the HW structure
3181 * @offset: offset to data location
3182 * @data: pointer to the location for storing the data
3183 *
3184 * Reads the flash word at offset into data. Offset is converted
3185 * to bytes before read.
3186 **/
e1000_read_flash_word_ich8lan(struct e1000_hw * hw,u32 offset,u16 * data)3187 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
3188 u16 *data)
3189 {
3190 /* Must convert offset into bytes. */
3191 offset <<= 1;
3192
3193 return e1000_read_flash_data_ich8lan(hw, offset, 2, data);
3194 }
3195
3196 /**
3197 * e1000_read_flash_byte_ich8lan - Read byte from flash
3198 * @hw: pointer to the HW structure
3199 * @offset: The offset of the byte to read.
3200 * @data: Pointer to a byte to store the value read.
3201 *
3202 * Reads a single byte from the NVM using the flash access registers.
3203 **/
e1000_read_flash_byte_ich8lan(struct e1000_hw * hw,u32 offset,u8 * data)3204 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
3205 u8 *data)
3206 {
3207 s32 ret_val;
3208 u16 word = 0;
3209
3210 ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
3211 if (ret_val)
3212 return ret_val;
3213
3214 *data = (u8)word;
3215
3216 return 0;
3217 }
3218
3219 /**
3220 * e1000_read_flash_data_ich8lan - Read byte or word from NVM
3221 * @hw: pointer to the HW structure
3222 * @offset: The offset (in bytes) of the byte or word to read.
3223 * @size: Size of data to read, 1=byte 2=word
3224 * @data: Pointer to the word to store the value read.
3225 *
3226 * Reads a byte or word from the NVM using the flash access registers.
3227 **/
e1000_read_flash_data_ich8lan(struct e1000_hw * hw,u32 offset,u8 size,u16 * data)3228 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
3229 u8 size, u16 *data)
3230 {
3231 union ich8_hws_flash_status hsfsts;
3232 union ich8_hws_flash_ctrl hsflctl;
3233 u32 flash_linear_addr;
3234 u32 flash_data = 0;
3235 s32 ret_val = -E1000_ERR_NVM;
3236 u8 count = 0;
3237
3238 if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
3239 return -E1000_ERR_NVM;
3240
3241 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
3242 hw->nvm.flash_base_addr);
3243
3244 do {
3245 udelay(1);
3246 /* Steps */
3247 ret_val = e1000_flash_cycle_init_ich8lan(hw);
3248 if (ret_val)
3249 break;
3250
3251 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
3252 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
3253 hsflctl.hsf_ctrl.fldbcount = size - 1;
3254 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
3255 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
3256
3257 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
3258
3259 ret_val =
3260 e1000_flash_cycle_ich8lan(hw,
3261 ICH_FLASH_READ_COMMAND_TIMEOUT);
3262
3263 /* Check if FCERR is set to 1, if set to 1, clear it
3264 * and try the whole sequence a few more times, else
3265 * read in (shift in) the Flash Data0, the order is
3266 * least significant byte first msb to lsb
3267 */
3268 if (!ret_val) {
3269 flash_data = er32flash(ICH_FLASH_FDATA0);
3270 if (size == 1)
3271 *data = (u8)(flash_data & 0x000000FF);
3272 else if (size == 2)
3273 *data = (u16)(flash_data & 0x0000FFFF);
3274 break;
3275 } else {
3276 /* If we've gotten here, then things are probably
3277 * completely hosed, but if the error condition is
3278 * detected, it won't hurt to give it another try...
3279 * ICH_FLASH_CYCLE_REPEAT_COUNT times.
3280 */
3281 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3282 if (hsfsts.hsf_status.flcerr) {
3283 /* Repeat for some time before giving up. */
3284 continue;
3285 } else if (!hsfsts.hsf_status.flcdone) {
3286 e_dbg("Timeout error - flash cycle did not complete.\n");
3287 break;
3288 }
3289 }
3290 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
3291
3292 return ret_val;
3293 }
3294
3295 /**
3296 * e1000_write_nvm_ich8lan - Write word(s) to the NVM
3297 * @hw: pointer to the HW structure
3298 * @offset: The offset (in bytes) of the word(s) to write.
3299 * @words: Size of data to write in words
3300 * @data: Pointer to the word(s) to write at offset.
3301 *
3302 * Writes a byte or word to the NVM using the flash access registers.
3303 **/
e1000_write_nvm_ich8lan(struct e1000_hw * hw,u16 offset,u16 words,u16 * data)3304 static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
3305 u16 *data)
3306 {
3307 struct e1000_nvm_info *nvm = &hw->nvm;
3308 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3309 u16 i;
3310
3311 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
3312 (words == 0)) {
3313 e_dbg("nvm parameter(s) out of bounds\n");
3314 return -E1000_ERR_NVM;
3315 }
3316
3317 nvm->ops.acquire(hw);
3318
3319 for (i = 0; i < words; i++) {
3320 dev_spec->shadow_ram[offset + i].modified = true;
3321 dev_spec->shadow_ram[offset + i].value = data[i];
3322 }
3323
3324 nvm->ops.release(hw);
3325
3326 return 0;
3327 }
3328
3329 /**
3330 * e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
3331 * @hw: pointer to the HW structure
3332 *
3333 * The NVM checksum is updated by calling the generic update_nvm_checksum,
3334 * which writes the checksum to the shadow ram. The changes in the shadow
3335 * ram are then committed to the EEPROM by processing each bank at a time
3336 * checking for the modified bit and writing only the pending changes.
3337 * After a successful commit, the shadow ram is cleared and is ready for
3338 * future writes.
3339 **/
e1000_update_nvm_checksum_ich8lan(struct e1000_hw * hw)3340 static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
3341 {
3342 struct e1000_nvm_info *nvm = &hw->nvm;
3343 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3344 u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
3345 s32 ret_val;
3346 u16 data;
3347
3348 ret_val = e1000e_update_nvm_checksum_generic(hw);
3349 if (ret_val)
3350 goto out;
3351
3352 if (nvm->type != e1000_nvm_flash_sw)
3353 goto out;
3354
3355 nvm->ops.acquire(hw);
3356
3357 /* We're writing to the opposite bank so if we're on bank 1,
3358 * write to bank 0 etc. We also need to erase the segment that
3359 * is going to be written
3360 */
3361 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3362 if (ret_val) {
3363 e_dbg("Could not detect valid bank, assuming bank 0\n");
3364 bank = 0;
3365 }
3366
3367 if (bank == 0) {
3368 new_bank_offset = nvm->flash_bank_size;
3369 old_bank_offset = 0;
3370 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
3371 if (ret_val)
3372 goto release;
3373 } else {
3374 old_bank_offset = nvm->flash_bank_size;
3375 new_bank_offset = 0;
3376 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
3377 if (ret_val)
3378 goto release;
3379 }
3380
3381 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
3382 /* Determine whether to write the value stored
3383 * in the other NVM bank or a modified value stored
3384 * in the shadow RAM
3385 */
3386 if (dev_spec->shadow_ram[i].modified) {
3387 data = dev_spec->shadow_ram[i].value;
3388 } else {
3389 ret_val = e1000_read_flash_word_ich8lan(hw, i +
3390 old_bank_offset,
3391 &data);
3392 if (ret_val)
3393 break;
3394 }
3395
3396 /* If the word is 0x13, then make sure the signature bits
3397 * (15:14) are 11b until the commit has completed.
3398 * This will allow us to write 10b which indicates the
3399 * signature is valid. We want to do this after the write
3400 * has completed so that we don't mark the segment valid
3401 * while the write is still in progress
3402 */
3403 if (i == E1000_ICH_NVM_SIG_WORD)
3404 data |= E1000_ICH_NVM_SIG_MASK;
3405
3406 /* Convert offset to bytes. */
3407 act_offset = (i + new_bank_offset) << 1;
3408
3409 usleep_range(100, 200);
3410 /* Write the bytes to the new bank. */
3411 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
3412 act_offset,
3413 (u8)data);
3414 if (ret_val)
3415 break;
3416
3417 usleep_range(100, 200);
3418 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
3419 act_offset + 1,
3420 (u8)(data >> 8));
3421 if (ret_val)
3422 break;
3423 }
3424
3425 /* Don't bother writing the segment valid bits if sector
3426 * programming failed.
3427 */
3428 if (ret_val) {
3429 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */
3430 e_dbg("Flash commit failed.\n");
3431 goto release;
3432 }
3433
3434 /* Finally validate the new segment by setting bit 15:14
3435 * to 10b in word 0x13 , this can be done without an
3436 * erase as well since these bits are 11 to start with
3437 * and we need to change bit 14 to 0b
3438 */
3439 act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
3440 ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data);
3441 if (ret_val)
3442 goto release;
3443
3444 data &= 0xBFFF;
3445 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
3446 act_offset * 2 + 1,
3447 (u8)(data >> 8));
3448 if (ret_val)
3449 goto release;
3450
3451 /* And invalidate the previously valid segment by setting
3452 * its signature word (0x13) high_byte to 0b. This can be
3453 * done without an erase because flash erase sets all bits
3454 * to 1's. We can write 1's to 0's without an erase
3455 */
3456 act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
3457 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
3458 if (ret_val)
3459 goto release;
3460
3461 /* Great! Everything worked, we can now clear the cached entries. */
3462 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
3463 dev_spec->shadow_ram[i].modified = false;
3464 dev_spec->shadow_ram[i].value = 0xFFFF;
3465 }
3466
3467 release:
3468 nvm->ops.release(hw);
3469
3470 /* Reload the EEPROM, or else modifications will not appear
3471 * until after the next adapter reset.
3472 */
3473 if (!ret_val) {
3474 nvm->ops.reload(hw);
3475 usleep_range(10000, 20000);
3476 }
3477
3478 out:
3479 if (ret_val)
3480 e_dbg("NVM update error: %d\n", ret_val);
3481
3482 return ret_val;
3483 }
3484
3485 /**
3486 * e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
3487 * @hw: pointer to the HW structure
3488 *
3489 * Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
3490 * If the bit is 0, that the EEPROM had been modified, but the checksum was not
3491 * calculated, in which case we need to calculate the checksum and set bit 6.
3492 **/
e1000_validate_nvm_checksum_ich8lan(struct e1000_hw * hw)3493 static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
3494 {
3495 s32 ret_val;
3496 u16 data;
3497 u16 word;
3498 u16 valid_csum_mask;
3499
3500 /* Read NVM and check Invalid Image CSUM bit. If this bit is 0,
3501 * the checksum needs to be fixed. This bit is an indication that
3502 * the NVM was prepared by OEM software and did not calculate
3503 * the checksum...a likely scenario.
3504 */
3505 switch (hw->mac.type) {
3506 case e1000_pch_lpt:
3507 word = NVM_COMPAT;
3508 valid_csum_mask = NVM_COMPAT_VALID_CSUM;
3509 break;
3510 default:
3511 word = NVM_FUTURE_INIT_WORD1;
3512 valid_csum_mask = NVM_FUTURE_INIT_WORD1_VALID_CSUM;
3513 break;
3514 }
3515
3516 ret_val = e1000_read_nvm(hw, word, 1, &data);
3517 if (ret_val)
3518 return ret_val;
3519
3520 if (!(data & valid_csum_mask)) {
3521 data |= valid_csum_mask;
3522 ret_val = e1000_write_nvm(hw, word, 1, &data);
3523 if (ret_val)
3524 return ret_val;
3525 ret_val = e1000e_update_nvm_checksum(hw);
3526 if (ret_val)
3527 return ret_val;
3528 }
3529
3530 return e1000e_validate_nvm_checksum_generic(hw);
3531 }
3532
3533 /**
3534 * e1000e_write_protect_nvm_ich8lan - Make the NVM read-only
3535 * @hw: pointer to the HW structure
3536 *
3537 * To prevent malicious write/erase of the NVM, set it to be read-only
3538 * so that the hardware ignores all write/erase cycles of the NVM via
3539 * the flash control registers. The shadow-ram copy of the NVM will
3540 * still be updated, however any updates to this copy will not stick
3541 * across driver reloads.
3542 **/
e1000e_write_protect_nvm_ich8lan(struct e1000_hw * hw)3543 void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw)
3544 {
3545 struct e1000_nvm_info *nvm = &hw->nvm;
3546 union ich8_flash_protected_range pr0;
3547 union ich8_hws_flash_status hsfsts;
3548 u32 gfpreg;
3549
3550 nvm->ops.acquire(hw);
3551
3552 gfpreg = er32flash(ICH_FLASH_GFPREG);
3553
3554 /* Write-protect GbE Sector of NVM */
3555 pr0.regval = er32flash(ICH_FLASH_PR0);
3556 pr0.range.base = gfpreg & FLASH_GFPREG_BASE_MASK;
3557 pr0.range.limit = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK);
3558 pr0.range.wpe = true;
3559 ew32flash(ICH_FLASH_PR0, pr0.regval);
3560
3561 /* Lock down a subset of GbE Flash Control Registers, e.g.
3562 * PR0 to prevent the write-protection from being lifted.
3563 * Once FLOCKDN is set, the registers protected by it cannot
3564 * be written until FLOCKDN is cleared by a hardware reset.
3565 */
3566 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3567 hsfsts.hsf_status.flockdn = true;
3568 ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval);
3569
3570 nvm->ops.release(hw);
3571 }
3572
3573 /**
3574 * e1000_write_flash_data_ich8lan - Writes bytes to the NVM
3575 * @hw: pointer to the HW structure
3576 * @offset: The offset (in bytes) of the byte/word to read.
3577 * @size: Size of data to read, 1=byte 2=word
3578 * @data: The byte(s) to write to the NVM.
3579 *
3580 * Writes one/two bytes to the NVM using the flash access registers.
3581 **/
e1000_write_flash_data_ich8lan(struct e1000_hw * hw,u32 offset,u8 size,u16 data)3582 static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
3583 u8 size, u16 data)
3584 {
3585 union ich8_hws_flash_status hsfsts;
3586 union ich8_hws_flash_ctrl hsflctl;
3587 u32 flash_linear_addr;
3588 u32 flash_data = 0;
3589 s32 ret_val;
3590 u8 count = 0;
3591
3592 if (size < 1 || size > 2 || data > size * 0xff ||
3593 offset > ICH_FLASH_LINEAR_ADDR_MASK)
3594 return -E1000_ERR_NVM;
3595
3596 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
3597 hw->nvm.flash_base_addr);
3598
3599 do {
3600 udelay(1);
3601 /* Steps */
3602 ret_val = e1000_flash_cycle_init_ich8lan(hw);
3603 if (ret_val)
3604 break;
3605
3606 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
3607 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
3608 hsflctl.hsf_ctrl.fldbcount = size - 1;
3609 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
3610 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
3611
3612 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
3613
3614 if (size == 1)
3615 flash_data = (u32)data & 0x00FF;
3616 else
3617 flash_data = (u32)data;
3618
3619 ew32flash(ICH_FLASH_FDATA0, flash_data);
3620
3621 /* check if FCERR is set to 1 , if set to 1, clear it
3622 * and try the whole sequence a few more times else done
3623 */
3624 ret_val =
3625 e1000_flash_cycle_ich8lan(hw,
3626 ICH_FLASH_WRITE_COMMAND_TIMEOUT);
3627 if (!ret_val)
3628 break;
3629
3630 /* If we're here, then things are most likely
3631 * completely hosed, but if the error condition
3632 * is detected, it won't hurt to give it another
3633 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
3634 */
3635 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3636 if (hsfsts.hsf_status.flcerr)
3637 /* Repeat for some time before giving up. */
3638 continue;
3639 if (!hsfsts.hsf_status.flcdone) {
3640 e_dbg("Timeout error - flash cycle did not complete.\n");
3641 break;
3642 }
3643 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
3644
3645 return ret_val;
3646 }
3647
3648 /**
3649 * e1000_write_flash_byte_ich8lan - Write a single byte to NVM
3650 * @hw: pointer to the HW structure
3651 * @offset: The index of the byte to read.
3652 * @data: The byte to write to the NVM.
3653 *
3654 * Writes a single byte to the NVM using the flash access registers.
3655 **/
e1000_write_flash_byte_ich8lan(struct e1000_hw * hw,u32 offset,u8 data)3656 static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
3657 u8 data)
3658 {
3659 u16 word = (u16)data;
3660
3661 return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
3662 }
3663
3664 /**
3665 * e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
3666 * @hw: pointer to the HW structure
3667 * @offset: The offset of the byte to write.
3668 * @byte: The byte to write to the NVM.
3669 *
3670 * Writes a single byte to the NVM using the flash access registers.
3671 * Goes through a retry algorithm before giving up.
3672 **/
e1000_retry_write_flash_byte_ich8lan(struct e1000_hw * hw,u32 offset,u8 byte)3673 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
3674 u32 offset, u8 byte)
3675 {
3676 s32 ret_val;
3677 u16 program_retries;
3678
3679 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
3680 if (!ret_val)
3681 return ret_val;
3682
3683 for (program_retries = 0; program_retries < 100; program_retries++) {
3684 e_dbg("Retrying Byte %2.2X at offset %u\n", byte, offset);
3685 usleep_range(100, 200);
3686 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
3687 if (!ret_val)
3688 break;
3689 }
3690 if (program_retries == 100)
3691 return -E1000_ERR_NVM;
3692
3693 return 0;
3694 }
3695
3696 /**
3697 * e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
3698 * @hw: pointer to the HW structure
3699 * @bank: 0 for first bank, 1 for second bank, etc.
3700 *
3701 * Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
3702 * bank N is 4096 * N + flash_reg_addr.
3703 **/
e1000_erase_flash_bank_ich8lan(struct e1000_hw * hw,u32 bank)3704 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
3705 {
3706 struct e1000_nvm_info *nvm = &hw->nvm;
3707 union ich8_hws_flash_status hsfsts;
3708 union ich8_hws_flash_ctrl hsflctl;
3709 u32 flash_linear_addr;
3710 /* bank size is in 16bit words - adjust to bytes */
3711 u32 flash_bank_size = nvm->flash_bank_size * 2;
3712 s32 ret_val;
3713 s32 count = 0;
3714 s32 j, iteration, sector_size;
3715
3716 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3717
3718 /* Determine HW Sector size: Read BERASE bits of hw flash status
3719 * register
3720 * 00: The Hw sector is 256 bytes, hence we need to erase 16
3721 * consecutive sectors. The start index for the nth Hw sector
3722 * can be calculated as = bank * 4096 + n * 256
3723 * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
3724 * The start index for the nth Hw sector can be calculated
3725 * as = bank * 4096
3726 * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
3727 * (ich9 only, otherwise error condition)
3728 * 11: The Hw sector is 64K bytes, nth sector = bank * 65536
3729 */
3730 switch (hsfsts.hsf_status.berasesz) {
3731 case 0:
3732 /* Hw sector size 256 */
3733 sector_size = ICH_FLASH_SEG_SIZE_256;
3734 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256;
3735 break;
3736 case 1:
3737 sector_size = ICH_FLASH_SEG_SIZE_4K;
3738 iteration = 1;
3739 break;
3740 case 2:
3741 sector_size = ICH_FLASH_SEG_SIZE_8K;
3742 iteration = 1;
3743 break;
3744 case 3:
3745 sector_size = ICH_FLASH_SEG_SIZE_64K;
3746 iteration = 1;
3747 break;
3748 default:
3749 return -E1000_ERR_NVM;
3750 }
3751
3752 /* Start with the base address, then add the sector offset. */
3753 flash_linear_addr = hw->nvm.flash_base_addr;
3754 flash_linear_addr += (bank) ? flash_bank_size : 0;
3755
3756 for (j = 0; j < iteration; j++) {
3757 do {
3758 u32 timeout = ICH_FLASH_ERASE_COMMAND_TIMEOUT;
3759
3760 /* Steps */
3761 ret_val = e1000_flash_cycle_init_ich8lan(hw);
3762 if (ret_val)
3763 return ret_val;
3764
3765 /* Write a value 11 (block Erase) in Flash
3766 * Cycle field in hw flash control
3767 */
3768 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
3769 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
3770 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
3771
3772 /* Write the last 24 bits of an index within the
3773 * block into Flash Linear address field in Flash
3774 * Address.
3775 */
3776 flash_linear_addr += (j * sector_size);
3777 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
3778
3779 ret_val = e1000_flash_cycle_ich8lan(hw, timeout);
3780 if (!ret_val)
3781 break;
3782
3783 /* Check if FCERR is set to 1. If 1,
3784 * clear it and try the whole sequence
3785 * a few more times else Done
3786 */
3787 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3788 if (hsfsts.hsf_status.flcerr)
3789 /* repeat for some time before giving up */
3790 continue;
3791 else if (!hsfsts.hsf_status.flcdone)
3792 return ret_val;
3793 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT);
3794 }
3795
3796 return 0;
3797 }
3798
3799 /**
3800 * e1000_valid_led_default_ich8lan - Set the default LED settings
3801 * @hw: pointer to the HW structure
3802 * @data: Pointer to the LED settings
3803 *
3804 * Reads the LED default settings from the NVM to data. If the NVM LED
3805 * settings is all 0's or F's, set the LED default to a valid LED default
3806 * setting.
3807 **/
e1000_valid_led_default_ich8lan(struct e1000_hw * hw,u16 * data)3808 static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
3809 {
3810 s32 ret_val;
3811
3812 ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
3813 if (ret_val) {
3814 e_dbg("NVM Read Error\n");
3815 return ret_val;
3816 }
3817
3818 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF)
3819 *data = ID_LED_DEFAULT_ICH8LAN;
3820
3821 return 0;
3822 }
3823
3824 /**
3825 * e1000_id_led_init_pchlan - store LED configurations
3826 * @hw: pointer to the HW structure
3827 *
3828 * PCH does not control LEDs via the LEDCTL register, rather it uses
3829 * the PHY LED configuration register.
3830 *
3831 * PCH also does not have an "always on" or "always off" mode which
3832 * complicates the ID feature. Instead of using the "on" mode to indicate
3833 * in ledctl_mode2 the LEDs to use for ID (see e1000e_id_led_init_generic()),
3834 * use "link_up" mode. The LEDs will still ID on request if there is no
3835 * link based on logic in e1000_led_[on|off]_pchlan().
3836 **/
e1000_id_led_init_pchlan(struct e1000_hw * hw)3837 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw)
3838 {
3839 struct e1000_mac_info *mac = &hw->mac;
3840 s32 ret_val;
3841 const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP;
3842 const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT;
3843 u16 data, i, temp, shift;
3844
3845 /* Get default ID LED modes */
3846 ret_val = hw->nvm.ops.valid_led_default(hw, &data);
3847 if (ret_val)
3848 return ret_val;
3849
3850 mac->ledctl_default = er32(LEDCTL);
3851 mac->ledctl_mode1 = mac->ledctl_default;
3852 mac->ledctl_mode2 = mac->ledctl_default;
3853
3854 for (i = 0; i < 4; i++) {
3855 temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK;
3856 shift = (i * 5);
3857 switch (temp) {
3858 case ID_LED_ON1_DEF2:
3859 case ID_LED_ON1_ON2:
3860 case ID_LED_ON1_OFF2:
3861 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
3862 mac->ledctl_mode1 |= (ledctl_on << shift);
3863 break;
3864 case ID_LED_OFF1_DEF2:
3865 case ID_LED_OFF1_ON2:
3866 case ID_LED_OFF1_OFF2:
3867 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
3868 mac->ledctl_mode1 |= (ledctl_off << shift);
3869 break;
3870 default:
3871 /* Do nothing */
3872 break;
3873 }
3874 switch (temp) {
3875 case ID_LED_DEF1_ON2:
3876 case ID_LED_ON1_ON2:
3877 case ID_LED_OFF1_ON2:
3878 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
3879 mac->ledctl_mode2 |= (ledctl_on << shift);
3880 break;
3881 case ID_LED_DEF1_OFF2:
3882 case ID_LED_ON1_OFF2:
3883 case ID_LED_OFF1_OFF2:
3884 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
3885 mac->ledctl_mode2 |= (ledctl_off << shift);
3886 break;
3887 default:
3888 /* Do nothing */
3889 break;
3890 }
3891 }
3892
3893 return 0;
3894 }
3895
3896 /**
3897 * e1000_get_bus_info_ich8lan - Get/Set the bus type and width
3898 * @hw: pointer to the HW structure
3899 *
3900 * ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
3901 * register, so the the bus width is hard coded.
3902 **/
e1000_get_bus_info_ich8lan(struct e1000_hw * hw)3903 static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
3904 {
3905 struct e1000_bus_info *bus = &hw->bus;
3906 s32 ret_val;
3907
3908 ret_val = e1000e_get_bus_info_pcie(hw);
3909
3910 /* ICH devices are "PCI Express"-ish. They have
3911 * a configuration space, but do not contain
3912 * PCI Express Capability registers, so bus width
3913 * must be hardcoded.
3914 */
3915 if (bus->width == e1000_bus_width_unknown)
3916 bus->width = e1000_bus_width_pcie_x1;
3917
3918 return ret_val;
3919 }
3920
3921 /**
3922 * e1000_reset_hw_ich8lan - Reset the hardware
3923 * @hw: pointer to the HW structure
3924 *
3925 * Does a full reset of the hardware which includes a reset of the PHY and
3926 * MAC.
3927 **/
e1000_reset_hw_ich8lan(struct e1000_hw * hw)3928 static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
3929 {
3930 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3931 u16 kum_cfg;
3932 u32 ctrl, reg;
3933 s32 ret_val;
3934
3935 /* Prevent the PCI-E bus from sticking if there is no TLP connection
3936 * on the last TLP read/write transaction when MAC is reset.
3937 */
3938 ret_val = e1000e_disable_pcie_master(hw);
3939 if (ret_val)
3940 e_dbg("PCI-E Master disable polling has failed.\n");
3941
3942 e_dbg("Masking off all interrupts\n");
3943 ew32(IMC, 0xffffffff);
3944
3945 /* Disable the Transmit and Receive units. Then delay to allow
3946 * any pending transactions to complete before we hit the MAC
3947 * with the global reset.
3948 */
3949 ew32(RCTL, 0);
3950 ew32(TCTL, E1000_TCTL_PSP);
3951 e1e_flush();
3952
3953 usleep_range(10000, 20000);
3954
3955 /* Workaround for ICH8 bit corruption issue in FIFO memory */
3956 if (hw->mac.type == e1000_ich8lan) {
3957 /* Set Tx and Rx buffer allocation to 8k apiece. */
3958 ew32(PBA, E1000_PBA_8K);
3959 /* Set Packet Buffer Size to 16k. */
3960 ew32(PBS, E1000_PBS_16K);
3961 }
3962
3963 if (hw->mac.type == e1000_pchlan) {
3964 /* Save the NVM K1 bit setting */
3965 ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, &kum_cfg);
3966 if (ret_val)
3967 return ret_val;
3968
3969 if (kum_cfg & E1000_NVM_K1_ENABLE)
3970 dev_spec->nvm_k1_enabled = true;
3971 else
3972 dev_spec->nvm_k1_enabled = false;
3973 }
3974
3975 ctrl = er32(CTRL);
3976
3977 if (!hw->phy.ops.check_reset_block(hw)) {
3978 /* Full-chip reset requires MAC and PHY reset at the same
3979 * time to make sure the interface between MAC and the
3980 * external PHY is reset.
3981 */
3982 ctrl |= E1000_CTRL_PHY_RST;
3983
3984 /* Gate automatic PHY configuration by hardware on
3985 * non-managed 82579
3986 */
3987 if ((hw->mac.type == e1000_pch2lan) &&
3988 !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
3989 e1000_gate_hw_phy_config_ich8lan(hw, true);
3990 }
3991 ret_val = e1000_acquire_swflag_ich8lan(hw);
3992 e_dbg("Issuing a global reset to ich8lan\n");
3993 ew32(CTRL, (ctrl | E1000_CTRL_RST));
3994 /* cannot issue a flush here because it hangs the hardware */
3995 msleep(20);
3996
3997 /* Set Phy Config Counter to 50msec */
3998 if (hw->mac.type == e1000_pch2lan) {
3999 reg = er32(FEXTNVM3);
4000 reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
4001 reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
4002 ew32(FEXTNVM3, reg);
4003 }
4004
4005 if (!ret_val)
4006 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state);
4007
4008 if (ctrl & E1000_CTRL_PHY_RST) {
4009 ret_val = hw->phy.ops.get_cfg_done(hw);
4010 if (ret_val)
4011 return ret_val;
4012
4013 ret_val = e1000_post_phy_reset_ich8lan(hw);
4014 if (ret_val)
4015 return ret_val;
4016 }
4017
4018 /* For PCH, this write will make sure that any noise
4019 * will be detected as a CRC error and be dropped rather than show up
4020 * as a bad packet to the DMA engine.
4021 */
4022 if (hw->mac.type == e1000_pchlan)
4023 ew32(CRC_OFFSET, 0x65656565);
4024
4025 ew32(IMC, 0xffffffff);
4026 er32(ICR);
4027
4028 reg = er32(KABGTXD);
4029 reg |= E1000_KABGTXD_BGSQLBIAS;
4030 ew32(KABGTXD, reg);
4031
4032 return 0;
4033 }
4034
4035 /**
4036 * e1000_init_hw_ich8lan - Initialize the hardware
4037 * @hw: pointer to the HW structure
4038 *
4039 * Prepares the hardware for transmit and receive by doing the following:
4040 * - initialize hardware bits
4041 * - initialize LED identification
4042 * - setup receive address registers
4043 * - setup flow control
4044 * - setup transmit descriptors
4045 * - clear statistics
4046 **/
e1000_init_hw_ich8lan(struct e1000_hw * hw)4047 static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
4048 {
4049 struct e1000_mac_info *mac = &hw->mac;
4050 u32 ctrl_ext, txdctl, snoop;
4051 s32 ret_val;
4052 u16 i;
4053
4054 e1000_initialize_hw_bits_ich8lan(hw);
4055
4056 /* Initialize identification LED */
4057 ret_val = mac->ops.id_led_init(hw);
4058 /* An error is not fatal and we should not stop init due to this */
4059 if (ret_val)
4060 e_dbg("Error initializing identification LED\n");
4061
4062 /* Setup the receive address. */
4063 e1000e_init_rx_addrs(hw, mac->rar_entry_count);
4064
4065 /* Zero out the Multicast HASH table */
4066 e_dbg("Zeroing the MTA\n");
4067 for (i = 0; i < mac->mta_reg_count; i++)
4068 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
4069
4070 /* The 82578 Rx buffer will stall if wakeup is enabled in host and
4071 * the ME. Disable wakeup by clearing the host wakeup bit.
4072 * Reset the phy after disabling host wakeup to reset the Rx buffer.
4073 */
4074 if (hw->phy.type == e1000_phy_82578) {
4075 e1e_rphy(hw, BM_PORT_GEN_CFG, &i);
4076 i &= ~BM_WUC_HOST_WU_BIT;
4077 e1e_wphy(hw, BM_PORT_GEN_CFG, i);
4078 ret_val = e1000_phy_hw_reset_ich8lan(hw);
4079 if (ret_val)
4080 return ret_val;
4081 }
4082
4083 /* Setup link and flow control */
4084 ret_val = mac->ops.setup_link(hw);
4085
4086 /* Set the transmit descriptor write-back policy for both queues */
4087 txdctl = er32(TXDCTL(0));
4088 txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) |
4089 E1000_TXDCTL_FULL_TX_DESC_WB);
4090 txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) |
4091 E1000_TXDCTL_MAX_TX_DESC_PREFETCH);
4092 ew32(TXDCTL(0), txdctl);
4093 txdctl = er32(TXDCTL(1));
4094 txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) |
4095 E1000_TXDCTL_FULL_TX_DESC_WB);
4096 txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) |
4097 E1000_TXDCTL_MAX_TX_DESC_PREFETCH);
4098 ew32(TXDCTL(1), txdctl);
4099
4100 /* ICH8 has opposite polarity of no_snoop bits.
4101 * By default, we should use snoop behavior.
4102 */
4103 if (mac->type == e1000_ich8lan)
4104 snoop = PCIE_ICH8_SNOOP_ALL;
4105 else
4106 snoop = (u32)~(PCIE_NO_SNOOP_ALL);
4107 e1000e_set_pcie_no_snoop(hw, snoop);
4108
4109 ctrl_ext = er32(CTRL_EXT);
4110 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
4111 ew32(CTRL_EXT, ctrl_ext);
4112
4113 /* Clear all of the statistics registers (clear on read). It is
4114 * important that we do this after we have tried to establish link
4115 * because the symbol error count will increment wildly if there
4116 * is no link.
4117 */
4118 e1000_clear_hw_cntrs_ich8lan(hw);
4119
4120 return ret_val;
4121 }
4122
4123 /**
4124 * e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
4125 * @hw: pointer to the HW structure
4126 *
4127 * Sets/Clears required hardware bits necessary for correctly setting up the
4128 * hardware for transmit and receive.
4129 **/
e1000_initialize_hw_bits_ich8lan(struct e1000_hw * hw)4130 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
4131 {
4132 u32 reg;
4133
4134 /* Extended Device Control */
4135 reg = er32(CTRL_EXT);
4136 reg |= (1 << 22);
4137 /* Enable PHY low-power state when MAC is at D3 w/o WoL */
4138 if (hw->mac.type >= e1000_pchlan)
4139 reg |= E1000_CTRL_EXT_PHYPDEN;
4140 ew32(CTRL_EXT, reg);
4141
4142 /* Transmit Descriptor Control 0 */
4143 reg = er32(TXDCTL(0));
4144 reg |= (1 << 22);
4145 ew32(TXDCTL(0), reg);
4146
4147 /* Transmit Descriptor Control 1 */
4148 reg = er32(TXDCTL(1));
4149 reg |= (1 << 22);
4150 ew32(TXDCTL(1), reg);
4151
4152 /* Transmit Arbitration Control 0 */
4153 reg = er32(TARC(0));
4154 if (hw->mac.type == e1000_ich8lan)
4155 reg |= (1 << 28) | (1 << 29);
4156 reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27);
4157 ew32(TARC(0), reg);
4158
4159 /* Transmit Arbitration Control 1 */
4160 reg = er32(TARC(1));
4161 if (er32(TCTL) & E1000_TCTL_MULR)
4162 reg &= ~(1 << 28);
4163 else
4164 reg |= (1 << 28);
4165 reg |= (1 << 24) | (1 << 26) | (1 << 30);
4166 ew32(TARC(1), reg);
4167
4168 /* Device Status */
4169 if (hw->mac.type == e1000_ich8lan) {
4170 reg = er32(STATUS);
4171 reg &= ~(1 << 31);
4172 ew32(STATUS, reg);
4173 }
4174
4175 /* work-around descriptor data corruption issue during nfs v2 udp
4176 * traffic, just disable the nfs filtering capability
4177 */
4178 reg = er32(RFCTL);
4179 reg |= (E1000_RFCTL_NFSW_DIS | E1000_RFCTL_NFSR_DIS);
4180
4181 /* Disable IPv6 extension header parsing because some malformed
4182 * IPv6 headers can hang the Rx.
4183 */
4184 if (hw->mac.type == e1000_ich8lan)
4185 reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS);
4186 ew32(RFCTL, reg);
4187
4188 /* Enable ECC on Lynxpoint */
4189 if (hw->mac.type == e1000_pch_lpt) {
4190 reg = er32(PBECCSTS);
4191 reg |= E1000_PBECCSTS_ECC_ENABLE;
4192 ew32(PBECCSTS, reg);
4193
4194 reg = er32(CTRL);
4195 reg |= E1000_CTRL_MEHE;
4196 ew32(CTRL, reg);
4197 }
4198 }
4199
4200 /**
4201 * e1000_setup_link_ich8lan - Setup flow control and link settings
4202 * @hw: pointer to the HW structure
4203 *
4204 * Determines which flow control settings to use, then configures flow
4205 * control. Calls the appropriate media-specific link configuration
4206 * function. Assuming the adapter has a valid link partner, a valid link
4207 * should be established. Assumes the hardware has previously been reset
4208 * and the transmitter and receiver are not enabled.
4209 **/
e1000_setup_link_ich8lan(struct e1000_hw * hw)4210 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
4211 {
4212 s32 ret_val;
4213
4214 if (hw->phy.ops.check_reset_block(hw))
4215 return 0;
4216
4217 /* ICH parts do not have a word in the NVM to determine
4218 * the default flow control setting, so we explicitly
4219 * set it to full.
4220 */
4221 if (hw->fc.requested_mode == e1000_fc_default) {
4222 /* Workaround h/w hang when Tx flow control enabled */
4223 if (hw->mac.type == e1000_pchlan)
4224 hw->fc.requested_mode = e1000_fc_rx_pause;
4225 else
4226 hw->fc.requested_mode = e1000_fc_full;
4227 }
4228
4229 /* Save off the requested flow control mode for use later. Depending
4230 * on the link partner's capabilities, we may or may not use this mode.
4231 */
4232 hw->fc.current_mode = hw->fc.requested_mode;
4233
4234 e_dbg("After fix-ups FlowControl is now = %x\n", hw->fc.current_mode);
4235
4236 /* Continue to configure the copper link. */
4237 ret_val = hw->mac.ops.setup_physical_interface(hw);
4238 if (ret_val)
4239 return ret_val;
4240
4241 ew32(FCTTV, hw->fc.pause_time);
4242 if ((hw->phy.type == e1000_phy_82578) ||
4243 (hw->phy.type == e1000_phy_82579) ||
4244 (hw->phy.type == e1000_phy_i217) ||
4245 (hw->phy.type == e1000_phy_82577)) {
4246 ew32(FCRTV_PCH, hw->fc.refresh_time);
4247
4248 ret_val = e1e_wphy(hw, PHY_REG(BM_PORT_CTRL_PAGE, 27),
4249 hw->fc.pause_time);
4250 if (ret_val)
4251 return ret_val;
4252 }
4253
4254 return e1000e_set_fc_watermarks(hw);
4255 }
4256
4257 /**
4258 * e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
4259 * @hw: pointer to the HW structure
4260 *
4261 * Configures the kumeran interface to the PHY to wait the appropriate time
4262 * when polling the PHY, then call the generic setup_copper_link to finish
4263 * configuring the copper link.
4264 **/
e1000_setup_copper_link_ich8lan(struct e1000_hw * hw)4265 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
4266 {
4267 u32 ctrl;
4268 s32 ret_val;
4269 u16 reg_data;
4270
4271 ctrl = er32(CTRL);
4272 ctrl |= E1000_CTRL_SLU;
4273 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
4274 ew32(CTRL, ctrl);
4275
4276 /* Set the mac to wait the maximum time between each iteration
4277 * and increase the max iterations when polling the phy;
4278 * this fixes erroneous timeouts at 10Mbps.
4279 */
4280 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_TIMEOUTS, 0xFFFF);
4281 if (ret_val)
4282 return ret_val;
4283 ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
4284 ®_data);
4285 if (ret_val)
4286 return ret_val;
4287 reg_data |= 0x3F;
4288 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
4289 reg_data);
4290 if (ret_val)
4291 return ret_val;
4292
4293 switch (hw->phy.type) {
4294 case e1000_phy_igp_3:
4295 ret_val = e1000e_copper_link_setup_igp(hw);
4296 if (ret_val)
4297 return ret_val;
4298 break;
4299 case e1000_phy_bm:
4300 case e1000_phy_82578:
4301 ret_val = e1000e_copper_link_setup_m88(hw);
4302 if (ret_val)
4303 return ret_val;
4304 break;
4305 case e1000_phy_82577:
4306 case e1000_phy_82579:
4307 ret_val = e1000_copper_link_setup_82577(hw);
4308 if (ret_val)
4309 return ret_val;
4310 break;
4311 case e1000_phy_ife:
4312 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, ®_data);
4313 if (ret_val)
4314 return ret_val;
4315
4316 reg_data &= ~IFE_PMC_AUTO_MDIX;
4317
4318 switch (hw->phy.mdix) {
4319 case 1:
4320 reg_data &= ~IFE_PMC_FORCE_MDIX;
4321 break;
4322 case 2:
4323 reg_data |= IFE_PMC_FORCE_MDIX;
4324 break;
4325 case 0:
4326 default:
4327 reg_data |= IFE_PMC_AUTO_MDIX;
4328 break;
4329 }
4330 ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, reg_data);
4331 if (ret_val)
4332 return ret_val;
4333 break;
4334 default:
4335 break;
4336 }
4337
4338 return e1000e_setup_copper_link(hw);
4339 }
4340
4341 /**
4342 * e1000_setup_copper_link_pch_lpt - Configure MAC/PHY interface
4343 * @hw: pointer to the HW structure
4344 *
4345 * Calls the PHY specific link setup function and then calls the
4346 * generic setup_copper_link to finish configuring the link for
4347 * Lynxpoint PCH devices
4348 **/
e1000_setup_copper_link_pch_lpt(struct e1000_hw * hw)4349 static s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw)
4350 {
4351 u32 ctrl;
4352 s32 ret_val;
4353
4354 ctrl = er32(CTRL);
4355 ctrl |= E1000_CTRL_SLU;
4356 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
4357 ew32(CTRL, ctrl);
4358
4359 ret_val = e1000_copper_link_setup_82577(hw);
4360 if (ret_val)
4361 return ret_val;
4362
4363 return e1000e_setup_copper_link(hw);
4364 }
4365
4366 /**
4367 * e1000_get_link_up_info_ich8lan - Get current link speed and duplex
4368 * @hw: pointer to the HW structure
4369 * @speed: pointer to store current link speed
4370 * @duplex: pointer to store the current link duplex
4371 *
4372 * Calls the generic get_speed_and_duplex to retrieve the current link
4373 * information and then calls the Kumeran lock loss workaround for links at
4374 * gigabit speeds.
4375 **/
e1000_get_link_up_info_ich8lan(struct e1000_hw * hw,u16 * speed,u16 * duplex)4376 static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
4377 u16 *duplex)
4378 {
4379 s32 ret_val;
4380
4381 ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex);
4382 if (ret_val)
4383 return ret_val;
4384
4385 if ((hw->mac.type == e1000_ich8lan) &&
4386 (hw->phy.type == e1000_phy_igp_3) && (*speed == SPEED_1000)) {
4387 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
4388 }
4389
4390 return ret_val;
4391 }
4392
4393 /**
4394 * e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
4395 * @hw: pointer to the HW structure
4396 *
4397 * Work-around for 82566 Kumeran PCS lock loss:
4398 * On link status change (i.e. PCI reset, speed change) and link is up and
4399 * speed is gigabit-
4400 * 0) if workaround is optionally disabled do nothing
4401 * 1) wait 1ms for Kumeran link to come up
4402 * 2) check Kumeran Diagnostic register PCS lock loss bit
4403 * 3) if not set the link is locked (all is good), otherwise...
4404 * 4) reset the PHY
4405 * 5) repeat up to 10 times
4406 * Note: this is only called for IGP3 copper when speed is 1gb.
4407 **/
e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw * hw)4408 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
4409 {
4410 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4411 u32 phy_ctrl;
4412 s32 ret_val;
4413 u16 i, data;
4414 bool link;
4415
4416 if (!dev_spec->kmrn_lock_loss_workaround_enabled)
4417 return 0;
4418
4419 /* Make sure link is up before proceeding. If not just return.
4420 * Attempting this while link is negotiating fouled up link
4421 * stability
4422 */
4423 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
4424 if (!link)
4425 return 0;
4426
4427 for (i = 0; i < 10; i++) {
4428 /* read once to clear */
4429 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
4430 if (ret_val)
4431 return ret_val;
4432 /* and again to get new status */
4433 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
4434 if (ret_val)
4435 return ret_val;
4436
4437 /* check for PCS lock */
4438 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
4439 return 0;
4440
4441 /* Issue PHY reset */
4442 e1000_phy_hw_reset(hw);
4443 mdelay(5);
4444 }
4445 /* Disable GigE link negotiation */
4446 phy_ctrl = er32(PHY_CTRL);
4447 phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE |
4448 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
4449 ew32(PHY_CTRL, phy_ctrl);
4450
4451 /* Call gig speed drop workaround on Gig disable before accessing
4452 * any PHY registers
4453 */
4454 e1000e_gig_downshift_workaround_ich8lan(hw);
4455
4456 /* unable to acquire PCS lock */
4457 return -E1000_ERR_PHY;
4458 }
4459
4460 /**
4461 * e1000e_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
4462 * @hw: pointer to the HW structure
4463 * @state: boolean value used to set the current Kumeran workaround state
4464 *
4465 * If ICH8, set the current Kumeran workaround state (enabled - true
4466 * /disabled - false).
4467 **/
e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw * hw,bool state)4468 void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
4469 bool state)
4470 {
4471 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4472
4473 if (hw->mac.type != e1000_ich8lan) {
4474 e_dbg("Workaround applies to ICH8 only.\n");
4475 return;
4476 }
4477
4478 dev_spec->kmrn_lock_loss_workaround_enabled = state;
4479 }
4480
4481 /**
4482 * e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
4483 * @hw: pointer to the HW structure
4484 *
4485 * Workaround for 82566 power-down on D3 entry:
4486 * 1) disable gigabit link
4487 * 2) write VR power-down enable
4488 * 3) read it back
4489 * Continue if successful, else issue LCD reset and repeat
4490 **/
e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw * hw)4491 void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
4492 {
4493 u32 reg;
4494 u16 data;
4495 u8 retry = 0;
4496
4497 if (hw->phy.type != e1000_phy_igp_3)
4498 return;
4499
4500 /* Try the workaround twice (if needed) */
4501 do {
4502 /* Disable link */
4503 reg = er32(PHY_CTRL);
4504 reg |= (E1000_PHY_CTRL_GBE_DISABLE |
4505 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
4506 ew32(PHY_CTRL, reg);
4507
4508 /* Call gig speed drop workaround on Gig disable before
4509 * accessing any PHY registers
4510 */
4511 if (hw->mac.type == e1000_ich8lan)
4512 e1000e_gig_downshift_workaround_ich8lan(hw);
4513
4514 /* Write VR power-down enable */
4515 e1e_rphy(hw, IGP3_VR_CTRL, &data);
4516 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
4517 e1e_wphy(hw, IGP3_VR_CTRL, data | IGP3_VR_CTRL_MODE_SHUTDOWN);
4518
4519 /* Read it back and test */
4520 e1e_rphy(hw, IGP3_VR_CTRL, &data);
4521 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
4522 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry)
4523 break;
4524
4525 /* Issue PHY reset and repeat at most one more time */
4526 reg = er32(CTRL);
4527 ew32(CTRL, reg | E1000_CTRL_PHY_RST);
4528 retry++;
4529 } while (retry);
4530 }
4531
4532 /**
4533 * e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working
4534 * @hw: pointer to the HW structure
4535 *
4536 * Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
4537 * LPLU, Gig disable, MDIC PHY reset):
4538 * 1) Set Kumeran Near-end loopback
4539 * 2) Clear Kumeran Near-end loopback
4540 * Should only be called for ICH8[m] devices with any 1G Phy.
4541 **/
e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw * hw)4542 void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
4543 {
4544 s32 ret_val;
4545 u16 reg_data;
4546
4547 if ((hw->mac.type != e1000_ich8lan) || (hw->phy.type == e1000_phy_ife))
4548 return;
4549
4550 ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
4551 ®_data);
4552 if (ret_val)
4553 return;
4554 reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK;
4555 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
4556 reg_data);
4557 if (ret_val)
4558 return;
4559 reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK;
4560 e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, reg_data);
4561 }
4562
4563 /**
4564 * e1000_suspend_workarounds_ich8lan - workarounds needed during S0->Sx
4565 * @hw: pointer to the HW structure
4566 *
4567 * During S0 to Sx transition, it is possible the link remains at gig
4568 * instead of negotiating to a lower speed. Before going to Sx, set
4569 * 'Gig Disable' to force link speed negotiation to a lower speed based on
4570 * the LPLU setting in the NVM or custom setting. For PCH and newer parts,
4571 * the OEM bits PHY register (LED, GbE disable and LPLU configurations) also
4572 * needs to be written.
4573 * Parts that support (and are linked to a partner which support) EEE in
4574 * 100Mbps should disable LPLU since 100Mbps w/ EEE requires less power
4575 * than 10Mbps w/o EEE.
4576 **/
e1000_suspend_workarounds_ich8lan(struct e1000_hw * hw)4577 void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw)
4578 {
4579 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4580 u32 phy_ctrl;
4581 s32 ret_val;
4582
4583 phy_ctrl = er32(PHY_CTRL);
4584 phy_ctrl |= E1000_PHY_CTRL_GBE_DISABLE;
4585
4586 if (hw->phy.type == e1000_phy_i217) {
4587 u16 phy_reg, device_id = hw->adapter->pdev->device;
4588
4589 if ((device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||
4590 (device_id == E1000_DEV_ID_PCH_LPTLP_I218_V) ||
4591 (device_id == E1000_DEV_ID_PCH_I218_LM3) ||
4592 (device_id == E1000_DEV_ID_PCH_I218_V3)) {
4593 u32 fextnvm6 = er32(FEXTNVM6);
4594
4595 ew32(FEXTNVM6, fextnvm6 & ~E1000_FEXTNVM6_REQ_PLL_CLK);
4596 }
4597
4598 ret_val = hw->phy.ops.acquire(hw);
4599 if (ret_val)
4600 goto out;
4601
4602 if (!dev_spec->eee_disable) {
4603 u16 eee_advert;
4604
4605 ret_val =
4606 e1000_read_emi_reg_locked(hw,
4607 I217_EEE_ADVERTISEMENT,
4608 &eee_advert);
4609 if (ret_val)
4610 goto release;
4611
4612 /* Disable LPLU if both link partners support 100BaseT
4613 * EEE and 100Full is advertised on both ends of the
4614 * link, and enable Auto Enable LPI since there will
4615 * be no driver to enable LPI while in Sx.
4616 */
4617 if ((eee_advert & I82579_EEE_100_SUPPORTED) &&
4618 (dev_spec->eee_lp_ability &
4619 I82579_EEE_100_SUPPORTED) &&
4620 (hw->phy.autoneg_advertised & ADVERTISE_100_FULL)) {
4621 phy_ctrl &= ~(E1000_PHY_CTRL_D0A_LPLU |
4622 E1000_PHY_CTRL_NOND0A_LPLU);
4623
4624 /* Set Auto Enable LPI after link up */
4625 e1e_rphy_locked(hw,
4626 I217_LPI_GPIO_CTRL, &phy_reg);
4627 phy_reg |= I217_LPI_GPIO_CTRL_AUTO_EN_LPI;
4628 e1e_wphy_locked(hw,
4629 I217_LPI_GPIO_CTRL, phy_reg);
4630 }
4631 }
4632
4633 /* For i217 Intel Rapid Start Technology support,
4634 * when the system is going into Sx and no manageability engine
4635 * is present, the driver must configure proxy to reset only on
4636 * power good. LPI (Low Power Idle) state must also reset only
4637 * on power good, as well as the MTA (Multicast table array).
4638 * The SMBus release must also be disabled on LCD reset.
4639 */
4640 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
4641 /* Enable proxy to reset only on power good. */
4642 e1e_rphy_locked(hw, I217_PROXY_CTRL, &phy_reg);
4643 phy_reg |= I217_PROXY_CTRL_AUTO_DISABLE;
4644 e1e_wphy_locked(hw, I217_PROXY_CTRL, phy_reg);
4645
4646 /* Set bit enable LPI (EEE) to reset only on
4647 * power good.
4648 */
4649 e1e_rphy_locked(hw, I217_SxCTRL, &phy_reg);
4650 phy_reg |= I217_SxCTRL_ENABLE_LPI_RESET;
4651 e1e_wphy_locked(hw, I217_SxCTRL, phy_reg);
4652
4653 /* Disable the SMB release on LCD reset. */
4654 e1e_rphy_locked(hw, I217_MEMPWR, &phy_reg);
4655 phy_reg &= ~I217_MEMPWR_DISABLE_SMB_RELEASE;
4656 e1e_wphy_locked(hw, I217_MEMPWR, phy_reg);
4657 }
4658
4659 /* Enable MTA to reset for Intel Rapid Start Technology
4660 * Support
4661 */
4662 e1e_rphy_locked(hw, I217_CGFREG, &phy_reg);
4663 phy_reg |= I217_CGFREG_ENABLE_MTA_RESET;
4664 e1e_wphy_locked(hw, I217_CGFREG, phy_reg);
4665
4666 release:
4667 hw->phy.ops.release(hw);
4668 }
4669 out:
4670 ew32(PHY_CTRL, phy_ctrl);
4671
4672 if (hw->mac.type == e1000_ich8lan)
4673 e1000e_gig_downshift_workaround_ich8lan(hw);
4674
4675 if (hw->mac.type >= e1000_pchlan) {
4676 e1000_oem_bits_config_ich8lan(hw, false);
4677
4678 /* Reset PHY to activate OEM bits on 82577/8 */
4679 if (hw->mac.type == e1000_pchlan)
4680 e1000e_phy_hw_reset_generic(hw);
4681
4682 ret_val = hw->phy.ops.acquire(hw);
4683 if (ret_val)
4684 return;
4685 e1000_write_smbus_addr(hw);
4686 hw->phy.ops.release(hw);
4687 }
4688 }
4689
4690 /**
4691 * e1000_resume_workarounds_pchlan - workarounds needed during Sx->S0
4692 * @hw: pointer to the HW structure
4693 *
4694 * During Sx to S0 transitions on non-managed devices or managed devices
4695 * on which PHY resets are not blocked, if the PHY registers cannot be
4696 * accessed properly by the s/w toggle the LANPHYPC value to power cycle
4697 * the PHY.
4698 * On i217, setup Intel Rapid Start Technology.
4699 **/
e1000_resume_workarounds_pchlan(struct e1000_hw * hw)4700 void e1000_resume_workarounds_pchlan(struct e1000_hw *hw)
4701 {
4702 s32 ret_val;
4703
4704 if (hw->mac.type < e1000_pch2lan)
4705 return;
4706
4707 ret_val = e1000_init_phy_workarounds_pchlan(hw);
4708 if (ret_val) {
4709 e_dbg("Failed to init PHY flow ret_val=%d\n", ret_val);
4710 return;
4711 }
4712
4713 /* For i217 Intel Rapid Start Technology support when the system
4714 * is transitioning from Sx and no manageability engine is present
4715 * configure SMBus to restore on reset, disable proxy, and enable
4716 * the reset on MTA (Multicast table array).
4717 */
4718 if (hw->phy.type == e1000_phy_i217) {
4719 u16 phy_reg;
4720
4721 ret_val = hw->phy.ops.acquire(hw);
4722 if (ret_val) {
4723 e_dbg("Failed to setup iRST\n");
4724 return;
4725 }
4726
4727 /* Clear Auto Enable LPI after link up */
4728 e1e_rphy_locked(hw, I217_LPI_GPIO_CTRL, &phy_reg);
4729 phy_reg &= ~I217_LPI_GPIO_CTRL_AUTO_EN_LPI;
4730 e1e_wphy_locked(hw, I217_LPI_GPIO_CTRL, phy_reg);
4731
4732 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
4733 /* Restore clear on SMB if no manageability engine
4734 * is present
4735 */
4736 ret_val = e1e_rphy_locked(hw, I217_MEMPWR, &phy_reg);
4737 if (ret_val)
4738 goto release;
4739 phy_reg |= I217_MEMPWR_DISABLE_SMB_RELEASE;
4740 e1e_wphy_locked(hw, I217_MEMPWR, phy_reg);
4741
4742 /* Disable Proxy */
4743 e1e_wphy_locked(hw, I217_PROXY_CTRL, 0);
4744 }
4745 /* Enable reset on MTA */
4746 ret_val = e1e_rphy_locked(hw, I217_CGFREG, &phy_reg);
4747 if (ret_val)
4748 goto release;
4749 phy_reg &= ~I217_CGFREG_ENABLE_MTA_RESET;
4750 e1e_wphy_locked(hw, I217_CGFREG, phy_reg);
4751 release:
4752 if (ret_val)
4753 e_dbg("Error %d in resume workarounds\n", ret_val);
4754 hw->phy.ops.release(hw);
4755 }
4756 }
4757
4758 /**
4759 * e1000_cleanup_led_ich8lan - Restore the default LED operation
4760 * @hw: pointer to the HW structure
4761 *
4762 * Return the LED back to the default configuration.
4763 **/
e1000_cleanup_led_ich8lan(struct e1000_hw * hw)4764 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
4765 {
4766 if (hw->phy.type == e1000_phy_ife)
4767 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0);
4768
4769 ew32(LEDCTL, hw->mac.ledctl_default);
4770 return 0;
4771 }
4772
4773 /**
4774 * e1000_led_on_ich8lan - Turn LEDs on
4775 * @hw: pointer to the HW structure
4776 *
4777 * Turn on the LEDs.
4778 **/
e1000_led_on_ich8lan(struct e1000_hw * hw)4779 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
4780 {
4781 if (hw->phy.type == e1000_phy_ife)
4782 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
4783 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
4784
4785 ew32(LEDCTL, hw->mac.ledctl_mode2);
4786 return 0;
4787 }
4788
4789 /**
4790 * e1000_led_off_ich8lan - Turn LEDs off
4791 * @hw: pointer to the HW structure
4792 *
4793 * Turn off the LEDs.
4794 **/
e1000_led_off_ich8lan(struct e1000_hw * hw)4795 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
4796 {
4797 if (hw->phy.type == e1000_phy_ife)
4798 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
4799 (IFE_PSCL_PROBE_MODE |
4800 IFE_PSCL_PROBE_LEDS_OFF));
4801
4802 ew32(LEDCTL, hw->mac.ledctl_mode1);
4803 return 0;
4804 }
4805
4806 /**
4807 * e1000_setup_led_pchlan - Configures SW controllable LED
4808 * @hw: pointer to the HW structure
4809 *
4810 * This prepares the SW controllable LED for use.
4811 **/
e1000_setup_led_pchlan(struct e1000_hw * hw)4812 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw)
4813 {
4814 return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_mode1);
4815 }
4816
4817 /**
4818 * e1000_cleanup_led_pchlan - Restore the default LED operation
4819 * @hw: pointer to the HW structure
4820 *
4821 * Return the LED back to the default configuration.
4822 **/
e1000_cleanup_led_pchlan(struct e1000_hw * hw)4823 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw)
4824 {
4825 return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_default);
4826 }
4827
4828 /**
4829 * e1000_led_on_pchlan - Turn LEDs on
4830 * @hw: pointer to the HW structure
4831 *
4832 * Turn on the LEDs.
4833 **/
e1000_led_on_pchlan(struct e1000_hw * hw)4834 static s32 e1000_led_on_pchlan(struct e1000_hw *hw)
4835 {
4836 u16 data = (u16)hw->mac.ledctl_mode2;
4837 u32 i, led;
4838
4839 /* If no link, then turn LED on by setting the invert bit
4840 * for each LED that's mode is "link_up" in ledctl_mode2.
4841 */
4842 if (!(er32(STATUS) & E1000_STATUS_LU)) {
4843 for (i = 0; i < 3; i++) {
4844 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
4845 if ((led & E1000_PHY_LED0_MODE_MASK) !=
4846 E1000_LEDCTL_MODE_LINK_UP)
4847 continue;
4848 if (led & E1000_PHY_LED0_IVRT)
4849 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
4850 else
4851 data |= (E1000_PHY_LED0_IVRT << (i * 5));
4852 }
4853 }
4854
4855 return e1e_wphy(hw, HV_LED_CONFIG, data);
4856 }
4857
4858 /**
4859 * e1000_led_off_pchlan - Turn LEDs off
4860 * @hw: pointer to the HW structure
4861 *
4862 * Turn off the LEDs.
4863 **/
e1000_led_off_pchlan(struct e1000_hw * hw)4864 static s32 e1000_led_off_pchlan(struct e1000_hw *hw)
4865 {
4866 u16 data = (u16)hw->mac.ledctl_mode1;
4867 u32 i, led;
4868
4869 /* If no link, then turn LED off by clearing the invert bit
4870 * for each LED that's mode is "link_up" in ledctl_mode1.
4871 */
4872 if (!(er32(STATUS) & E1000_STATUS_LU)) {
4873 for (i = 0; i < 3; i++) {
4874 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
4875 if ((led & E1000_PHY_LED0_MODE_MASK) !=
4876 E1000_LEDCTL_MODE_LINK_UP)
4877 continue;
4878 if (led & E1000_PHY_LED0_IVRT)
4879 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
4880 else
4881 data |= (E1000_PHY_LED0_IVRT << (i * 5));
4882 }
4883 }
4884
4885 return e1e_wphy(hw, HV_LED_CONFIG, data);
4886 }
4887
4888 /**
4889 * e1000_get_cfg_done_ich8lan - Read config done bit after Full or PHY reset
4890 * @hw: pointer to the HW structure
4891 *
4892 * Read appropriate register for the config done bit for completion status
4893 * and configure the PHY through s/w for EEPROM-less parts.
4894 *
4895 * NOTE: some silicon which is EEPROM-less will fail trying to read the
4896 * config done bit, so only an error is logged and continues. If we were
4897 * to return with error, EEPROM-less silicon would not be able to be reset
4898 * or change link.
4899 **/
e1000_get_cfg_done_ich8lan(struct e1000_hw * hw)4900 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
4901 {
4902 s32 ret_val = 0;
4903 u32 bank = 0;
4904 u32 status;
4905
4906 e1000e_get_cfg_done_generic(hw);
4907
4908 /* Wait for indication from h/w that it has completed basic config */
4909 if (hw->mac.type >= e1000_ich10lan) {
4910 e1000_lan_init_done_ich8lan(hw);
4911 } else {
4912 ret_val = e1000e_get_auto_rd_done(hw);
4913 if (ret_val) {
4914 /* When auto config read does not complete, do not
4915 * return with an error. This can happen in situations
4916 * where there is no eeprom and prevents getting link.
4917 */
4918 e_dbg("Auto Read Done did not complete\n");
4919 ret_val = 0;
4920 }
4921 }
4922
4923 /* Clear PHY Reset Asserted bit */
4924 status = er32(STATUS);
4925 if (status & E1000_STATUS_PHYRA)
4926 ew32(STATUS, status & ~E1000_STATUS_PHYRA);
4927 else
4928 e_dbg("PHY Reset Asserted not set - needs delay\n");
4929
4930 /* If EEPROM is not marked present, init the IGP 3 PHY manually */
4931 if (hw->mac.type <= e1000_ich9lan) {
4932 if (!(er32(EECD) & E1000_EECD_PRES) &&
4933 (hw->phy.type == e1000_phy_igp_3)) {
4934 e1000e_phy_init_script_igp3(hw);
4935 }
4936 } else {
4937 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {
4938 /* Maybe we should do a basic PHY config */
4939 e_dbg("EEPROM not present\n");
4940 ret_val = -E1000_ERR_CONFIG;
4941 }
4942 }
4943
4944 return ret_val;
4945 }
4946
4947 /**
4948 * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down
4949 * @hw: pointer to the HW structure
4950 *
4951 * In the case of a PHY power down to save power, or to turn off link during a
4952 * driver unload, or wake on lan is not enabled, remove the link.
4953 **/
e1000_power_down_phy_copper_ich8lan(struct e1000_hw * hw)4954 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw)
4955 {
4956 /* If the management interface is not enabled, then power down */
4957 if (!(hw->mac.ops.check_mng_mode(hw) ||
4958 hw->phy.ops.check_reset_block(hw)))
4959 e1000_power_down_phy_copper(hw);
4960 }
4961
4962 /**
4963 * e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
4964 * @hw: pointer to the HW structure
4965 *
4966 * Clears hardware counters specific to the silicon family and calls
4967 * clear_hw_cntrs_generic to clear all general purpose counters.
4968 **/
e1000_clear_hw_cntrs_ich8lan(struct e1000_hw * hw)4969 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
4970 {
4971 u16 phy_data;
4972 s32 ret_val;
4973
4974 e1000e_clear_hw_cntrs_base(hw);
4975
4976 er32(ALGNERRC);
4977 er32(RXERRC);
4978 er32(TNCRS);
4979 er32(CEXTERR);
4980 er32(TSCTC);
4981 er32(TSCTFC);
4982
4983 er32(MGTPRC);
4984 er32(MGTPDC);
4985 er32(MGTPTC);
4986
4987 er32(IAC);
4988 er32(ICRXOC);
4989
4990 /* Clear PHY statistics registers */
4991 if ((hw->phy.type == e1000_phy_82578) ||
4992 (hw->phy.type == e1000_phy_82579) ||
4993 (hw->phy.type == e1000_phy_i217) ||
4994 (hw->phy.type == e1000_phy_82577)) {
4995 ret_val = hw->phy.ops.acquire(hw);
4996 if (ret_val)
4997 return;
4998 ret_val = hw->phy.ops.set_page(hw,
4999 HV_STATS_PAGE << IGP_PAGE_SHIFT);
5000 if (ret_val)
5001 goto release;
5002 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data);
5003 hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data);
5004 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data);
5005 hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data);
5006 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data);
5007 hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data);
5008 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data);
5009 hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data);
5010 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data);
5011 hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data);
5012 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data);
5013 hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data);
5014 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data);
5015 hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data);
5016 release:
5017 hw->phy.ops.release(hw);
5018 }
5019 }
5020
5021 static const struct e1000_mac_operations ich8_mac_ops = {
5022 /* check_mng_mode dependent on mac type */
5023 .check_for_link = e1000_check_for_copper_link_ich8lan,
5024 /* cleanup_led dependent on mac type */
5025 .clear_hw_cntrs = e1000_clear_hw_cntrs_ich8lan,
5026 .get_bus_info = e1000_get_bus_info_ich8lan,
5027 .set_lan_id = e1000_set_lan_id_single_port,
5028 .get_link_up_info = e1000_get_link_up_info_ich8lan,
5029 /* led_on dependent on mac type */
5030 /* led_off dependent on mac type */
5031 .update_mc_addr_list = e1000e_update_mc_addr_list_generic,
5032 .reset_hw = e1000_reset_hw_ich8lan,
5033 .init_hw = e1000_init_hw_ich8lan,
5034 .setup_link = e1000_setup_link_ich8lan,
5035 .setup_physical_interface = e1000_setup_copper_link_ich8lan,
5036 /* id_led_init dependent on mac type */
5037 .config_collision_dist = e1000e_config_collision_dist_generic,
5038 .rar_set = e1000e_rar_set_generic,
5039 .rar_get_count = e1000e_rar_get_count_generic,
5040 };
5041
5042 static const struct e1000_phy_operations ich8_phy_ops = {
5043 .acquire = e1000_acquire_swflag_ich8lan,
5044 .check_reset_block = e1000_check_reset_block_ich8lan,
5045 .commit = NULL,
5046 .get_cfg_done = e1000_get_cfg_done_ich8lan,
5047 .get_cable_length = e1000e_get_cable_length_igp_2,
5048 .read_reg = e1000e_read_phy_reg_igp,
5049 .release = e1000_release_swflag_ich8lan,
5050 .reset = e1000_phy_hw_reset_ich8lan,
5051 .set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan,
5052 .set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan,
5053 .write_reg = e1000e_write_phy_reg_igp,
5054 };
5055
5056 static const struct e1000_nvm_operations ich8_nvm_ops = {
5057 .acquire = e1000_acquire_nvm_ich8lan,
5058 .read = e1000_read_nvm_ich8lan,
5059 .release = e1000_release_nvm_ich8lan,
5060 .reload = e1000e_reload_nvm_generic,
5061 .update = e1000_update_nvm_checksum_ich8lan,
5062 .valid_led_default = e1000_valid_led_default_ich8lan,
5063 .validate = e1000_validate_nvm_checksum_ich8lan,
5064 .write = e1000_write_nvm_ich8lan,
5065 };
5066
5067 const struct e1000_info e1000_ich8_info = {
5068 .mac = e1000_ich8lan,
5069 .flags = FLAG_HAS_WOL
5070 | FLAG_IS_ICH
5071 | FLAG_HAS_CTRLEXT_ON_LOAD
5072 | FLAG_HAS_AMT
5073 | FLAG_HAS_FLASH
5074 | FLAG_APME_IN_WUC,
5075 .pba = 8,
5076 .max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN,
5077 .get_variants = e1000_get_variants_ich8lan,
5078 .mac_ops = &ich8_mac_ops,
5079 .phy_ops = &ich8_phy_ops,
5080 .nvm_ops = &ich8_nvm_ops,
5081 };
5082
5083 const struct e1000_info e1000_ich9_info = {
5084 .mac = e1000_ich9lan,
5085 .flags = FLAG_HAS_JUMBO_FRAMES
5086 | FLAG_IS_ICH
5087 | FLAG_HAS_WOL
5088 | FLAG_HAS_CTRLEXT_ON_LOAD
5089 | FLAG_HAS_AMT
5090 | FLAG_HAS_FLASH
5091 | FLAG_APME_IN_WUC,
5092 .pba = 18,
5093 .max_hw_frame_size = DEFAULT_JUMBO,
5094 .get_variants = e1000_get_variants_ich8lan,
5095 .mac_ops = &ich8_mac_ops,
5096 .phy_ops = &ich8_phy_ops,
5097 .nvm_ops = &ich8_nvm_ops,
5098 };
5099
5100 const struct e1000_info e1000_ich10_info = {
5101 .mac = e1000_ich10lan,
5102 .flags = FLAG_HAS_JUMBO_FRAMES
5103 | FLAG_IS_ICH
5104 | FLAG_HAS_WOL
5105 | FLAG_HAS_CTRLEXT_ON_LOAD
5106 | FLAG_HAS_AMT
5107 | FLAG_HAS_FLASH
5108 | FLAG_APME_IN_WUC,
5109 .pba = 18,
5110 .max_hw_frame_size = DEFAULT_JUMBO,
5111 .get_variants = e1000_get_variants_ich8lan,
5112 .mac_ops = &ich8_mac_ops,
5113 .phy_ops = &ich8_phy_ops,
5114 .nvm_ops = &ich8_nvm_ops,
5115 };
5116
5117 const struct e1000_info e1000_pch_info = {
5118 .mac = e1000_pchlan,
5119 .flags = FLAG_IS_ICH
5120 | FLAG_HAS_WOL
5121 | FLAG_HAS_CTRLEXT_ON_LOAD
5122 | FLAG_HAS_AMT
5123 | FLAG_HAS_FLASH
5124 | FLAG_HAS_JUMBO_FRAMES
5125 | FLAG_DISABLE_FC_PAUSE_TIME /* errata */
5126 | FLAG_APME_IN_WUC,
5127 .flags2 = FLAG2_HAS_PHY_STATS,
5128 .pba = 26,
5129 .max_hw_frame_size = 4096,
5130 .get_variants = e1000_get_variants_ich8lan,
5131 .mac_ops = &ich8_mac_ops,
5132 .phy_ops = &ich8_phy_ops,
5133 .nvm_ops = &ich8_nvm_ops,
5134 };
5135
5136 const struct e1000_info e1000_pch2_info = {
5137 .mac = e1000_pch2lan,
5138 .flags = FLAG_IS_ICH
5139 | FLAG_HAS_WOL
5140 | FLAG_HAS_HW_TIMESTAMP
5141 | FLAG_HAS_CTRLEXT_ON_LOAD
5142 | FLAG_HAS_AMT
5143 | FLAG_HAS_FLASH
5144 | FLAG_HAS_JUMBO_FRAMES
5145 | FLAG_APME_IN_WUC,
5146 .flags2 = FLAG2_HAS_PHY_STATS
5147 | FLAG2_HAS_EEE,
5148 .pba = 26,
5149 .max_hw_frame_size = 9018,
5150 .get_variants = e1000_get_variants_ich8lan,
5151 .mac_ops = &ich8_mac_ops,
5152 .phy_ops = &ich8_phy_ops,
5153 .nvm_ops = &ich8_nvm_ops,
5154 };
5155
5156 const struct e1000_info e1000_pch_lpt_info = {
5157 .mac = e1000_pch_lpt,
5158 .flags = FLAG_IS_ICH
5159 | FLAG_HAS_WOL
5160 | FLAG_HAS_HW_TIMESTAMP
5161 | FLAG_HAS_CTRLEXT_ON_LOAD
5162 | FLAG_HAS_AMT
5163 | FLAG_HAS_FLASH
5164 | FLAG_HAS_JUMBO_FRAMES
5165 | FLAG_APME_IN_WUC,
5166 .flags2 = FLAG2_HAS_PHY_STATS
5167 | FLAG2_HAS_EEE,
5168 .pba = 26,
5169 .max_hw_frame_size = 9018,
5170 .get_variants = e1000_get_variants_ich8lan,
5171 .mac_ops = &ich8_mac_ops,
5172 .phy_ops = &ich8_phy_ops,
5173 .nvm_ops = &ich8_nvm_ops,
5174 };
5175