1 /* Intel(R) Gigabit Ethernet Linux driver
2 * Copyright(c) 2007-2014 Intel Corporation.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License along with
14 * this program; if not, see <http://www.gnu.org/licenses/>.
15 *
16 * The full GNU General Public License is included in this distribution in
17 * the file called "COPYING".
18 *
19 * Contact Information:
20 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
21 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
22 */
23
24 #include <linux/if_ether.h>
25 #include <linux/delay.h>
26
27 #include "e1000_mac.h"
28 #include "e1000_phy.h"
29
30 static s32 igb_phy_setup_autoneg(struct e1000_hw *hw);
31 static void igb_phy_force_speed_duplex_setup(struct e1000_hw *hw,
32 u16 *phy_ctrl);
33 static s32 igb_wait_autoneg(struct e1000_hw *hw);
34 static s32 igb_set_master_slave_mode(struct e1000_hw *hw);
35
36 /* Cable length tables */
37 static const u16 e1000_m88_cable_length_table[] = {
38 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED };
39 #define M88E1000_CABLE_LENGTH_TABLE_SIZE \
40 (sizeof(e1000_m88_cable_length_table) / \
41 sizeof(e1000_m88_cable_length_table[0]))
42
43 static const u16 e1000_igp_2_cable_length_table[] = {
44 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21,
45 0, 0, 0, 3, 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41,
46 6, 10, 14, 18, 22, 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61,
47 21, 26, 31, 35, 40, 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82,
48 40, 45, 51, 56, 61, 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104,
49 60, 66, 72, 77, 82, 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121,
50 83, 89, 95, 100, 105, 109, 113, 116, 119, 122, 124,
51 104, 109, 114, 118, 121, 124};
52 #define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \
53 (sizeof(e1000_igp_2_cable_length_table) / \
54 sizeof(e1000_igp_2_cable_length_table[0]))
55
56 /**
57 * igb_check_reset_block - Check if PHY reset is blocked
58 * @hw: pointer to the HW structure
59 *
60 * Read the PHY management control register and check whether a PHY reset
61 * is blocked. If a reset is not blocked return 0, otherwise
62 * return E1000_BLK_PHY_RESET (12).
63 **/
igb_check_reset_block(struct e1000_hw * hw)64 s32 igb_check_reset_block(struct e1000_hw *hw)
65 {
66 u32 manc;
67
68 manc = rd32(E1000_MANC);
69
70 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ? E1000_BLK_PHY_RESET : 0;
71 }
72
73 /**
74 * igb_get_phy_id - Retrieve the PHY ID and revision
75 * @hw: pointer to the HW structure
76 *
77 * Reads the PHY registers and stores the PHY ID and possibly the PHY
78 * revision in the hardware structure.
79 **/
igb_get_phy_id(struct e1000_hw * hw)80 s32 igb_get_phy_id(struct e1000_hw *hw)
81 {
82 struct e1000_phy_info *phy = &hw->phy;
83 s32 ret_val = 0;
84 u16 phy_id;
85
86 /* ensure PHY page selection to fix misconfigured i210 */
87 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211))
88 phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0);
89
90 ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id);
91 if (ret_val)
92 goto out;
93
94 phy->id = (u32)(phy_id << 16);
95 udelay(20);
96 ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id);
97 if (ret_val)
98 goto out;
99
100 phy->id |= (u32)(phy_id & PHY_REVISION_MASK);
101 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
102
103 out:
104 return ret_val;
105 }
106
107 /**
108 * igb_phy_reset_dsp - Reset PHY DSP
109 * @hw: pointer to the HW structure
110 *
111 * Reset the digital signal processor.
112 **/
igb_phy_reset_dsp(struct e1000_hw * hw)113 static s32 igb_phy_reset_dsp(struct e1000_hw *hw)
114 {
115 s32 ret_val = 0;
116
117 if (!(hw->phy.ops.write_reg))
118 goto out;
119
120 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xC1);
121 if (ret_val)
122 goto out;
123
124 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0);
125
126 out:
127 return ret_val;
128 }
129
130 /**
131 * igb_read_phy_reg_mdic - Read MDI control register
132 * @hw: pointer to the HW structure
133 * @offset: register offset to be read
134 * @data: pointer to the read data
135 *
136 * Reads the MDI control regsiter in the PHY at offset and stores the
137 * information read to data.
138 **/
igb_read_phy_reg_mdic(struct e1000_hw * hw,u32 offset,u16 * data)139 s32 igb_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
140 {
141 struct e1000_phy_info *phy = &hw->phy;
142 u32 i, mdic = 0;
143 s32 ret_val = 0;
144
145 if (offset > MAX_PHY_REG_ADDRESS) {
146 hw_dbg("PHY Address %d is out of range\n", offset);
147 ret_val = -E1000_ERR_PARAM;
148 goto out;
149 }
150
151 /* Set up Op-code, Phy Address, and register offset in the MDI
152 * Control register. The MAC will take care of interfacing with the
153 * PHY to retrieve the desired data.
154 */
155 mdic = ((offset << E1000_MDIC_REG_SHIFT) |
156 (phy->addr << E1000_MDIC_PHY_SHIFT) |
157 (E1000_MDIC_OP_READ));
158
159 wr32(E1000_MDIC, mdic);
160
161 /* Poll the ready bit to see if the MDI read completed
162 * Increasing the time out as testing showed failures with
163 * the lower time out
164 */
165 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
166 udelay(50);
167 mdic = rd32(E1000_MDIC);
168 if (mdic & E1000_MDIC_READY)
169 break;
170 }
171 if (!(mdic & E1000_MDIC_READY)) {
172 hw_dbg("MDI Read did not complete\n");
173 ret_val = -E1000_ERR_PHY;
174 goto out;
175 }
176 if (mdic & E1000_MDIC_ERROR) {
177 hw_dbg("MDI Error\n");
178 ret_val = -E1000_ERR_PHY;
179 goto out;
180 }
181 *data = (u16) mdic;
182
183 out:
184 return ret_val;
185 }
186
187 /**
188 * igb_write_phy_reg_mdic - Write MDI control register
189 * @hw: pointer to the HW structure
190 * @offset: register offset to write to
191 * @data: data to write to register at offset
192 *
193 * Writes data to MDI control register in the PHY at offset.
194 **/
igb_write_phy_reg_mdic(struct e1000_hw * hw,u32 offset,u16 data)195 s32 igb_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
196 {
197 struct e1000_phy_info *phy = &hw->phy;
198 u32 i, mdic = 0;
199 s32 ret_val = 0;
200
201 if (offset > MAX_PHY_REG_ADDRESS) {
202 hw_dbg("PHY Address %d is out of range\n", offset);
203 ret_val = -E1000_ERR_PARAM;
204 goto out;
205 }
206
207 /* Set up Op-code, Phy Address, and register offset in the MDI
208 * Control register. The MAC will take care of interfacing with the
209 * PHY to retrieve the desired data.
210 */
211 mdic = (((u32)data) |
212 (offset << E1000_MDIC_REG_SHIFT) |
213 (phy->addr << E1000_MDIC_PHY_SHIFT) |
214 (E1000_MDIC_OP_WRITE));
215
216 wr32(E1000_MDIC, mdic);
217
218 /* Poll the ready bit to see if the MDI read completed
219 * Increasing the time out as testing showed failures with
220 * the lower time out
221 */
222 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
223 udelay(50);
224 mdic = rd32(E1000_MDIC);
225 if (mdic & E1000_MDIC_READY)
226 break;
227 }
228 if (!(mdic & E1000_MDIC_READY)) {
229 hw_dbg("MDI Write did not complete\n");
230 ret_val = -E1000_ERR_PHY;
231 goto out;
232 }
233 if (mdic & E1000_MDIC_ERROR) {
234 hw_dbg("MDI Error\n");
235 ret_val = -E1000_ERR_PHY;
236 goto out;
237 }
238
239 out:
240 return ret_val;
241 }
242
243 /**
244 * igb_read_phy_reg_i2c - Read PHY register using i2c
245 * @hw: pointer to the HW structure
246 * @offset: register offset to be read
247 * @data: pointer to the read data
248 *
249 * Reads the PHY register at offset using the i2c interface and stores the
250 * retrieved information in data.
251 **/
igb_read_phy_reg_i2c(struct e1000_hw * hw,u32 offset,u16 * data)252 s32 igb_read_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 *data)
253 {
254 struct e1000_phy_info *phy = &hw->phy;
255 u32 i, i2ccmd = 0;
256
257 /* Set up Op-code, Phy Address, and register address in the I2CCMD
258 * register. The MAC will take care of interfacing with the
259 * PHY to retrieve the desired data.
260 */
261 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
262 (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) |
263 (E1000_I2CCMD_OPCODE_READ));
264
265 wr32(E1000_I2CCMD, i2ccmd);
266
267 /* Poll the ready bit to see if the I2C read completed */
268 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
269 udelay(50);
270 i2ccmd = rd32(E1000_I2CCMD);
271 if (i2ccmd & E1000_I2CCMD_READY)
272 break;
273 }
274 if (!(i2ccmd & E1000_I2CCMD_READY)) {
275 hw_dbg("I2CCMD Read did not complete\n");
276 return -E1000_ERR_PHY;
277 }
278 if (i2ccmd & E1000_I2CCMD_ERROR) {
279 hw_dbg("I2CCMD Error bit set\n");
280 return -E1000_ERR_PHY;
281 }
282
283 /* Need to byte-swap the 16-bit value. */
284 *data = ((i2ccmd >> 8) & 0x00FF) | ((i2ccmd << 8) & 0xFF00);
285
286 return 0;
287 }
288
289 /**
290 * igb_write_phy_reg_i2c - Write PHY register using i2c
291 * @hw: pointer to the HW structure
292 * @offset: register offset to write to
293 * @data: data to write at register offset
294 *
295 * Writes the data to PHY register at the offset using the i2c interface.
296 **/
igb_write_phy_reg_i2c(struct e1000_hw * hw,u32 offset,u16 data)297 s32 igb_write_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 data)
298 {
299 struct e1000_phy_info *phy = &hw->phy;
300 u32 i, i2ccmd = 0;
301 u16 phy_data_swapped;
302
303 /* Prevent overwritting SFP I2C EEPROM which is at A0 address.*/
304 if ((hw->phy.addr == 0) || (hw->phy.addr > 7)) {
305 hw_dbg("PHY I2C Address %d is out of range.\n",
306 hw->phy.addr);
307 return -E1000_ERR_CONFIG;
308 }
309
310 /* Swap the data bytes for the I2C interface */
311 phy_data_swapped = ((data >> 8) & 0x00FF) | ((data << 8) & 0xFF00);
312
313 /* Set up Op-code, Phy Address, and register address in the I2CCMD
314 * register. The MAC will take care of interfacing with the
315 * PHY to retrieve the desired data.
316 */
317 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
318 (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) |
319 E1000_I2CCMD_OPCODE_WRITE |
320 phy_data_swapped);
321
322 wr32(E1000_I2CCMD, i2ccmd);
323
324 /* Poll the ready bit to see if the I2C read completed */
325 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
326 udelay(50);
327 i2ccmd = rd32(E1000_I2CCMD);
328 if (i2ccmd & E1000_I2CCMD_READY)
329 break;
330 }
331 if (!(i2ccmd & E1000_I2CCMD_READY)) {
332 hw_dbg("I2CCMD Write did not complete\n");
333 return -E1000_ERR_PHY;
334 }
335 if (i2ccmd & E1000_I2CCMD_ERROR) {
336 hw_dbg("I2CCMD Error bit set\n");
337 return -E1000_ERR_PHY;
338 }
339
340 return 0;
341 }
342
343 /**
344 * igb_read_sfp_data_byte - Reads SFP module data.
345 * @hw: pointer to the HW structure
346 * @offset: byte location offset to be read
347 * @data: read data buffer pointer
348 *
349 * Reads one byte from SFP module data stored
350 * in SFP resided EEPROM memory or SFP diagnostic area.
351 * Function should be called with
352 * E1000_I2CCMD_SFP_DATA_ADDR(<byte offset>) for SFP module database access
353 * E1000_I2CCMD_SFP_DIAG_ADDR(<byte offset>) for SFP diagnostics parameters
354 * access
355 **/
igb_read_sfp_data_byte(struct e1000_hw * hw,u16 offset,u8 * data)356 s32 igb_read_sfp_data_byte(struct e1000_hw *hw, u16 offset, u8 *data)
357 {
358 u32 i = 0;
359 u32 i2ccmd = 0;
360 u32 data_local = 0;
361
362 if (offset > E1000_I2CCMD_SFP_DIAG_ADDR(255)) {
363 hw_dbg("I2CCMD command address exceeds upper limit\n");
364 return -E1000_ERR_PHY;
365 }
366
367 /* Set up Op-code, EEPROM Address,in the I2CCMD
368 * register. The MAC will take care of interfacing with the
369 * EEPROM to retrieve the desired data.
370 */
371 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
372 E1000_I2CCMD_OPCODE_READ);
373
374 wr32(E1000_I2CCMD, i2ccmd);
375
376 /* Poll the ready bit to see if the I2C read completed */
377 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
378 udelay(50);
379 data_local = rd32(E1000_I2CCMD);
380 if (data_local & E1000_I2CCMD_READY)
381 break;
382 }
383 if (!(data_local & E1000_I2CCMD_READY)) {
384 hw_dbg("I2CCMD Read did not complete\n");
385 return -E1000_ERR_PHY;
386 }
387 if (data_local & E1000_I2CCMD_ERROR) {
388 hw_dbg("I2CCMD Error bit set\n");
389 return -E1000_ERR_PHY;
390 }
391 *data = (u8) data_local & 0xFF;
392
393 return 0;
394 }
395
396 /**
397 * igb_read_phy_reg_igp - Read igp PHY register
398 * @hw: pointer to the HW structure
399 * @offset: register offset to be read
400 * @data: pointer to the read data
401 *
402 * Acquires semaphore, if necessary, then reads the PHY register at offset
403 * and storing the retrieved information in data. Release any acquired
404 * semaphores before exiting.
405 **/
igb_read_phy_reg_igp(struct e1000_hw * hw,u32 offset,u16 * data)406 s32 igb_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data)
407 {
408 s32 ret_val = 0;
409
410 if (!(hw->phy.ops.acquire))
411 goto out;
412
413 ret_val = hw->phy.ops.acquire(hw);
414 if (ret_val)
415 goto out;
416
417 if (offset > MAX_PHY_MULTI_PAGE_REG) {
418 ret_val = igb_write_phy_reg_mdic(hw,
419 IGP01E1000_PHY_PAGE_SELECT,
420 (u16)offset);
421 if (ret_val) {
422 hw->phy.ops.release(hw);
423 goto out;
424 }
425 }
426
427 ret_val = igb_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
428 data);
429
430 hw->phy.ops.release(hw);
431
432 out:
433 return ret_val;
434 }
435
436 /**
437 * igb_write_phy_reg_igp - Write igp PHY register
438 * @hw: pointer to the HW structure
439 * @offset: register offset to write to
440 * @data: data to write at register offset
441 *
442 * Acquires semaphore, if necessary, then writes the data to PHY register
443 * at the offset. Release any acquired semaphores before exiting.
444 **/
igb_write_phy_reg_igp(struct e1000_hw * hw,u32 offset,u16 data)445 s32 igb_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data)
446 {
447 s32 ret_val = 0;
448
449 if (!(hw->phy.ops.acquire))
450 goto out;
451
452 ret_val = hw->phy.ops.acquire(hw);
453 if (ret_val)
454 goto out;
455
456 if (offset > MAX_PHY_MULTI_PAGE_REG) {
457 ret_val = igb_write_phy_reg_mdic(hw,
458 IGP01E1000_PHY_PAGE_SELECT,
459 (u16)offset);
460 if (ret_val) {
461 hw->phy.ops.release(hw);
462 goto out;
463 }
464 }
465
466 ret_val = igb_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
467 data);
468
469 hw->phy.ops.release(hw);
470
471 out:
472 return ret_val;
473 }
474
475 /**
476 * igb_copper_link_setup_82580 - Setup 82580 PHY for copper link
477 * @hw: pointer to the HW structure
478 *
479 * Sets up Carrier-sense on Transmit and downshift values.
480 **/
igb_copper_link_setup_82580(struct e1000_hw * hw)481 s32 igb_copper_link_setup_82580(struct e1000_hw *hw)
482 {
483 struct e1000_phy_info *phy = &hw->phy;
484 s32 ret_val;
485 u16 phy_data;
486
487 if (phy->reset_disable) {
488 ret_val = 0;
489 goto out;
490 }
491
492 if (phy->type == e1000_phy_82580) {
493 ret_val = hw->phy.ops.reset(hw);
494 if (ret_val) {
495 hw_dbg("Error resetting the PHY.\n");
496 goto out;
497 }
498 }
499
500 /* Enable CRS on TX. This must be set for half-duplex operation. */
501 ret_val = phy->ops.read_reg(hw, I82580_CFG_REG, &phy_data);
502 if (ret_val)
503 goto out;
504
505 phy_data |= I82580_CFG_ASSERT_CRS_ON_TX;
506
507 /* Enable downshift */
508 phy_data |= I82580_CFG_ENABLE_DOWNSHIFT;
509
510 ret_val = phy->ops.write_reg(hw, I82580_CFG_REG, phy_data);
511 if (ret_val)
512 goto out;
513
514 /* Set MDI/MDIX mode */
515 ret_val = phy->ops.read_reg(hw, I82580_PHY_CTRL_2, &phy_data);
516 if (ret_val)
517 goto out;
518 phy_data &= ~I82580_PHY_CTRL2_MDIX_CFG_MASK;
519 /* Options:
520 * 0 - Auto (default)
521 * 1 - MDI mode
522 * 2 - MDI-X mode
523 */
524 switch (hw->phy.mdix) {
525 case 1:
526 break;
527 case 2:
528 phy_data |= I82580_PHY_CTRL2_MANUAL_MDIX;
529 break;
530 case 0:
531 default:
532 phy_data |= I82580_PHY_CTRL2_AUTO_MDI_MDIX;
533 break;
534 }
535 ret_val = hw->phy.ops.write_reg(hw, I82580_PHY_CTRL_2, phy_data);
536
537 out:
538 return ret_val;
539 }
540
541 /**
542 * igb_copper_link_setup_m88 - Setup m88 PHY's for copper link
543 * @hw: pointer to the HW structure
544 *
545 * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock
546 * and downshift values are set also.
547 **/
igb_copper_link_setup_m88(struct e1000_hw * hw)548 s32 igb_copper_link_setup_m88(struct e1000_hw *hw)
549 {
550 struct e1000_phy_info *phy = &hw->phy;
551 s32 ret_val;
552 u16 phy_data;
553
554 if (phy->reset_disable) {
555 ret_val = 0;
556 goto out;
557 }
558
559 /* Enable CRS on TX. This must be set for half-duplex operation. */
560 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
561 if (ret_val)
562 goto out;
563
564 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
565
566 /* Options:
567 * MDI/MDI-X = 0 (default)
568 * 0 - Auto for all speeds
569 * 1 - MDI mode
570 * 2 - MDI-X mode
571 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
572 */
573 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
574
575 switch (phy->mdix) {
576 case 1:
577 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
578 break;
579 case 2:
580 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
581 break;
582 case 3:
583 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
584 break;
585 case 0:
586 default:
587 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
588 break;
589 }
590
591 /* Options:
592 * disable_polarity_correction = 0 (default)
593 * Automatic Correction for Reversed Cable Polarity
594 * 0 - Disabled
595 * 1 - Enabled
596 */
597 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
598 if (phy->disable_polarity_correction == 1)
599 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
600
601 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
602 if (ret_val)
603 goto out;
604
605 if (phy->revision < E1000_REVISION_4) {
606 /* Force TX_CLK in the Extended PHY Specific Control Register
607 * to 25MHz clock.
608 */
609 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
610 &phy_data);
611 if (ret_val)
612 goto out;
613
614 phy_data |= M88E1000_EPSCR_TX_CLK_25;
615
616 if ((phy->revision == E1000_REVISION_2) &&
617 (phy->id == M88E1111_I_PHY_ID)) {
618 /* 82573L PHY - set the downshift counter to 5x. */
619 phy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK;
620 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
621 } else {
622 /* Configure Master and Slave downshift values */
623 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
624 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
625 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
626 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
627 }
628 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
629 phy_data);
630 if (ret_val)
631 goto out;
632 }
633
634 /* Commit the changes. */
635 ret_val = igb_phy_sw_reset(hw);
636 if (ret_val) {
637 hw_dbg("Error committing the PHY changes\n");
638 goto out;
639 }
640
641 out:
642 return ret_val;
643 }
644
645 /**
646 * igb_copper_link_setup_m88_gen2 - Setup m88 PHY's for copper link
647 * @hw: pointer to the HW structure
648 *
649 * Sets up MDI/MDI-X and polarity for i347-AT4, m88e1322 and m88e1112 PHY's.
650 * Also enables and sets the downshift parameters.
651 **/
igb_copper_link_setup_m88_gen2(struct e1000_hw * hw)652 s32 igb_copper_link_setup_m88_gen2(struct e1000_hw *hw)
653 {
654 struct e1000_phy_info *phy = &hw->phy;
655 s32 ret_val;
656 u16 phy_data;
657
658 if (phy->reset_disable)
659 return 0;
660
661 /* Enable CRS on Tx. This must be set for half-duplex operation. */
662 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
663 if (ret_val)
664 return ret_val;
665
666 /* Options:
667 * MDI/MDI-X = 0 (default)
668 * 0 - Auto for all speeds
669 * 1 - MDI mode
670 * 2 - MDI-X mode
671 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
672 */
673 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
674
675 switch (phy->mdix) {
676 case 1:
677 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
678 break;
679 case 2:
680 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
681 break;
682 case 3:
683 /* M88E1112 does not support this mode) */
684 if (phy->id != M88E1112_E_PHY_ID) {
685 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
686 break;
687 }
688 case 0:
689 default:
690 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
691 break;
692 }
693
694 /* Options:
695 * disable_polarity_correction = 0 (default)
696 * Automatic Correction for Reversed Cable Polarity
697 * 0 - Disabled
698 * 1 - Enabled
699 */
700 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
701 if (phy->disable_polarity_correction == 1)
702 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
703
704 /* Enable downshift and setting it to X6 */
705 if (phy->id == M88E1543_E_PHY_ID) {
706 phy_data &= ~I347AT4_PSCR_DOWNSHIFT_ENABLE;
707 ret_val =
708 phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
709 if (ret_val)
710 return ret_val;
711
712 ret_val = igb_phy_sw_reset(hw);
713 if (ret_val) {
714 hw_dbg("Error committing the PHY changes\n");
715 return ret_val;
716 }
717 }
718
719 phy_data &= ~I347AT4_PSCR_DOWNSHIFT_MASK;
720 phy_data |= I347AT4_PSCR_DOWNSHIFT_6X;
721 phy_data |= I347AT4_PSCR_DOWNSHIFT_ENABLE;
722
723 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
724 if (ret_val)
725 return ret_val;
726
727 /* Commit the changes. */
728 ret_val = igb_phy_sw_reset(hw);
729 if (ret_val) {
730 hw_dbg("Error committing the PHY changes\n");
731 return ret_val;
732 }
733 ret_val = igb_set_master_slave_mode(hw);
734 if (ret_val)
735 return ret_val;
736
737 return 0;
738 }
739
740 /**
741 * igb_copper_link_setup_igp - Setup igp PHY's for copper link
742 * @hw: pointer to the HW structure
743 *
744 * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for
745 * igp PHY's.
746 **/
igb_copper_link_setup_igp(struct e1000_hw * hw)747 s32 igb_copper_link_setup_igp(struct e1000_hw *hw)
748 {
749 struct e1000_phy_info *phy = &hw->phy;
750 s32 ret_val;
751 u16 data;
752
753 if (phy->reset_disable) {
754 ret_val = 0;
755 goto out;
756 }
757
758 ret_val = phy->ops.reset(hw);
759 if (ret_val) {
760 hw_dbg("Error resetting the PHY.\n");
761 goto out;
762 }
763
764 /* Wait 100ms for MAC to configure PHY from NVM settings, to avoid
765 * timeout issues when LFS is enabled.
766 */
767 msleep(100);
768
769 /* The NVM settings will configure LPLU in D3 for
770 * non-IGP1 PHYs.
771 */
772 if (phy->type == e1000_phy_igp) {
773 /* disable lplu d3 during driver init */
774 if (phy->ops.set_d3_lplu_state)
775 ret_val = phy->ops.set_d3_lplu_state(hw, false);
776 if (ret_val) {
777 hw_dbg("Error Disabling LPLU D3\n");
778 goto out;
779 }
780 }
781
782 /* disable lplu d0 during driver init */
783 ret_val = phy->ops.set_d0_lplu_state(hw, false);
784 if (ret_val) {
785 hw_dbg("Error Disabling LPLU D0\n");
786 goto out;
787 }
788 /* Configure mdi-mdix settings */
789 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &data);
790 if (ret_val)
791 goto out;
792
793 data &= ~IGP01E1000_PSCR_AUTO_MDIX;
794
795 switch (phy->mdix) {
796 case 1:
797 data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
798 break;
799 case 2:
800 data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
801 break;
802 case 0:
803 default:
804 data |= IGP01E1000_PSCR_AUTO_MDIX;
805 break;
806 }
807 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, data);
808 if (ret_val)
809 goto out;
810
811 /* set auto-master slave resolution settings */
812 if (hw->mac.autoneg) {
813 /* when autonegotiation advertisement is only 1000Mbps then we
814 * should disable SmartSpeed and enable Auto MasterSlave
815 * resolution as hardware default.
816 */
817 if (phy->autoneg_advertised == ADVERTISE_1000_FULL) {
818 /* Disable SmartSpeed */
819 ret_val = phy->ops.read_reg(hw,
820 IGP01E1000_PHY_PORT_CONFIG,
821 &data);
822 if (ret_val)
823 goto out;
824
825 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
826 ret_val = phy->ops.write_reg(hw,
827 IGP01E1000_PHY_PORT_CONFIG,
828 data);
829 if (ret_val)
830 goto out;
831
832 /* Set auto Master/Slave resolution process */
833 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data);
834 if (ret_val)
835 goto out;
836
837 data &= ~CR_1000T_MS_ENABLE;
838 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data);
839 if (ret_val)
840 goto out;
841 }
842
843 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data);
844 if (ret_val)
845 goto out;
846
847 /* load defaults for future use */
848 phy->original_ms_type = (data & CR_1000T_MS_ENABLE) ?
849 ((data & CR_1000T_MS_VALUE) ?
850 e1000_ms_force_master :
851 e1000_ms_force_slave) :
852 e1000_ms_auto;
853
854 switch (phy->ms_type) {
855 case e1000_ms_force_master:
856 data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
857 break;
858 case e1000_ms_force_slave:
859 data |= CR_1000T_MS_ENABLE;
860 data &= ~(CR_1000T_MS_VALUE);
861 break;
862 case e1000_ms_auto:
863 data &= ~CR_1000T_MS_ENABLE;
864 default:
865 break;
866 }
867 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data);
868 if (ret_val)
869 goto out;
870 }
871
872 out:
873 return ret_val;
874 }
875
876 /**
877 * igb_copper_link_autoneg - Setup/Enable autoneg for copper link
878 * @hw: pointer to the HW structure
879 *
880 * Performs initial bounds checking on autoneg advertisement parameter, then
881 * configure to advertise the full capability. Setup the PHY to autoneg
882 * and restart the negotiation process between the link partner. If
883 * autoneg_wait_to_complete, then wait for autoneg to complete before exiting.
884 **/
igb_copper_link_autoneg(struct e1000_hw * hw)885 static s32 igb_copper_link_autoneg(struct e1000_hw *hw)
886 {
887 struct e1000_phy_info *phy = &hw->phy;
888 s32 ret_val;
889 u16 phy_ctrl;
890
891 /* Perform some bounds checking on the autoneg advertisement
892 * parameter.
893 */
894 phy->autoneg_advertised &= phy->autoneg_mask;
895
896 /* If autoneg_advertised is zero, we assume it was not defaulted
897 * by the calling code so we set to advertise full capability.
898 */
899 if (phy->autoneg_advertised == 0)
900 phy->autoneg_advertised = phy->autoneg_mask;
901
902 hw_dbg("Reconfiguring auto-neg advertisement params\n");
903 ret_val = igb_phy_setup_autoneg(hw);
904 if (ret_val) {
905 hw_dbg("Error Setting up Auto-Negotiation\n");
906 goto out;
907 }
908 hw_dbg("Restarting Auto-Neg\n");
909
910 /* Restart auto-negotiation by setting the Auto Neg Enable bit and
911 * the Auto Neg Restart bit in the PHY control register.
912 */
913 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_ctrl);
914 if (ret_val)
915 goto out;
916
917 phy_ctrl |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
918 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_ctrl);
919 if (ret_val)
920 goto out;
921
922 /* Does the user want to wait for Auto-Neg to complete here, or
923 * check at a later time (for example, callback routine).
924 */
925 if (phy->autoneg_wait_to_complete) {
926 ret_val = igb_wait_autoneg(hw);
927 if (ret_val) {
928 hw_dbg("Error while waiting for autoneg to complete\n");
929 goto out;
930 }
931 }
932
933 hw->mac.get_link_status = true;
934
935 out:
936 return ret_val;
937 }
938
939 /**
940 * igb_phy_setup_autoneg - Configure PHY for auto-negotiation
941 * @hw: pointer to the HW structure
942 *
943 * Reads the MII auto-neg advertisement register and/or the 1000T control
944 * register and if the PHY is already setup for auto-negotiation, then
945 * return successful. Otherwise, setup advertisement and flow control to
946 * the appropriate values for the wanted auto-negotiation.
947 **/
igb_phy_setup_autoneg(struct e1000_hw * hw)948 static s32 igb_phy_setup_autoneg(struct e1000_hw *hw)
949 {
950 struct e1000_phy_info *phy = &hw->phy;
951 s32 ret_val;
952 u16 mii_autoneg_adv_reg;
953 u16 mii_1000t_ctrl_reg = 0;
954
955 phy->autoneg_advertised &= phy->autoneg_mask;
956
957 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
958 ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
959 if (ret_val)
960 goto out;
961
962 if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
963 /* Read the MII 1000Base-T Control Register (Address 9). */
964 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL,
965 &mii_1000t_ctrl_reg);
966 if (ret_val)
967 goto out;
968 }
969
970 /* Need to parse both autoneg_advertised and fc and set up
971 * the appropriate PHY registers. First we will parse for
972 * autoneg_advertised software override. Since we can advertise
973 * a plethora of combinations, we need to check each bit
974 * individually.
975 */
976
977 /* First we clear all the 10/100 mb speed bits in the Auto-Neg
978 * Advertisement Register (Address 4) and the 1000 mb speed bits in
979 * the 1000Base-T Control Register (Address 9).
980 */
981 mii_autoneg_adv_reg &= ~(NWAY_AR_100TX_FD_CAPS |
982 NWAY_AR_100TX_HD_CAPS |
983 NWAY_AR_10T_FD_CAPS |
984 NWAY_AR_10T_HD_CAPS);
985 mii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS);
986
987 hw_dbg("autoneg_advertised %x\n", phy->autoneg_advertised);
988
989 /* Do we want to advertise 10 Mb Half Duplex? */
990 if (phy->autoneg_advertised & ADVERTISE_10_HALF) {
991 hw_dbg("Advertise 10mb Half duplex\n");
992 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
993 }
994
995 /* Do we want to advertise 10 Mb Full Duplex? */
996 if (phy->autoneg_advertised & ADVERTISE_10_FULL) {
997 hw_dbg("Advertise 10mb Full duplex\n");
998 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
999 }
1000
1001 /* Do we want to advertise 100 Mb Half Duplex? */
1002 if (phy->autoneg_advertised & ADVERTISE_100_HALF) {
1003 hw_dbg("Advertise 100mb Half duplex\n");
1004 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
1005 }
1006
1007 /* Do we want to advertise 100 Mb Full Duplex? */
1008 if (phy->autoneg_advertised & ADVERTISE_100_FULL) {
1009 hw_dbg("Advertise 100mb Full duplex\n");
1010 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
1011 }
1012
1013 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
1014 if (phy->autoneg_advertised & ADVERTISE_1000_HALF)
1015 hw_dbg("Advertise 1000mb Half duplex request denied!\n");
1016
1017 /* Do we want to advertise 1000 Mb Full Duplex? */
1018 if (phy->autoneg_advertised & ADVERTISE_1000_FULL) {
1019 hw_dbg("Advertise 1000mb Full duplex\n");
1020 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
1021 }
1022
1023 /* Check for a software override of the flow control settings, and
1024 * setup the PHY advertisement registers accordingly. If
1025 * auto-negotiation is enabled, then software will have to set the
1026 * "PAUSE" bits to the correct value in the Auto-Negotiation
1027 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-
1028 * negotiation.
1029 *
1030 * The possible values of the "fc" parameter are:
1031 * 0: Flow control is completely disabled
1032 * 1: Rx flow control is enabled (we can receive pause frames
1033 * but not send pause frames).
1034 * 2: Tx flow control is enabled (we can send pause frames
1035 * but we do not support receiving pause frames).
1036 * 3: Both Rx and TX flow control (symmetric) are enabled.
1037 * other: No software override. The flow control configuration
1038 * in the EEPROM is used.
1039 */
1040 switch (hw->fc.current_mode) {
1041 case e1000_fc_none:
1042 /* Flow control (RX & TX) is completely disabled by a
1043 * software over-ride.
1044 */
1045 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1046 break;
1047 case e1000_fc_rx_pause:
1048 /* RX Flow control is enabled, and TX Flow control is
1049 * disabled, by a software over-ride.
1050 *
1051 * Since there really isn't a way to advertise that we are
1052 * capable of RX Pause ONLY, we will advertise that we
1053 * support both symmetric and asymmetric RX PAUSE. Later
1054 * (in e1000_config_fc_after_link_up) we will disable the
1055 * hw's ability to send PAUSE frames.
1056 */
1057 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1058 break;
1059 case e1000_fc_tx_pause:
1060 /* TX Flow control is enabled, and RX Flow control is
1061 * disabled, by a software over-ride.
1062 */
1063 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
1064 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
1065 break;
1066 case e1000_fc_full:
1067 /* Flow control (both RX and TX) is enabled by a software
1068 * over-ride.
1069 */
1070 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1071 break;
1072 default:
1073 hw_dbg("Flow control param set incorrectly\n");
1074 ret_val = -E1000_ERR_CONFIG;
1075 goto out;
1076 }
1077
1078 ret_val = phy->ops.write_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
1079 if (ret_val)
1080 goto out;
1081
1082 hw_dbg("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
1083
1084 if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
1085 ret_val = phy->ops.write_reg(hw,
1086 PHY_1000T_CTRL,
1087 mii_1000t_ctrl_reg);
1088 if (ret_val)
1089 goto out;
1090 }
1091
1092 out:
1093 return ret_val;
1094 }
1095
1096 /**
1097 * igb_setup_copper_link - Configure copper link settings
1098 * @hw: pointer to the HW structure
1099 *
1100 * Calls the appropriate function to configure the link for auto-neg or forced
1101 * speed and duplex. Then we check for link, once link is established calls
1102 * to configure collision distance and flow control are called. If link is
1103 * not established, we return -E1000_ERR_PHY (-2).
1104 **/
igb_setup_copper_link(struct e1000_hw * hw)1105 s32 igb_setup_copper_link(struct e1000_hw *hw)
1106 {
1107 s32 ret_val;
1108 bool link;
1109
1110 if (hw->mac.autoneg) {
1111 /* Setup autoneg and flow control advertisement and perform
1112 * autonegotiation.
1113 */
1114 ret_val = igb_copper_link_autoneg(hw);
1115 if (ret_val)
1116 goto out;
1117 } else {
1118 /* PHY will be set to 10H, 10F, 100H or 100F
1119 * depending on user settings.
1120 */
1121 hw_dbg("Forcing Speed and Duplex\n");
1122 ret_val = hw->phy.ops.force_speed_duplex(hw);
1123 if (ret_val) {
1124 hw_dbg("Error Forcing Speed and Duplex\n");
1125 goto out;
1126 }
1127 }
1128
1129 /* Check link status. Wait up to 100 microseconds for link to become
1130 * valid.
1131 */
1132 ret_val = igb_phy_has_link(hw, COPPER_LINK_UP_LIMIT, 10, &link);
1133 if (ret_val)
1134 goto out;
1135
1136 if (link) {
1137 hw_dbg("Valid link established!!!\n");
1138 igb_config_collision_dist(hw);
1139 ret_val = igb_config_fc_after_link_up(hw);
1140 } else {
1141 hw_dbg("Unable to establish link!!!\n");
1142 }
1143
1144 out:
1145 return ret_val;
1146 }
1147
1148 /**
1149 * igb_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY
1150 * @hw: pointer to the HW structure
1151 *
1152 * Calls the PHY setup function to force speed and duplex. Clears the
1153 * auto-crossover to force MDI manually. Waits for link and returns
1154 * successful if link up is successful, else -E1000_ERR_PHY (-2).
1155 **/
igb_phy_force_speed_duplex_igp(struct e1000_hw * hw)1156 s32 igb_phy_force_speed_duplex_igp(struct e1000_hw *hw)
1157 {
1158 struct e1000_phy_info *phy = &hw->phy;
1159 s32 ret_val;
1160 u16 phy_data;
1161 bool link;
1162
1163 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
1164 if (ret_val)
1165 goto out;
1166
1167 igb_phy_force_speed_duplex_setup(hw, &phy_data);
1168
1169 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
1170 if (ret_val)
1171 goto out;
1172
1173 /* Clear Auto-Crossover to force MDI manually. IGP requires MDI
1174 * forced whenever speed and duplex are forced.
1175 */
1176 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
1177 if (ret_val)
1178 goto out;
1179
1180 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1181 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1182
1183 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
1184 if (ret_val)
1185 goto out;
1186
1187 hw_dbg("IGP PSCR: %X\n", phy_data);
1188
1189 udelay(1);
1190
1191 if (phy->autoneg_wait_to_complete) {
1192 hw_dbg("Waiting for forced speed/duplex link on IGP phy.\n");
1193
1194 ret_val = igb_phy_has_link(hw, PHY_FORCE_LIMIT, 10000, &link);
1195 if (ret_val)
1196 goto out;
1197
1198 if (!link)
1199 hw_dbg("Link taking longer than expected.\n");
1200
1201 /* Try once more */
1202 ret_val = igb_phy_has_link(hw, PHY_FORCE_LIMIT, 10000, &link);
1203 if (ret_val)
1204 goto out;
1205 }
1206
1207 out:
1208 return ret_val;
1209 }
1210
1211 /**
1212 * igb_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY
1213 * @hw: pointer to the HW structure
1214 *
1215 * Calls the PHY setup function to force speed and duplex. Clears the
1216 * auto-crossover to force MDI manually. Resets the PHY to commit the
1217 * changes. If time expires while waiting for link up, we reset the DSP.
1218 * After reset, TX_CLK and CRS on TX must be set. Return successful upon
1219 * successful completion, else return corresponding error code.
1220 **/
igb_phy_force_speed_duplex_m88(struct e1000_hw * hw)1221 s32 igb_phy_force_speed_duplex_m88(struct e1000_hw *hw)
1222 {
1223 struct e1000_phy_info *phy = &hw->phy;
1224 s32 ret_val;
1225 u16 phy_data;
1226 bool link;
1227
1228 /* I210 and I211 devices support Auto-Crossover in forced operation. */
1229 if (phy->type != e1000_phy_i210) {
1230 /* Clear Auto-Crossover to force MDI manually. M88E1000
1231 * requires MDI forced whenever speed and duplex are forced.
1232 */
1233 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL,
1234 &phy_data);
1235 if (ret_val)
1236 goto out;
1237
1238 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1239 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL,
1240 phy_data);
1241 if (ret_val)
1242 goto out;
1243
1244 hw_dbg("M88E1000 PSCR: %X\n", phy_data);
1245 }
1246
1247 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
1248 if (ret_val)
1249 goto out;
1250
1251 igb_phy_force_speed_duplex_setup(hw, &phy_data);
1252
1253 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
1254 if (ret_val)
1255 goto out;
1256
1257 /* Reset the phy to commit changes. */
1258 ret_val = igb_phy_sw_reset(hw);
1259 if (ret_val)
1260 goto out;
1261
1262 if (phy->autoneg_wait_to_complete) {
1263 hw_dbg("Waiting for forced speed/duplex link on M88 phy.\n");
1264
1265 ret_val = igb_phy_has_link(hw, PHY_FORCE_LIMIT, 100000, &link);
1266 if (ret_val)
1267 goto out;
1268
1269 if (!link) {
1270 bool reset_dsp = true;
1271
1272 switch (hw->phy.id) {
1273 case I347AT4_E_PHY_ID:
1274 case M88E1112_E_PHY_ID:
1275 case I210_I_PHY_ID:
1276 reset_dsp = false;
1277 break;
1278 default:
1279 if (hw->phy.type != e1000_phy_m88)
1280 reset_dsp = false;
1281 break;
1282 }
1283 if (!reset_dsp)
1284 hw_dbg("Link taking longer than expected.\n");
1285 else {
1286 /* We didn't get link.
1287 * Reset the DSP and cross our fingers.
1288 */
1289 ret_val = phy->ops.write_reg(hw,
1290 M88E1000_PHY_PAGE_SELECT,
1291 0x001d);
1292 if (ret_val)
1293 goto out;
1294 ret_val = igb_phy_reset_dsp(hw);
1295 if (ret_val)
1296 goto out;
1297 }
1298 }
1299
1300 /* Try once more */
1301 ret_val = igb_phy_has_link(hw, PHY_FORCE_LIMIT,
1302 100000, &link);
1303 if (ret_val)
1304 goto out;
1305 }
1306
1307 if (hw->phy.type != e1000_phy_m88 ||
1308 hw->phy.id == I347AT4_E_PHY_ID ||
1309 hw->phy.id == M88E1112_E_PHY_ID ||
1310 hw->phy.id == I210_I_PHY_ID)
1311 goto out;
1312
1313 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
1314 if (ret_val)
1315 goto out;
1316
1317 /* Resetting the phy means we need to re-force TX_CLK in the
1318 * Extended PHY Specific Control Register to 25MHz clock from
1319 * the reset value of 2.5MHz.
1320 */
1321 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1322 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
1323 if (ret_val)
1324 goto out;
1325
1326 /* In addition, we must re-enable CRS on Tx for both half and full
1327 * duplex.
1328 */
1329 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1330 if (ret_val)
1331 goto out;
1332
1333 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1334 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1335
1336 out:
1337 return ret_val;
1338 }
1339
1340 /**
1341 * igb_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex
1342 * @hw: pointer to the HW structure
1343 * @phy_ctrl: pointer to current value of PHY_CONTROL
1344 *
1345 * Forces speed and duplex on the PHY by doing the following: disable flow
1346 * control, force speed/duplex on the MAC, disable auto speed detection,
1347 * disable auto-negotiation, configure duplex, configure speed, configure
1348 * the collision distance, write configuration to CTRL register. The
1349 * caller must write to the PHY_CONTROL register for these settings to
1350 * take affect.
1351 **/
igb_phy_force_speed_duplex_setup(struct e1000_hw * hw,u16 * phy_ctrl)1352 static void igb_phy_force_speed_duplex_setup(struct e1000_hw *hw,
1353 u16 *phy_ctrl)
1354 {
1355 struct e1000_mac_info *mac = &hw->mac;
1356 u32 ctrl;
1357
1358 /* Turn off flow control when forcing speed/duplex */
1359 hw->fc.current_mode = e1000_fc_none;
1360
1361 /* Force speed/duplex on the mac */
1362 ctrl = rd32(E1000_CTRL);
1363 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1364 ctrl &= ~E1000_CTRL_SPD_SEL;
1365
1366 /* Disable Auto Speed Detection */
1367 ctrl &= ~E1000_CTRL_ASDE;
1368
1369 /* Disable autoneg on the phy */
1370 *phy_ctrl &= ~MII_CR_AUTO_NEG_EN;
1371
1372 /* Forcing Full or Half Duplex? */
1373 if (mac->forced_speed_duplex & E1000_ALL_HALF_DUPLEX) {
1374 ctrl &= ~E1000_CTRL_FD;
1375 *phy_ctrl &= ~MII_CR_FULL_DUPLEX;
1376 hw_dbg("Half Duplex\n");
1377 } else {
1378 ctrl |= E1000_CTRL_FD;
1379 *phy_ctrl |= MII_CR_FULL_DUPLEX;
1380 hw_dbg("Full Duplex\n");
1381 }
1382
1383 /* Forcing 10mb or 100mb? */
1384 if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) {
1385 ctrl |= E1000_CTRL_SPD_100;
1386 *phy_ctrl |= MII_CR_SPEED_100;
1387 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10);
1388 hw_dbg("Forcing 100mb\n");
1389 } else {
1390 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1391 *phy_ctrl |= MII_CR_SPEED_10;
1392 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);
1393 hw_dbg("Forcing 10mb\n");
1394 }
1395
1396 igb_config_collision_dist(hw);
1397
1398 wr32(E1000_CTRL, ctrl);
1399 }
1400
1401 /**
1402 * igb_set_d3_lplu_state - Sets low power link up state for D3
1403 * @hw: pointer to the HW structure
1404 * @active: boolean used to enable/disable lplu
1405 *
1406 * Success returns 0, Failure returns 1
1407 *
1408 * The low power link up (lplu) state is set to the power management level D3
1409 * and SmartSpeed is disabled when active is true, else clear lplu for D3
1410 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
1411 * is used during Dx states where the power conservation is most important.
1412 * During driver activity, SmartSpeed should be enabled so performance is
1413 * maintained.
1414 **/
igb_set_d3_lplu_state(struct e1000_hw * hw,bool active)1415 s32 igb_set_d3_lplu_state(struct e1000_hw *hw, bool active)
1416 {
1417 struct e1000_phy_info *phy = &hw->phy;
1418 s32 ret_val = 0;
1419 u16 data;
1420
1421 if (!(hw->phy.ops.read_reg))
1422 goto out;
1423
1424 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
1425 if (ret_val)
1426 goto out;
1427
1428 if (!active) {
1429 data &= ~IGP02E1000_PM_D3_LPLU;
1430 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
1431 data);
1432 if (ret_val)
1433 goto out;
1434 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
1435 * during Dx states where the power conservation is most
1436 * important. During driver activity we should enable
1437 * SmartSpeed, so performance is maintained.
1438 */
1439 if (phy->smart_speed == e1000_smart_speed_on) {
1440 ret_val = phy->ops.read_reg(hw,
1441 IGP01E1000_PHY_PORT_CONFIG,
1442 &data);
1443 if (ret_val)
1444 goto out;
1445
1446 data |= IGP01E1000_PSCFR_SMART_SPEED;
1447 ret_val = phy->ops.write_reg(hw,
1448 IGP01E1000_PHY_PORT_CONFIG,
1449 data);
1450 if (ret_val)
1451 goto out;
1452 } else if (phy->smart_speed == e1000_smart_speed_off) {
1453 ret_val = phy->ops.read_reg(hw,
1454 IGP01E1000_PHY_PORT_CONFIG,
1455 &data);
1456 if (ret_val)
1457 goto out;
1458
1459 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1460 ret_val = phy->ops.write_reg(hw,
1461 IGP01E1000_PHY_PORT_CONFIG,
1462 data);
1463 if (ret_val)
1464 goto out;
1465 }
1466 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
1467 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
1468 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
1469 data |= IGP02E1000_PM_D3_LPLU;
1470 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
1471 data);
1472 if (ret_val)
1473 goto out;
1474
1475 /* When LPLU is enabled, we should disable SmartSpeed */
1476 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1477 &data);
1478 if (ret_val)
1479 goto out;
1480
1481 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1482 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1483 data);
1484 }
1485
1486 out:
1487 return ret_val;
1488 }
1489
1490 /**
1491 * igb_check_downshift - Checks whether a downshift in speed occurred
1492 * @hw: pointer to the HW structure
1493 *
1494 * Success returns 0, Failure returns 1
1495 *
1496 * A downshift is detected by querying the PHY link health.
1497 **/
igb_check_downshift(struct e1000_hw * hw)1498 s32 igb_check_downshift(struct e1000_hw *hw)
1499 {
1500 struct e1000_phy_info *phy = &hw->phy;
1501 s32 ret_val;
1502 u16 phy_data, offset, mask;
1503
1504 switch (phy->type) {
1505 case e1000_phy_i210:
1506 case e1000_phy_m88:
1507 case e1000_phy_gg82563:
1508 offset = M88E1000_PHY_SPEC_STATUS;
1509 mask = M88E1000_PSSR_DOWNSHIFT;
1510 break;
1511 case e1000_phy_igp_2:
1512 case e1000_phy_igp:
1513 case e1000_phy_igp_3:
1514 offset = IGP01E1000_PHY_LINK_HEALTH;
1515 mask = IGP01E1000_PLHR_SS_DOWNGRADE;
1516 break;
1517 default:
1518 /* speed downshift not supported */
1519 phy->speed_downgraded = false;
1520 ret_val = 0;
1521 goto out;
1522 }
1523
1524 ret_val = phy->ops.read_reg(hw, offset, &phy_data);
1525
1526 if (!ret_val)
1527 phy->speed_downgraded = (phy_data & mask) ? true : false;
1528
1529 out:
1530 return ret_val;
1531 }
1532
1533 /**
1534 * igb_check_polarity_m88 - Checks the polarity.
1535 * @hw: pointer to the HW structure
1536 *
1537 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1538 *
1539 * Polarity is determined based on the PHY specific status register.
1540 **/
igb_check_polarity_m88(struct e1000_hw * hw)1541 s32 igb_check_polarity_m88(struct e1000_hw *hw)
1542 {
1543 struct e1000_phy_info *phy = &hw->phy;
1544 s32 ret_val;
1545 u16 data;
1546
1547 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &data);
1548
1549 if (!ret_val)
1550 phy->cable_polarity = (data & M88E1000_PSSR_REV_POLARITY)
1551 ? e1000_rev_polarity_reversed
1552 : e1000_rev_polarity_normal;
1553
1554 return ret_val;
1555 }
1556
1557 /**
1558 * igb_check_polarity_igp - Checks the polarity.
1559 * @hw: pointer to the HW structure
1560 *
1561 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1562 *
1563 * Polarity is determined based on the PHY port status register, and the
1564 * current speed (since there is no polarity at 100Mbps).
1565 **/
igb_check_polarity_igp(struct e1000_hw * hw)1566 static s32 igb_check_polarity_igp(struct e1000_hw *hw)
1567 {
1568 struct e1000_phy_info *phy = &hw->phy;
1569 s32 ret_val;
1570 u16 data, offset, mask;
1571
1572 /* Polarity is determined based on the speed of
1573 * our connection.
1574 */
1575 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data);
1576 if (ret_val)
1577 goto out;
1578
1579 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
1580 IGP01E1000_PSSR_SPEED_1000MBPS) {
1581 offset = IGP01E1000_PHY_PCS_INIT_REG;
1582 mask = IGP01E1000_PHY_POLARITY_MASK;
1583 } else {
1584 /* This really only applies to 10Mbps since
1585 * there is no polarity for 100Mbps (always 0).
1586 */
1587 offset = IGP01E1000_PHY_PORT_STATUS;
1588 mask = IGP01E1000_PSSR_POLARITY_REVERSED;
1589 }
1590
1591 ret_val = phy->ops.read_reg(hw, offset, &data);
1592
1593 if (!ret_val)
1594 phy->cable_polarity = (data & mask)
1595 ? e1000_rev_polarity_reversed
1596 : e1000_rev_polarity_normal;
1597
1598 out:
1599 return ret_val;
1600 }
1601
1602 /**
1603 * igb_wait_autoneg - Wait for auto-neg completion
1604 * @hw: pointer to the HW structure
1605 *
1606 * Waits for auto-negotiation to complete or for the auto-negotiation time
1607 * limit to expire, which ever happens first.
1608 **/
igb_wait_autoneg(struct e1000_hw * hw)1609 static s32 igb_wait_autoneg(struct e1000_hw *hw)
1610 {
1611 s32 ret_val = 0;
1612 u16 i, phy_status;
1613
1614 /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */
1615 for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) {
1616 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
1617 if (ret_val)
1618 break;
1619 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
1620 if (ret_val)
1621 break;
1622 if (phy_status & MII_SR_AUTONEG_COMPLETE)
1623 break;
1624 msleep(100);
1625 }
1626
1627 /* PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation
1628 * has completed.
1629 */
1630 return ret_val;
1631 }
1632
1633 /**
1634 * igb_phy_has_link - Polls PHY for link
1635 * @hw: pointer to the HW structure
1636 * @iterations: number of times to poll for link
1637 * @usec_interval: delay between polling attempts
1638 * @success: pointer to whether polling was successful or not
1639 *
1640 * Polls the PHY status register for link, 'iterations' number of times.
1641 **/
igb_phy_has_link(struct e1000_hw * hw,u32 iterations,u32 usec_interval,bool * success)1642 s32 igb_phy_has_link(struct e1000_hw *hw, u32 iterations,
1643 u32 usec_interval, bool *success)
1644 {
1645 s32 ret_val = 0;
1646 u16 i, phy_status;
1647
1648 for (i = 0; i < iterations; i++) {
1649 /* Some PHYs require the PHY_STATUS register to be read
1650 * twice due to the link bit being sticky. No harm doing
1651 * it across the board.
1652 */
1653 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
1654 if (ret_val && usec_interval > 0) {
1655 /* If the first read fails, another entity may have
1656 * ownership of the resources, wait and try again to
1657 * see if they have relinquished the resources yet.
1658 */
1659 if (usec_interval >= 1000)
1660 mdelay(usec_interval/1000);
1661 else
1662 udelay(usec_interval);
1663 }
1664 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
1665 if (ret_val)
1666 break;
1667 if (phy_status & MII_SR_LINK_STATUS)
1668 break;
1669 if (usec_interval >= 1000)
1670 mdelay(usec_interval/1000);
1671 else
1672 udelay(usec_interval);
1673 }
1674
1675 *success = (i < iterations) ? true : false;
1676
1677 return ret_val;
1678 }
1679
1680 /**
1681 * igb_get_cable_length_m88 - Determine cable length for m88 PHY
1682 * @hw: pointer to the HW structure
1683 *
1684 * Reads the PHY specific status register to retrieve the cable length
1685 * information. The cable length is determined by averaging the minimum and
1686 * maximum values to get the "average" cable length. The m88 PHY has four
1687 * possible cable length values, which are:
1688 * Register Value Cable Length
1689 * 0 < 50 meters
1690 * 1 50 - 80 meters
1691 * 2 80 - 110 meters
1692 * 3 110 - 140 meters
1693 * 4 > 140 meters
1694 **/
igb_get_cable_length_m88(struct e1000_hw * hw)1695 s32 igb_get_cable_length_m88(struct e1000_hw *hw)
1696 {
1697 struct e1000_phy_info *phy = &hw->phy;
1698 s32 ret_val;
1699 u16 phy_data, index;
1700
1701 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
1702 if (ret_val)
1703 goto out;
1704
1705 index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
1706 M88E1000_PSSR_CABLE_LENGTH_SHIFT;
1707 if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1) {
1708 ret_val = -E1000_ERR_PHY;
1709 goto out;
1710 }
1711
1712 phy->min_cable_length = e1000_m88_cable_length_table[index];
1713 phy->max_cable_length = e1000_m88_cable_length_table[index + 1];
1714
1715 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
1716
1717 out:
1718 return ret_val;
1719 }
1720
igb_get_cable_length_m88_gen2(struct e1000_hw * hw)1721 s32 igb_get_cable_length_m88_gen2(struct e1000_hw *hw)
1722 {
1723 struct e1000_phy_info *phy = &hw->phy;
1724 s32 ret_val;
1725 u16 phy_data, phy_data2, index, default_page, is_cm;
1726
1727 switch (hw->phy.id) {
1728 case I210_I_PHY_ID:
1729 /* Get cable length from PHY Cable Diagnostics Control Reg */
1730 ret_val = phy->ops.read_reg(hw, (0x7 << GS40G_PAGE_SHIFT) +
1731 (I347AT4_PCDL + phy->addr),
1732 &phy_data);
1733 if (ret_val)
1734 return ret_val;
1735
1736 /* Check if the unit of cable length is meters or cm */
1737 ret_val = phy->ops.read_reg(hw, (0x7 << GS40G_PAGE_SHIFT) +
1738 I347AT4_PCDC, &phy_data2);
1739 if (ret_val)
1740 return ret_val;
1741
1742 is_cm = !(phy_data2 & I347AT4_PCDC_CABLE_LENGTH_UNIT);
1743
1744 /* Populate the phy structure with cable length in meters */
1745 phy->min_cable_length = phy_data / (is_cm ? 100 : 1);
1746 phy->max_cable_length = phy_data / (is_cm ? 100 : 1);
1747 phy->cable_length = phy_data / (is_cm ? 100 : 1);
1748 break;
1749 case M88E1543_E_PHY_ID:
1750 case I347AT4_E_PHY_ID:
1751 /* Remember the original page select and set it to 7 */
1752 ret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT,
1753 &default_page);
1754 if (ret_val)
1755 goto out;
1756
1757 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x07);
1758 if (ret_val)
1759 goto out;
1760
1761 /* Get cable length from PHY Cable Diagnostics Control Reg */
1762 ret_val = phy->ops.read_reg(hw, (I347AT4_PCDL + phy->addr),
1763 &phy_data);
1764 if (ret_val)
1765 goto out;
1766
1767 /* Check if the unit of cable length is meters or cm */
1768 ret_val = phy->ops.read_reg(hw, I347AT4_PCDC, &phy_data2);
1769 if (ret_val)
1770 goto out;
1771
1772 is_cm = !(phy_data2 & I347AT4_PCDC_CABLE_LENGTH_UNIT);
1773
1774 /* Populate the phy structure with cable length in meters */
1775 phy->min_cable_length = phy_data / (is_cm ? 100 : 1);
1776 phy->max_cable_length = phy_data / (is_cm ? 100 : 1);
1777 phy->cable_length = phy_data / (is_cm ? 100 : 1);
1778
1779 /* Reset the page selec to its original value */
1780 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT,
1781 default_page);
1782 if (ret_val)
1783 goto out;
1784 break;
1785 case M88E1112_E_PHY_ID:
1786 /* Remember the original page select and set it to 5 */
1787 ret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT,
1788 &default_page);
1789 if (ret_val)
1790 goto out;
1791
1792 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x05);
1793 if (ret_val)
1794 goto out;
1795
1796 ret_val = phy->ops.read_reg(hw, M88E1112_VCT_DSP_DISTANCE,
1797 &phy_data);
1798 if (ret_val)
1799 goto out;
1800
1801 index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
1802 M88E1000_PSSR_CABLE_LENGTH_SHIFT;
1803 if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1) {
1804 ret_val = -E1000_ERR_PHY;
1805 goto out;
1806 }
1807
1808 phy->min_cable_length = e1000_m88_cable_length_table[index];
1809 phy->max_cable_length = e1000_m88_cable_length_table[index + 1];
1810
1811 phy->cable_length = (phy->min_cable_length +
1812 phy->max_cable_length) / 2;
1813
1814 /* Reset the page select to its original value */
1815 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT,
1816 default_page);
1817 if (ret_val)
1818 goto out;
1819
1820 break;
1821 default:
1822 ret_val = -E1000_ERR_PHY;
1823 goto out;
1824 }
1825
1826 out:
1827 return ret_val;
1828 }
1829
1830 /**
1831 * igb_get_cable_length_igp_2 - Determine cable length for igp2 PHY
1832 * @hw: pointer to the HW structure
1833 *
1834 * The automatic gain control (agc) normalizes the amplitude of the
1835 * received signal, adjusting for the attenuation produced by the
1836 * cable. By reading the AGC registers, which represent the
1837 * combination of coarse and fine gain value, the value can be put
1838 * into a lookup table to obtain the approximate cable length
1839 * for each channel.
1840 **/
igb_get_cable_length_igp_2(struct e1000_hw * hw)1841 s32 igb_get_cable_length_igp_2(struct e1000_hw *hw)
1842 {
1843 struct e1000_phy_info *phy = &hw->phy;
1844 s32 ret_val = 0;
1845 u16 phy_data, i, agc_value = 0;
1846 u16 cur_agc_index, max_agc_index = 0;
1847 u16 min_agc_index = IGP02E1000_CABLE_LENGTH_TABLE_SIZE - 1;
1848 static const u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = {
1849 IGP02E1000_PHY_AGC_A,
1850 IGP02E1000_PHY_AGC_B,
1851 IGP02E1000_PHY_AGC_C,
1852 IGP02E1000_PHY_AGC_D
1853 };
1854
1855 /* Read the AGC registers for all channels */
1856 for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) {
1857 ret_val = phy->ops.read_reg(hw, agc_reg_array[i], &phy_data);
1858 if (ret_val)
1859 goto out;
1860
1861 /* Getting bits 15:9, which represent the combination of
1862 * coarse and fine gain values. The result is a number
1863 * that can be put into the lookup table to obtain the
1864 * approximate cable length.
1865 */
1866 cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) &
1867 IGP02E1000_AGC_LENGTH_MASK;
1868
1869 /* Array index bound check. */
1870 if ((cur_agc_index >= IGP02E1000_CABLE_LENGTH_TABLE_SIZE) ||
1871 (cur_agc_index == 0)) {
1872 ret_val = -E1000_ERR_PHY;
1873 goto out;
1874 }
1875
1876 /* Remove min & max AGC values from calculation. */
1877 if (e1000_igp_2_cable_length_table[min_agc_index] >
1878 e1000_igp_2_cable_length_table[cur_agc_index])
1879 min_agc_index = cur_agc_index;
1880 if (e1000_igp_2_cable_length_table[max_agc_index] <
1881 e1000_igp_2_cable_length_table[cur_agc_index])
1882 max_agc_index = cur_agc_index;
1883
1884 agc_value += e1000_igp_2_cable_length_table[cur_agc_index];
1885 }
1886
1887 agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] +
1888 e1000_igp_2_cable_length_table[max_agc_index]);
1889 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2);
1890
1891 /* Calculate cable length with the error range of +/- 10 meters. */
1892 phy->min_cable_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ?
1893 (agc_value - IGP02E1000_AGC_RANGE) : 0;
1894 phy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE;
1895
1896 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
1897
1898 out:
1899 return ret_val;
1900 }
1901
1902 /**
1903 * igb_get_phy_info_m88 - Retrieve PHY information
1904 * @hw: pointer to the HW structure
1905 *
1906 * Valid for only copper links. Read the PHY status register (sticky read)
1907 * to verify that link is up. Read the PHY special control register to
1908 * determine the polarity and 10base-T extended distance. Read the PHY
1909 * special status register to determine MDI/MDIx and current speed. If
1910 * speed is 1000, then determine cable length, local and remote receiver.
1911 **/
igb_get_phy_info_m88(struct e1000_hw * hw)1912 s32 igb_get_phy_info_m88(struct e1000_hw *hw)
1913 {
1914 struct e1000_phy_info *phy = &hw->phy;
1915 s32 ret_val;
1916 u16 phy_data;
1917 bool link;
1918
1919 if (phy->media_type != e1000_media_type_copper) {
1920 hw_dbg("Phy info is only valid for copper media\n");
1921 ret_val = -E1000_ERR_CONFIG;
1922 goto out;
1923 }
1924
1925 ret_val = igb_phy_has_link(hw, 1, 0, &link);
1926 if (ret_val)
1927 goto out;
1928
1929 if (!link) {
1930 hw_dbg("Phy info is only valid if link is up\n");
1931 ret_val = -E1000_ERR_CONFIG;
1932 goto out;
1933 }
1934
1935 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1936 if (ret_val)
1937 goto out;
1938
1939 phy->polarity_correction = (phy_data & M88E1000_PSCR_POLARITY_REVERSAL)
1940 ? true : false;
1941
1942 ret_val = igb_check_polarity_m88(hw);
1943 if (ret_val)
1944 goto out;
1945
1946 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
1947 if (ret_val)
1948 goto out;
1949
1950 phy->is_mdix = (phy_data & M88E1000_PSSR_MDIX) ? true : false;
1951
1952 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) {
1953 ret_val = phy->ops.get_cable_length(hw);
1954 if (ret_val)
1955 goto out;
1956
1957 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &phy_data);
1958 if (ret_val)
1959 goto out;
1960
1961 phy->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS)
1962 ? e1000_1000t_rx_status_ok
1963 : e1000_1000t_rx_status_not_ok;
1964
1965 phy->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS)
1966 ? e1000_1000t_rx_status_ok
1967 : e1000_1000t_rx_status_not_ok;
1968 } else {
1969 /* Set values to "undefined" */
1970 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
1971 phy->local_rx = e1000_1000t_rx_status_undefined;
1972 phy->remote_rx = e1000_1000t_rx_status_undefined;
1973 }
1974
1975 out:
1976 return ret_val;
1977 }
1978
1979 /**
1980 * igb_get_phy_info_igp - Retrieve igp PHY information
1981 * @hw: pointer to the HW structure
1982 *
1983 * Read PHY status to determine if link is up. If link is up, then
1984 * set/determine 10base-T extended distance and polarity correction. Read
1985 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
1986 * determine on the cable length, local and remote receiver.
1987 **/
igb_get_phy_info_igp(struct e1000_hw * hw)1988 s32 igb_get_phy_info_igp(struct e1000_hw *hw)
1989 {
1990 struct e1000_phy_info *phy = &hw->phy;
1991 s32 ret_val;
1992 u16 data;
1993 bool link;
1994
1995 ret_val = igb_phy_has_link(hw, 1, 0, &link);
1996 if (ret_val)
1997 goto out;
1998
1999 if (!link) {
2000 hw_dbg("Phy info is only valid if link is up\n");
2001 ret_val = -E1000_ERR_CONFIG;
2002 goto out;
2003 }
2004
2005 phy->polarity_correction = true;
2006
2007 ret_val = igb_check_polarity_igp(hw);
2008 if (ret_val)
2009 goto out;
2010
2011 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data);
2012 if (ret_val)
2013 goto out;
2014
2015 phy->is_mdix = (data & IGP01E1000_PSSR_MDIX) ? true : false;
2016
2017 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
2018 IGP01E1000_PSSR_SPEED_1000MBPS) {
2019 ret_val = phy->ops.get_cable_length(hw);
2020 if (ret_val)
2021 goto out;
2022
2023 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data);
2024 if (ret_val)
2025 goto out;
2026
2027 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
2028 ? e1000_1000t_rx_status_ok
2029 : e1000_1000t_rx_status_not_ok;
2030
2031 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
2032 ? e1000_1000t_rx_status_ok
2033 : e1000_1000t_rx_status_not_ok;
2034 } else {
2035 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2036 phy->local_rx = e1000_1000t_rx_status_undefined;
2037 phy->remote_rx = e1000_1000t_rx_status_undefined;
2038 }
2039
2040 out:
2041 return ret_val;
2042 }
2043
2044 /**
2045 * igb_phy_sw_reset - PHY software reset
2046 * @hw: pointer to the HW structure
2047 *
2048 * Does a software reset of the PHY by reading the PHY control register and
2049 * setting/write the control register reset bit to the PHY.
2050 **/
igb_phy_sw_reset(struct e1000_hw * hw)2051 s32 igb_phy_sw_reset(struct e1000_hw *hw)
2052 {
2053 s32 ret_val = 0;
2054 u16 phy_ctrl;
2055
2056 if (!(hw->phy.ops.read_reg))
2057 goto out;
2058
2059 ret_val = hw->phy.ops.read_reg(hw, PHY_CONTROL, &phy_ctrl);
2060 if (ret_val)
2061 goto out;
2062
2063 phy_ctrl |= MII_CR_RESET;
2064 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, phy_ctrl);
2065 if (ret_val)
2066 goto out;
2067
2068 udelay(1);
2069
2070 out:
2071 return ret_val;
2072 }
2073
2074 /**
2075 * igb_phy_hw_reset - PHY hardware reset
2076 * @hw: pointer to the HW structure
2077 *
2078 * Verify the reset block is not blocking us from resetting. Acquire
2079 * semaphore (if necessary) and read/set/write the device control reset
2080 * bit in the PHY. Wait the appropriate delay time for the device to
2081 * reset and release the semaphore (if necessary).
2082 **/
igb_phy_hw_reset(struct e1000_hw * hw)2083 s32 igb_phy_hw_reset(struct e1000_hw *hw)
2084 {
2085 struct e1000_phy_info *phy = &hw->phy;
2086 s32 ret_val;
2087 u32 ctrl;
2088
2089 ret_val = igb_check_reset_block(hw);
2090 if (ret_val) {
2091 ret_val = 0;
2092 goto out;
2093 }
2094
2095 ret_val = phy->ops.acquire(hw);
2096 if (ret_val)
2097 goto out;
2098
2099 ctrl = rd32(E1000_CTRL);
2100 wr32(E1000_CTRL, ctrl | E1000_CTRL_PHY_RST);
2101 wrfl();
2102
2103 udelay(phy->reset_delay_us);
2104
2105 wr32(E1000_CTRL, ctrl);
2106 wrfl();
2107
2108 udelay(150);
2109
2110 phy->ops.release(hw);
2111
2112 ret_val = phy->ops.get_cfg_done(hw);
2113
2114 out:
2115 return ret_val;
2116 }
2117
2118 /**
2119 * igb_phy_init_script_igp3 - Inits the IGP3 PHY
2120 * @hw: pointer to the HW structure
2121 *
2122 * Initializes a Intel Gigabit PHY3 when an EEPROM is not present.
2123 **/
igb_phy_init_script_igp3(struct e1000_hw * hw)2124 s32 igb_phy_init_script_igp3(struct e1000_hw *hw)
2125 {
2126 hw_dbg("Running IGP 3 PHY init script\n");
2127
2128 /* PHY init IGP 3 */
2129 /* Enable rise/fall, 10-mode work in class-A */
2130 hw->phy.ops.write_reg(hw, 0x2F5B, 0x9018);
2131 /* Remove all caps from Replica path filter */
2132 hw->phy.ops.write_reg(hw, 0x2F52, 0x0000);
2133 /* Bias trimming for ADC, AFE and Driver (Default) */
2134 hw->phy.ops.write_reg(hw, 0x2FB1, 0x8B24);
2135 /* Increase Hybrid poly bias */
2136 hw->phy.ops.write_reg(hw, 0x2FB2, 0xF8F0);
2137 /* Add 4% to TX amplitude in Giga mode */
2138 hw->phy.ops.write_reg(hw, 0x2010, 0x10B0);
2139 /* Disable trimming (TTT) */
2140 hw->phy.ops.write_reg(hw, 0x2011, 0x0000);
2141 /* Poly DC correction to 94.6% + 2% for all channels */
2142 hw->phy.ops.write_reg(hw, 0x20DD, 0x249A);
2143 /* ABS DC correction to 95.9% */
2144 hw->phy.ops.write_reg(hw, 0x20DE, 0x00D3);
2145 /* BG temp curve trim */
2146 hw->phy.ops.write_reg(hw, 0x28B4, 0x04CE);
2147 /* Increasing ADC OPAMP stage 1 currents to max */
2148 hw->phy.ops.write_reg(hw, 0x2F70, 0x29E4);
2149 /* Force 1000 ( required for enabling PHY regs configuration) */
2150 hw->phy.ops.write_reg(hw, 0x0000, 0x0140);
2151 /* Set upd_freq to 6 */
2152 hw->phy.ops.write_reg(hw, 0x1F30, 0x1606);
2153 /* Disable NPDFE */
2154 hw->phy.ops.write_reg(hw, 0x1F31, 0xB814);
2155 /* Disable adaptive fixed FFE (Default) */
2156 hw->phy.ops.write_reg(hw, 0x1F35, 0x002A);
2157 /* Enable FFE hysteresis */
2158 hw->phy.ops.write_reg(hw, 0x1F3E, 0x0067);
2159 /* Fixed FFE for short cable lengths */
2160 hw->phy.ops.write_reg(hw, 0x1F54, 0x0065);
2161 /* Fixed FFE for medium cable lengths */
2162 hw->phy.ops.write_reg(hw, 0x1F55, 0x002A);
2163 /* Fixed FFE for long cable lengths */
2164 hw->phy.ops.write_reg(hw, 0x1F56, 0x002A);
2165 /* Enable Adaptive Clip Threshold */
2166 hw->phy.ops.write_reg(hw, 0x1F72, 0x3FB0);
2167 /* AHT reset limit to 1 */
2168 hw->phy.ops.write_reg(hw, 0x1F76, 0xC0FF);
2169 /* Set AHT master delay to 127 msec */
2170 hw->phy.ops.write_reg(hw, 0x1F77, 0x1DEC);
2171 /* Set scan bits for AHT */
2172 hw->phy.ops.write_reg(hw, 0x1F78, 0xF9EF);
2173 /* Set AHT Preset bits */
2174 hw->phy.ops.write_reg(hw, 0x1F79, 0x0210);
2175 /* Change integ_factor of channel A to 3 */
2176 hw->phy.ops.write_reg(hw, 0x1895, 0x0003);
2177 /* Change prop_factor of channels BCD to 8 */
2178 hw->phy.ops.write_reg(hw, 0x1796, 0x0008);
2179 /* Change cg_icount + enable integbp for channels BCD */
2180 hw->phy.ops.write_reg(hw, 0x1798, 0xD008);
2181 /* Change cg_icount + enable integbp + change prop_factor_master
2182 * to 8 for channel A
2183 */
2184 hw->phy.ops.write_reg(hw, 0x1898, 0xD918);
2185 /* Disable AHT in Slave mode on channel A */
2186 hw->phy.ops.write_reg(hw, 0x187A, 0x0800);
2187 /* Enable LPLU and disable AN to 1000 in non-D0a states,
2188 * Enable SPD+B2B
2189 */
2190 hw->phy.ops.write_reg(hw, 0x0019, 0x008D);
2191 /* Enable restart AN on an1000_dis change */
2192 hw->phy.ops.write_reg(hw, 0x001B, 0x2080);
2193 /* Enable wh_fifo read clock in 10/100 modes */
2194 hw->phy.ops.write_reg(hw, 0x0014, 0x0045);
2195 /* Restart AN, Speed selection is 1000 */
2196 hw->phy.ops.write_reg(hw, 0x0000, 0x1340);
2197
2198 return 0;
2199 }
2200
2201 /**
2202 * igb_power_up_phy_copper - Restore copper link in case of PHY power down
2203 * @hw: pointer to the HW structure
2204 *
2205 * In the case of a PHY power down to save power, or to turn off link during a
2206 * driver unload, restore the link to previous settings.
2207 **/
igb_power_up_phy_copper(struct e1000_hw * hw)2208 void igb_power_up_phy_copper(struct e1000_hw *hw)
2209 {
2210 u16 mii_reg = 0;
2211
2212 /* The PHY will retain its settings across a power down/up cycle */
2213 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);
2214 mii_reg &= ~MII_CR_POWER_DOWN;
2215 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);
2216 }
2217
2218 /**
2219 * igb_power_down_phy_copper - Power down copper PHY
2220 * @hw: pointer to the HW structure
2221 *
2222 * Power down PHY to save power when interface is down and wake on lan
2223 * is not enabled.
2224 **/
igb_power_down_phy_copper(struct e1000_hw * hw)2225 void igb_power_down_phy_copper(struct e1000_hw *hw)
2226 {
2227 u16 mii_reg = 0;
2228
2229 /* The PHY will retain its settings across a power down/up cycle */
2230 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);
2231 mii_reg |= MII_CR_POWER_DOWN;
2232 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);
2233 usleep_range(1000, 2000);
2234 }
2235
2236 /**
2237 * igb_check_polarity_82580 - Checks the polarity.
2238 * @hw: pointer to the HW structure
2239 *
2240 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
2241 *
2242 * Polarity is determined based on the PHY specific status register.
2243 **/
igb_check_polarity_82580(struct e1000_hw * hw)2244 static s32 igb_check_polarity_82580(struct e1000_hw *hw)
2245 {
2246 struct e1000_phy_info *phy = &hw->phy;
2247 s32 ret_val;
2248 u16 data;
2249
2250
2251 ret_val = phy->ops.read_reg(hw, I82580_PHY_STATUS_2, &data);
2252
2253 if (!ret_val)
2254 phy->cable_polarity = (data & I82580_PHY_STATUS2_REV_POLARITY)
2255 ? e1000_rev_polarity_reversed
2256 : e1000_rev_polarity_normal;
2257
2258 return ret_val;
2259 }
2260
2261 /**
2262 * igb_phy_force_speed_duplex_82580 - Force speed/duplex for I82580 PHY
2263 * @hw: pointer to the HW structure
2264 *
2265 * Calls the PHY setup function to force speed and duplex. Clears the
2266 * auto-crossover to force MDI manually. Waits for link and returns
2267 * successful if link up is successful, else -E1000_ERR_PHY (-2).
2268 **/
igb_phy_force_speed_duplex_82580(struct e1000_hw * hw)2269 s32 igb_phy_force_speed_duplex_82580(struct e1000_hw *hw)
2270 {
2271 struct e1000_phy_info *phy = &hw->phy;
2272 s32 ret_val;
2273 u16 phy_data;
2274 bool link;
2275
2276 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
2277 if (ret_val)
2278 goto out;
2279
2280 igb_phy_force_speed_duplex_setup(hw, &phy_data);
2281
2282 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
2283 if (ret_val)
2284 goto out;
2285
2286 /* Clear Auto-Crossover to force MDI manually. 82580 requires MDI
2287 * forced whenever speed and duplex are forced.
2288 */
2289 ret_val = phy->ops.read_reg(hw, I82580_PHY_CTRL_2, &phy_data);
2290 if (ret_val)
2291 goto out;
2292
2293 phy_data &= ~I82580_PHY_CTRL2_MDIX_CFG_MASK;
2294
2295 ret_val = phy->ops.write_reg(hw, I82580_PHY_CTRL_2, phy_data);
2296 if (ret_val)
2297 goto out;
2298
2299 hw_dbg("I82580_PHY_CTRL_2: %X\n", phy_data);
2300
2301 udelay(1);
2302
2303 if (phy->autoneg_wait_to_complete) {
2304 hw_dbg("Waiting for forced speed/duplex link on 82580 phy\n");
2305
2306 ret_val = igb_phy_has_link(hw, PHY_FORCE_LIMIT, 100000, &link);
2307 if (ret_val)
2308 goto out;
2309
2310 if (!link)
2311 hw_dbg("Link taking longer than expected.\n");
2312
2313 /* Try once more */
2314 ret_val = igb_phy_has_link(hw, PHY_FORCE_LIMIT, 100000, &link);
2315 if (ret_val)
2316 goto out;
2317 }
2318
2319 out:
2320 return ret_val;
2321 }
2322
2323 /**
2324 * igb_get_phy_info_82580 - Retrieve I82580 PHY information
2325 * @hw: pointer to the HW structure
2326 *
2327 * Read PHY status to determine if link is up. If link is up, then
2328 * set/determine 10base-T extended distance and polarity correction. Read
2329 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
2330 * determine on the cable length, local and remote receiver.
2331 **/
igb_get_phy_info_82580(struct e1000_hw * hw)2332 s32 igb_get_phy_info_82580(struct e1000_hw *hw)
2333 {
2334 struct e1000_phy_info *phy = &hw->phy;
2335 s32 ret_val;
2336 u16 data;
2337 bool link;
2338
2339 ret_val = igb_phy_has_link(hw, 1, 0, &link);
2340 if (ret_val)
2341 goto out;
2342
2343 if (!link) {
2344 hw_dbg("Phy info is only valid if link is up\n");
2345 ret_val = -E1000_ERR_CONFIG;
2346 goto out;
2347 }
2348
2349 phy->polarity_correction = true;
2350
2351 ret_val = igb_check_polarity_82580(hw);
2352 if (ret_val)
2353 goto out;
2354
2355 ret_val = phy->ops.read_reg(hw, I82580_PHY_STATUS_2, &data);
2356 if (ret_val)
2357 goto out;
2358
2359 phy->is_mdix = (data & I82580_PHY_STATUS2_MDIX) ? true : false;
2360
2361 if ((data & I82580_PHY_STATUS2_SPEED_MASK) ==
2362 I82580_PHY_STATUS2_SPEED_1000MBPS) {
2363 ret_val = hw->phy.ops.get_cable_length(hw);
2364 if (ret_val)
2365 goto out;
2366
2367 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data);
2368 if (ret_val)
2369 goto out;
2370
2371 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
2372 ? e1000_1000t_rx_status_ok
2373 : e1000_1000t_rx_status_not_ok;
2374
2375 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
2376 ? e1000_1000t_rx_status_ok
2377 : e1000_1000t_rx_status_not_ok;
2378 } else {
2379 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2380 phy->local_rx = e1000_1000t_rx_status_undefined;
2381 phy->remote_rx = e1000_1000t_rx_status_undefined;
2382 }
2383
2384 out:
2385 return ret_val;
2386 }
2387
2388 /**
2389 * igb_get_cable_length_82580 - Determine cable length for 82580 PHY
2390 * @hw: pointer to the HW structure
2391 *
2392 * Reads the diagnostic status register and verifies result is valid before
2393 * placing it in the phy_cable_length field.
2394 **/
igb_get_cable_length_82580(struct e1000_hw * hw)2395 s32 igb_get_cable_length_82580(struct e1000_hw *hw)
2396 {
2397 struct e1000_phy_info *phy = &hw->phy;
2398 s32 ret_val;
2399 u16 phy_data, length;
2400
2401 ret_val = phy->ops.read_reg(hw, I82580_PHY_DIAG_STATUS, &phy_data);
2402 if (ret_val)
2403 goto out;
2404
2405 length = (phy_data & I82580_DSTATUS_CABLE_LENGTH) >>
2406 I82580_DSTATUS_CABLE_LENGTH_SHIFT;
2407
2408 if (length == E1000_CABLE_LENGTH_UNDEFINED)
2409 ret_val = -E1000_ERR_PHY;
2410
2411 phy->cable_length = length;
2412
2413 out:
2414 return ret_val;
2415 }
2416
2417 /**
2418 * igb_write_phy_reg_gs40g - Write GS40G PHY register
2419 * @hw: pointer to the HW structure
2420 * @offset: lower half is register offset to write to
2421 * upper half is page to use.
2422 * @data: data to write at register offset
2423 *
2424 * Acquires semaphore, if necessary, then writes the data to PHY register
2425 * at the offset. Release any acquired semaphores before exiting.
2426 **/
igb_write_phy_reg_gs40g(struct e1000_hw * hw,u32 offset,u16 data)2427 s32 igb_write_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 data)
2428 {
2429 s32 ret_val;
2430 u16 page = offset >> GS40G_PAGE_SHIFT;
2431
2432 offset = offset & GS40G_OFFSET_MASK;
2433 ret_val = hw->phy.ops.acquire(hw);
2434 if (ret_val)
2435 return ret_val;
2436
2437 ret_val = igb_write_phy_reg_mdic(hw, GS40G_PAGE_SELECT, page);
2438 if (ret_val)
2439 goto release;
2440 ret_val = igb_write_phy_reg_mdic(hw, offset, data);
2441
2442 release:
2443 hw->phy.ops.release(hw);
2444 return ret_val;
2445 }
2446
2447 /**
2448 * igb_read_phy_reg_gs40g - Read GS40G PHY register
2449 * @hw: pointer to the HW structure
2450 * @offset: lower half is register offset to read to
2451 * upper half is page to use.
2452 * @data: data to read at register offset
2453 *
2454 * Acquires semaphore, if necessary, then reads the data in the PHY register
2455 * at the offset. Release any acquired semaphores before exiting.
2456 **/
igb_read_phy_reg_gs40g(struct e1000_hw * hw,u32 offset,u16 * data)2457 s32 igb_read_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 *data)
2458 {
2459 s32 ret_val;
2460 u16 page = offset >> GS40G_PAGE_SHIFT;
2461
2462 offset = offset & GS40G_OFFSET_MASK;
2463 ret_val = hw->phy.ops.acquire(hw);
2464 if (ret_val)
2465 return ret_val;
2466
2467 ret_val = igb_write_phy_reg_mdic(hw, GS40G_PAGE_SELECT, page);
2468 if (ret_val)
2469 goto release;
2470 ret_val = igb_read_phy_reg_mdic(hw, offset, data);
2471
2472 release:
2473 hw->phy.ops.release(hw);
2474 return ret_val;
2475 }
2476
2477 /**
2478 * igb_set_master_slave_mode - Setup PHY for Master/slave mode
2479 * @hw: pointer to the HW structure
2480 *
2481 * Sets up Master/slave mode
2482 **/
igb_set_master_slave_mode(struct e1000_hw * hw)2483 static s32 igb_set_master_slave_mode(struct e1000_hw *hw)
2484 {
2485 s32 ret_val;
2486 u16 phy_data;
2487
2488 /* Resolve Master/Slave mode */
2489 ret_val = hw->phy.ops.read_reg(hw, PHY_1000T_CTRL, &phy_data);
2490 if (ret_val)
2491 return ret_val;
2492
2493 /* load defaults for future use */
2494 hw->phy.original_ms_type = (phy_data & CR_1000T_MS_ENABLE) ?
2495 ((phy_data & CR_1000T_MS_VALUE) ?
2496 e1000_ms_force_master :
2497 e1000_ms_force_slave) : e1000_ms_auto;
2498
2499 switch (hw->phy.ms_type) {
2500 case e1000_ms_force_master:
2501 phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
2502 break;
2503 case e1000_ms_force_slave:
2504 phy_data |= CR_1000T_MS_ENABLE;
2505 phy_data &= ~(CR_1000T_MS_VALUE);
2506 break;
2507 case e1000_ms_auto:
2508 phy_data &= ~CR_1000T_MS_ENABLE;
2509 /* fall-through */
2510 default:
2511 break;
2512 }
2513
2514 return hw->phy.ops.write_reg(hw, PHY_1000T_CTRL, phy_data);
2515 }
2516