1 /*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2013 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27 *******************************************************************************/
28
29 #ifndef _IXGBE_H_
30 #define _IXGBE_H_
31
32 #include <linux/bitops.h>
33 #include <linux/types.h>
34 #include <linux/pci.h>
35 #include <linux/netdevice.h>
36 #include <linux/cpumask.h>
37 #include <linux/aer.h>
38 #include <linux/if_vlan.h>
39 #include <linux/jiffies.h>
40
41 #include <linux/timecounter.h>
42 #include <linux/net_tstamp.h>
43 #include <linux/ptp_clock_kernel.h>
44
45 #include "ixgbe_type.h"
46 #include "ixgbe_common.h"
47 #include "ixgbe_dcb.h"
48 #if defined(CONFIG_FCOE) || defined(CONFIG_FCOE_MODULE)
49 #define IXGBE_FCOE
50 #include "ixgbe_fcoe.h"
51 #endif /* CONFIG_FCOE or CONFIG_FCOE_MODULE */
52 #ifdef CONFIG_IXGBE_DCA
53 #include <linux/dca.h>
54 #endif
55
56 #include <net/busy_poll.h>
57
58 #ifdef CONFIG_NET_RX_BUSY_POLL
59 #define BP_EXTENDED_STATS
60 #endif
61 /* common prefix used by pr_<> macros */
62 #undef pr_fmt
63 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
64
65 /* TX/RX descriptor defines */
66 #define IXGBE_DEFAULT_TXD 512
67 #define IXGBE_DEFAULT_TX_WORK 256
68 #define IXGBE_MAX_TXD 4096
69 #define IXGBE_MIN_TXD 64
70
71 #if (PAGE_SIZE < 8192)
72 #define IXGBE_DEFAULT_RXD 512
73 #else
74 #define IXGBE_DEFAULT_RXD 128
75 #endif
76 #define IXGBE_MAX_RXD 4096
77 #define IXGBE_MIN_RXD 64
78
79 /* flow control */
80 #define IXGBE_MIN_FCRTL 0x40
81 #define IXGBE_MAX_FCRTL 0x7FF80
82 #define IXGBE_MIN_FCRTH 0x600
83 #define IXGBE_MAX_FCRTH 0x7FFF0
84 #define IXGBE_DEFAULT_FCPAUSE 0xFFFF
85 #define IXGBE_MIN_FCPAUSE 0
86 #define IXGBE_MAX_FCPAUSE 0xFFFF
87
88 /* Supported Rx Buffer Sizes */
89 #define IXGBE_RXBUFFER_256 256 /* Used for skb receive header */
90 #define IXGBE_RXBUFFER_2K 2048
91 #define IXGBE_RXBUFFER_3K 3072
92 #define IXGBE_RXBUFFER_4K 4096
93 #define IXGBE_MAX_RXBUFFER 16384 /* largest size for a single descriptor */
94
95 /*
96 * NOTE: netdev_alloc_skb reserves up to 64 bytes, NET_IP_ALIGN means we
97 * reserve 64 more, and skb_shared_info adds an additional 320 bytes more,
98 * this adds up to 448 bytes of extra data.
99 *
100 * Since netdev_alloc_skb now allocates a page fragment we can use a value
101 * of 256 and the resultant skb will have a truesize of 960 or less.
102 */
103 #define IXGBE_RX_HDR_SIZE IXGBE_RXBUFFER_256
104
105 /* How many Rx Buffers do we bundle into one write to the hardware ? */
106 #define IXGBE_RX_BUFFER_WRITE 16 /* Must be power of 2 */
107
108 enum ixgbe_tx_flags {
109 /* cmd_type flags */
110 IXGBE_TX_FLAGS_HW_VLAN = 0x01,
111 IXGBE_TX_FLAGS_TSO = 0x02,
112 IXGBE_TX_FLAGS_TSTAMP = 0x04,
113
114 /* olinfo flags */
115 IXGBE_TX_FLAGS_CC = 0x08,
116 IXGBE_TX_FLAGS_IPV4 = 0x10,
117 IXGBE_TX_FLAGS_CSUM = 0x20,
118
119 /* software defined flags */
120 IXGBE_TX_FLAGS_SW_VLAN = 0x40,
121 IXGBE_TX_FLAGS_FCOE = 0x80,
122 };
123
124 /* VLAN info */
125 #define IXGBE_TX_FLAGS_VLAN_MASK 0xffff0000
126 #define IXGBE_TX_FLAGS_VLAN_PRIO_MASK 0xe0000000
127 #define IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT 29
128 #define IXGBE_TX_FLAGS_VLAN_SHIFT 16
129
130 #define IXGBE_MAX_VF_MC_ENTRIES 30
131 #define IXGBE_MAX_VF_FUNCTIONS 64
132 #define IXGBE_MAX_VFTA_ENTRIES 128
133 #define MAX_EMULATION_MAC_ADDRS 16
134 #define IXGBE_MAX_PF_MACVLANS 15
135 #define VMDQ_P(p) ((p) + adapter->ring_feature[RING_F_VMDQ].offset)
136 #define IXGBE_82599_VF_DEVICE_ID 0x10ED
137 #define IXGBE_X540_VF_DEVICE_ID 0x1515
138
139 struct vf_data_storage {
140 unsigned char vf_mac_addresses[ETH_ALEN];
141 u16 vf_mc_hashes[IXGBE_MAX_VF_MC_ENTRIES];
142 u16 num_vf_mc_hashes;
143 u16 default_vf_vlan_id;
144 u16 vlans_enabled;
145 bool clear_to_send;
146 bool pf_set_mac;
147 u16 pf_vlan; /* When set, guest VLAN config not allowed. */
148 u16 pf_qos;
149 u16 tx_rate;
150 u16 vlan_count;
151 u8 spoofchk_enabled;
152 unsigned int vf_api;
153 };
154
155 struct vf_macvlans {
156 struct list_head l;
157 int vf;
158 bool free;
159 bool is_macvlan;
160 u8 vf_macvlan[ETH_ALEN];
161 };
162
163 #define IXGBE_MAX_TXD_PWR 14
164 #define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR)
165
166 /* Tx Descriptors needed, worst case */
167 #define TXD_USE_COUNT(S) DIV_ROUND_UP((S), IXGBE_MAX_DATA_PER_TXD)
168 #define DESC_NEEDED (MAX_SKB_FRAGS + 4)
169
170 /* wrapper around a pointer to a socket buffer,
171 * so a DMA handle can be stored along with the buffer */
172 struct ixgbe_tx_buffer {
173 union ixgbe_adv_tx_desc *next_to_watch;
174 unsigned long time_stamp;
175 struct sk_buff *skb;
176 unsigned int bytecount;
177 unsigned short gso_segs;
178 __be16 protocol;
179 DEFINE_DMA_UNMAP_ADDR(dma);
180 DEFINE_DMA_UNMAP_LEN(len);
181 u32 tx_flags;
182 };
183
184 struct ixgbe_rx_buffer {
185 struct sk_buff *skb;
186 dma_addr_t dma;
187 struct page *page;
188 unsigned int page_offset;
189 };
190
191 struct ixgbe_queue_stats {
192 u64 packets;
193 u64 bytes;
194 #ifdef BP_EXTENDED_STATS
195 u64 yields;
196 u64 misses;
197 u64 cleaned;
198 #endif /* BP_EXTENDED_STATS */
199 };
200
201 struct ixgbe_tx_queue_stats {
202 u64 restart_queue;
203 u64 tx_busy;
204 u64 tx_done_old;
205 };
206
207 struct ixgbe_rx_queue_stats {
208 u64 rsc_count;
209 u64 rsc_flush;
210 u64 non_eop_descs;
211 u64 alloc_rx_page_failed;
212 u64 alloc_rx_buff_failed;
213 u64 csum_err;
214 };
215
216 enum ixgbe_ring_state_t {
217 __IXGBE_TX_FDIR_INIT_DONE,
218 __IXGBE_TX_XPS_INIT_DONE,
219 __IXGBE_TX_DETECT_HANG,
220 __IXGBE_HANG_CHECK_ARMED,
221 __IXGBE_RX_RSC_ENABLED,
222 __IXGBE_RX_CSUM_UDP_ZERO_ERR,
223 __IXGBE_RX_FCOE,
224 };
225
226 struct ixgbe_fwd_adapter {
227 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
228 struct net_device *netdev;
229 struct ixgbe_adapter *real_adapter;
230 unsigned int tx_base_queue;
231 unsigned int rx_base_queue;
232 int pool;
233 };
234
235 #define check_for_tx_hang(ring) \
236 test_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state)
237 #define set_check_for_tx_hang(ring) \
238 set_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state)
239 #define clear_check_for_tx_hang(ring) \
240 clear_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state)
241 #define ring_is_rsc_enabled(ring) \
242 test_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state)
243 #define set_ring_rsc_enabled(ring) \
244 set_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state)
245 #define clear_ring_rsc_enabled(ring) \
246 clear_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state)
247 struct ixgbe_ring {
248 struct ixgbe_ring *next; /* pointer to next ring in q_vector */
249 struct ixgbe_q_vector *q_vector; /* backpointer to host q_vector */
250 struct net_device *netdev; /* netdev ring belongs to */
251 struct device *dev; /* device for DMA mapping */
252 struct ixgbe_fwd_adapter *l2_accel_priv;
253 void *desc; /* descriptor ring memory */
254 union {
255 struct ixgbe_tx_buffer *tx_buffer_info;
256 struct ixgbe_rx_buffer *rx_buffer_info;
257 };
258 unsigned long state;
259 u8 __iomem *tail;
260 dma_addr_t dma; /* phys. address of descriptor ring */
261 unsigned int size; /* length in bytes */
262
263 u16 count; /* amount of descriptors */
264
265 u8 queue_index; /* needed for multiqueue queue management */
266 u8 reg_idx; /* holds the special value that gets
267 * the hardware register offset
268 * associated with this ring, which is
269 * different for DCB and RSS modes
270 */
271 u16 next_to_use;
272 u16 next_to_clean;
273
274 union {
275 u16 next_to_alloc;
276 struct {
277 u8 atr_sample_rate;
278 u8 atr_count;
279 };
280 };
281
282 u8 dcb_tc;
283 struct ixgbe_queue_stats stats;
284 struct u64_stats_sync syncp;
285 union {
286 struct ixgbe_tx_queue_stats tx_stats;
287 struct ixgbe_rx_queue_stats rx_stats;
288 };
289 } ____cacheline_internodealigned_in_smp;
290
291 enum ixgbe_ring_f_enum {
292 RING_F_NONE = 0,
293 RING_F_VMDQ, /* SR-IOV uses the same ring feature */
294 RING_F_RSS,
295 RING_F_FDIR,
296 #ifdef IXGBE_FCOE
297 RING_F_FCOE,
298 #endif /* IXGBE_FCOE */
299
300 RING_F_ARRAY_SIZE /* must be last in enum set */
301 };
302
303 #define IXGBE_MAX_RSS_INDICES 16
304 #define IXGBE_MAX_VMDQ_INDICES 64
305 #define IXGBE_MAX_FDIR_INDICES 63 /* based on q_vector limit */
306 #define IXGBE_MAX_FCOE_INDICES 8
307 #define MAX_RX_QUEUES (IXGBE_MAX_FDIR_INDICES + 1)
308 #define MAX_TX_QUEUES (IXGBE_MAX_FDIR_INDICES + 1)
309 #define IXGBE_MAX_L2A_QUEUES 4
310 #define IXGBE_BAD_L2A_QUEUE 3
311 #define IXGBE_MAX_MACVLANS 31
312 #define IXGBE_MAX_DCBMACVLANS 8
313
314 struct ixgbe_ring_feature {
315 u16 limit; /* upper limit on feature indices */
316 u16 indices; /* current value of indices */
317 u16 mask; /* Mask used for feature to ring mapping */
318 u16 offset; /* offset to start of feature */
319 } ____cacheline_internodealigned_in_smp;
320
321 #define IXGBE_82599_VMDQ_8Q_MASK 0x78
322 #define IXGBE_82599_VMDQ_4Q_MASK 0x7C
323 #define IXGBE_82599_VMDQ_2Q_MASK 0x7E
324
325 /*
326 * FCoE requires that all Rx buffers be over 2200 bytes in length. Since
327 * this is twice the size of a half page we need to double the page order
328 * for FCoE enabled Rx queues.
329 */
ixgbe_rx_bufsz(struct ixgbe_ring * ring)330 static inline unsigned int ixgbe_rx_bufsz(struct ixgbe_ring *ring)
331 {
332 #ifdef IXGBE_FCOE
333 if (test_bit(__IXGBE_RX_FCOE, &ring->state))
334 return (PAGE_SIZE < 8192) ? IXGBE_RXBUFFER_4K :
335 IXGBE_RXBUFFER_3K;
336 #endif
337 return IXGBE_RXBUFFER_2K;
338 }
339
ixgbe_rx_pg_order(struct ixgbe_ring * ring)340 static inline unsigned int ixgbe_rx_pg_order(struct ixgbe_ring *ring)
341 {
342 #ifdef IXGBE_FCOE
343 if (test_bit(__IXGBE_RX_FCOE, &ring->state))
344 return (PAGE_SIZE < 8192) ? 1 : 0;
345 #endif
346 return 0;
347 }
348 #define ixgbe_rx_pg_size(_ring) (PAGE_SIZE << ixgbe_rx_pg_order(_ring))
349
350 struct ixgbe_ring_container {
351 struct ixgbe_ring *ring; /* pointer to linked list of rings */
352 unsigned int total_bytes; /* total bytes processed this int */
353 unsigned int total_packets; /* total packets processed this int */
354 u16 work_limit; /* total work allowed per interrupt */
355 u8 count; /* total number of rings in vector */
356 u8 itr; /* current ITR setting for ring */
357 };
358
359 /* iterator for handling rings in ring container */
360 #define ixgbe_for_each_ring(pos, head) \
361 for (pos = (head).ring; pos != NULL; pos = pos->next)
362
363 #define MAX_RX_PACKET_BUFFERS ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) \
364 ? 8 : 1)
365 #define MAX_TX_PACKET_BUFFERS MAX_RX_PACKET_BUFFERS
366
367 /* MAX_Q_VECTORS of these are allocated,
368 * but we only use one per queue-specific vector.
369 */
370 struct ixgbe_q_vector {
371 struct ixgbe_adapter *adapter;
372 #ifdef CONFIG_IXGBE_DCA
373 int cpu; /* CPU for DCA */
374 #endif
375 u16 v_idx; /* index of q_vector within array, also used for
376 * finding the bit in EICR and friends that
377 * represents the vector for this ring */
378 u16 itr; /* Interrupt throttle rate written to EITR */
379 struct ixgbe_ring_container rx, tx;
380
381 struct napi_struct napi;
382 cpumask_t affinity_mask;
383 int numa_node;
384 struct rcu_head rcu; /* to avoid race with update stats on free */
385 char name[IFNAMSIZ + 9];
386
387 #ifdef CONFIG_NET_RX_BUSY_POLL
388 atomic_t state;
389 #endif /* CONFIG_NET_RX_BUSY_POLL */
390
391 /* for dynamic allocation of rings associated with this q_vector */
392 struct ixgbe_ring ring[0] ____cacheline_internodealigned_in_smp;
393 };
394
395 #ifdef CONFIG_NET_RX_BUSY_POLL
396 enum ixgbe_qv_state_t {
397 IXGBE_QV_STATE_IDLE = 0,
398 IXGBE_QV_STATE_NAPI,
399 IXGBE_QV_STATE_POLL,
400 IXGBE_QV_STATE_DISABLE
401 };
402
ixgbe_qv_init_lock(struct ixgbe_q_vector * q_vector)403 static inline void ixgbe_qv_init_lock(struct ixgbe_q_vector *q_vector)
404 {
405 /* reset state to idle */
406 atomic_set(&q_vector->state, IXGBE_QV_STATE_IDLE);
407 }
408
409 /* called from the device poll routine to get ownership of a q_vector */
ixgbe_qv_lock_napi(struct ixgbe_q_vector * q_vector)410 static inline bool ixgbe_qv_lock_napi(struct ixgbe_q_vector *q_vector)
411 {
412 int rc = atomic_cmpxchg(&q_vector->state, IXGBE_QV_STATE_IDLE,
413 IXGBE_QV_STATE_NAPI);
414 #ifdef BP_EXTENDED_STATS
415 if (rc != IXGBE_QV_STATE_IDLE)
416 q_vector->tx.ring->stats.yields++;
417 #endif
418
419 return rc == IXGBE_QV_STATE_IDLE;
420 }
421
422 /* returns true is someone tried to get the qv while napi had it */
ixgbe_qv_unlock_napi(struct ixgbe_q_vector * q_vector)423 static inline void ixgbe_qv_unlock_napi(struct ixgbe_q_vector *q_vector)
424 {
425 WARN_ON(atomic_read(&q_vector->state) != IXGBE_QV_STATE_NAPI);
426
427 /* flush any outstanding Rx frames */
428 if (q_vector->napi.gro_list)
429 napi_gro_flush(&q_vector->napi, false);
430
431 /* reset state to idle */
432 atomic_set(&q_vector->state, IXGBE_QV_STATE_IDLE);
433 }
434
435 /* called from ixgbe_low_latency_poll() */
ixgbe_qv_lock_poll(struct ixgbe_q_vector * q_vector)436 static inline bool ixgbe_qv_lock_poll(struct ixgbe_q_vector *q_vector)
437 {
438 int rc = atomic_cmpxchg(&q_vector->state, IXGBE_QV_STATE_IDLE,
439 IXGBE_QV_STATE_POLL);
440 #ifdef BP_EXTENDED_STATS
441 if (rc != IXGBE_QV_STATE_IDLE)
442 q_vector->tx.ring->stats.yields++;
443 #endif
444 return rc == IXGBE_QV_STATE_IDLE;
445 }
446
447 /* returns true if someone tried to get the qv while it was locked */
ixgbe_qv_unlock_poll(struct ixgbe_q_vector * q_vector)448 static inline void ixgbe_qv_unlock_poll(struct ixgbe_q_vector *q_vector)
449 {
450 WARN_ON(atomic_read(&q_vector->state) != IXGBE_QV_STATE_POLL);
451
452 /* reset state to idle */
453 atomic_set(&q_vector->state, IXGBE_QV_STATE_IDLE);
454 }
455
456 /* true if a socket is polling, even if it did not get the lock */
ixgbe_qv_busy_polling(struct ixgbe_q_vector * q_vector)457 static inline bool ixgbe_qv_busy_polling(struct ixgbe_q_vector *q_vector)
458 {
459 return atomic_read(&q_vector->state) == IXGBE_QV_STATE_POLL;
460 }
461
462 /* false if QV is currently owned */
ixgbe_qv_disable(struct ixgbe_q_vector * q_vector)463 static inline bool ixgbe_qv_disable(struct ixgbe_q_vector *q_vector)
464 {
465 int rc = atomic_cmpxchg(&q_vector->state, IXGBE_QV_STATE_IDLE,
466 IXGBE_QV_STATE_DISABLE);
467
468 return rc == IXGBE_QV_STATE_IDLE;
469 }
470
471 #else /* CONFIG_NET_RX_BUSY_POLL */
ixgbe_qv_init_lock(struct ixgbe_q_vector * q_vector)472 static inline void ixgbe_qv_init_lock(struct ixgbe_q_vector *q_vector)
473 {
474 }
475
ixgbe_qv_lock_napi(struct ixgbe_q_vector * q_vector)476 static inline bool ixgbe_qv_lock_napi(struct ixgbe_q_vector *q_vector)
477 {
478 return true;
479 }
480
ixgbe_qv_unlock_napi(struct ixgbe_q_vector * q_vector)481 static inline bool ixgbe_qv_unlock_napi(struct ixgbe_q_vector *q_vector)
482 {
483 return false;
484 }
485
ixgbe_qv_lock_poll(struct ixgbe_q_vector * q_vector)486 static inline bool ixgbe_qv_lock_poll(struct ixgbe_q_vector *q_vector)
487 {
488 return false;
489 }
490
ixgbe_qv_unlock_poll(struct ixgbe_q_vector * q_vector)491 static inline bool ixgbe_qv_unlock_poll(struct ixgbe_q_vector *q_vector)
492 {
493 return false;
494 }
495
ixgbe_qv_busy_polling(struct ixgbe_q_vector * q_vector)496 static inline bool ixgbe_qv_busy_polling(struct ixgbe_q_vector *q_vector)
497 {
498 return false;
499 }
500
ixgbe_qv_disable(struct ixgbe_q_vector * q_vector)501 static inline bool ixgbe_qv_disable(struct ixgbe_q_vector *q_vector)
502 {
503 return true;
504 }
505
506 #endif /* CONFIG_NET_RX_BUSY_POLL */
507
508 #ifdef CONFIG_IXGBE_HWMON
509
510 #define IXGBE_HWMON_TYPE_LOC 0
511 #define IXGBE_HWMON_TYPE_TEMP 1
512 #define IXGBE_HWMON_TYPE_CAUTION 2
513 #define IXGBE_HWMON_TYPE_MAX 3
514
515 struct hwmon_attr {
516 struct device_attribute dev_attr;
517 struct ixgbe_hw *hw;
518 struct ixgbe_thermal_diode_data *sensor;
519 char name[12];
520 };
521
522 struct hwmon_buff {
523 struct attribute_group group;
524 const struct attribute_group *groups[2];
525 struct attribute *attrs[IXGBE_MAX_SENSORS * 4 + 1];
526 struct hwmon_attr hwmon_list[IXGBE_MAX_SENSORS * 4];
527 unsigned int n_hwmon;
528 };
529 #endif /* CONFIG_IXGBE_HWMON */
530
531 /*
532 * microsecond values for various ITR rates shifted by 2 to fit itr register
533 * with the first 3 bits reserved 0
534 */
535 #define IXGBE_MIN_RSC_ITR 24
536 #define IXGBE_100K_ITR 40
537 #define IXGBE_20K_ITR 200
538 #define IXGBE_10K_ITR 400
539 #define IXGBE_8K_ITR 500
540
541 /* ixgbe_test_staterr - tests bits in Rx descriptor status and error fields */
ixgbe_test_staterr(union ixgbe_adv_rx_desc * rx_desc,const u32 stat_err_bits)542 static inline __le32 ixgbe_test_staterr(union ixgbe_adv_rx_desc *rx_desc,
543 const u32 stat_err_bits)
544 {
545 return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits);
546 }
547
ixgbe_desc_unused(struct ixgbe_ring * ring)548 static inline u16 ixgbe_desc_unused(struct ixgbe_ring *ring)
549 {
550 u16 ntc = ring->next_to_clean;
551 u16 ntu = ring->next_to_use;
552
553 return ((ntc > ntu) ? 0 : ring->count) + ntc - ntu - 1;
554 }
555
ixgbe_write_tail(struct ixgbe_ring * ring,u32 value)556 static inline void ixgbe_write_tail(struct ixgbe_ring *ring, u32 value)
557 {
558 writel(value, ring->tail);
559 }
560
561 #define IXGBE_RX_DESC(R, i) \
562 (&(((union ixgbe_adv_rx_desc *)((R)->desc))[i]))
563 #define IXGBE_TX_DESC(R, i) \
564 (&(((union ixgbe_adv_tx_desc *)((R)->desc))[i]))
565 #define IXGBE_TX_CTXTDESC(R, i) \
566 (&(((struct ixgbe_adv_tx_context_desc *)((R)->desc))[i]))
567
568 #define IXGBE_MAX_JUMBO_FRAME_SIZE 9728 /* Maximum Supported Size 9.5KB */
569 #ifdef IXGBE_FCOE
570 /* Use 3K as the baby jumbo frame size for FCoE */
571 #define IXGBE_FCOE_JUMBO_FRAME_SIZE 3072
572 #endif /* IXGBE_FCOE */
573
574 #define OTHER_VECTOR 1
575 #define NON_Q_VECTORS (OTHER_VECTOR)
576
577 #define MAX_MSIX_VECTORS_82599 64
578 #define MAX_Q_VECTORS_82599 64
579 #define MAX_MSIX_VECTORS_82598 18
580 #define MAX_Q_VECTORS_82598 16
581
582 struct ixgbe_mac_addr {
583 u8 addr[ETH_ALEN];
584 u16 queue;
585 u16 state; /* bitmask */
586 };
587 #define IXGBE_MAC_STATE_DEFAULT 0x1
588 #define IXGBE_MAC_STATE_MODIFIED 0x2
589 #define IXGBE_MAC_STATE_IN_USE 0x4
590
591 #define MAX_Q_VECTORS MAX_Q_VECTORS_82599
592 #define MAX_MSIX_COUNT MAX_MSIX_VECTORS_82599
593
594 #define MIN_MSIX_Q_VECTORS 1
595 #define MIN_MSIX_COUNT (MIN_MSIX_Q_VECTORS + NON_Q_VECTORS)
596
597 /* default to trying for four seconds */
598 #define IXGBE_TRY_LINK_TIMEOUT (4 * HZ)
599
600 /* board specific private data structure */
601 struct ixgbe_adapter {
602 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
603 /* OS defined structs */
604 struct net_device *netdev;
605 struct pci_dev *pdev;
606
607 unsigned long state;
608
609 /* Some features need tri-state capability,
610 * thus the additional *_CAPABLE flags.
611 */
612 u32 flags;
613 #define IXGBE_FLAG_MSI_ENABLED (u32)(1 << 1)
614 #define IXGBE_FLAG_MSIX_ENABLED (u32)(1 << 3)
615 #define IXGBE_FLAG_RX_1BUF_CAPABLE (u32)(1 << 4)
616 #define IXGBE_FLAG_RX_PS_CAPABLE (u32)(1 << 5)
617 #define IXGBE_FLAG_RX_PS_ENABLED (u32)(1 << 6)
618 #define IXGBE_FLAG_IN_NETPOLL (u32)(1 << 7)
619 #define IXGBE_FLAG_DCA_ENABLED (u32)(1 << 8)
620 #define IXGBE_FLAG_DCA_CAPABLE (u32)(1 << 9)
621 #define IXGBE_FLAG_IMIR_ENABLED (u32)(1 << 10)
622 #define IXGBE_FLAG_MQ_CAPABLE (u32)(1 << 11)
623 #define IXGBE_FLAG_DCB_ENABLED (u32)(1 << 12)
624 #define IXGBE_FLAG_VMDQ_CAPABLE (u32)(1 << 13)
625 #define IXGBE_FLAG_VMDQ_ENABLED (u32)(1 << 14)
626 #define IXGBE_FLAG_FAN_FAIL_CAPABLE (u32)(1 << 15)
627 #define IXGBE_FLAG_NEED_LINK_UPDATE (u32)(1 << 16)
628 #define IXGBE_FLAG_NEED_LINK_CONFIG (u32)(1 << 17)
629 #define IXGBE_FLAG_FDIR_HASH_CAPABLE (u32)(1 << 18)
630 #define IXGBE_FLAG_FDIR_PERFECT_CAPABLE (u32)(1 << 19)
631 #define IXGBE_FLAG_FCOE_CAPABLE (u32)(1 << 20)
632 #define IXGBE_FLAG_FCOE_ENABLED (u32)(1 << 21)
633 #define IXGBE_FLAG_SRIOV_CAPABLE (u32)(1 << 22)
634 #define IXGBE_FLAG_SRIOV_ENABLED (u32)(1 << 23)
635
636 u32 flags2;
637 #define IXGBE_FLAG2_RSC_CAPABLE (u32)(1 << 0)
638 #define IXGBE_FLAG2_RSC_ENABLED (u32)(1 << 1)
639 #define IXGBE_FLAG2_TEMP_SENSOR_CAPABLE (u32)(1 << 2)
640 #define IXGBE_FLAG2_TEMP_SENSOR_EVENT (u32)(1 << 3)
641 #define IXGBE_FLAG2_SEARCH_FOR_SFP (u32)(1 << 4)
642 #define IXGBE_FLAG2_SFP_NEEDS_RESET (u32)(1 << 5)
643 #define IXGBE_FLAG2_RESET_REQUESTED (u32)(1 << 6)
644 #define IXGBE_FLAG2_FDIR_REQUIRES_REINIT (u32)(1 << 7)
645 #define IXGBE_FLAG2_RSS_FIELD_IPV4_UDP (u32)(1 << 8)
646 #define IXGBE_FLAG2_RSS_FIELD_IPV6_UDP (u32)(1 << 9)
647 #define IXGBE_FLAG2_PTP_PPS_ENABLED (u32)(1 << 10)
648 #define IXGBE_FLAG2_BRIDGE_MODE_VEB (u32)(1 << 11)
649
650 /* Tx fast path data */
651 int num_tx_queues;
652 u16 tx_itr_setting;
653 u16 tx_work_limit;
654
655 /* Rx fast path data */
656 int num_rx_queues;
657 u16 rx_itr_setting;
658
659 /* TX */
660 struct ixgbe_ring *tx_ring[MAX_TX_QUEUES] ____cacheline_aligned_in_smp;
661
662 u64 restart_queue;
663 u64 lsc_int;
664 u32 tx_timeout_count;
665
666 /* RX */
667 struct ixgbe_ring *rx_ring[MAX_RX_QUEUES];
668 int num_rx_pools; /* == num_rx_queues in 82598 */
669 int num_rx_queues_per_pool; /* 1 if 82598, can be many if 82599 */
670 u64 hw_csum_rx_error;
671 u64 hw_rx_no_dma_resources;
672 u64 rsc_total_count;
673 u64 rsc_total_flush;
674 u64 non_eop_descs;
675 u32 alloc_rx_page_failed;
676 u32 alloc_rx_buff_failed;
677
678 struct ixgbe_q_vector *q_vector[MAX_Q_VECTORS];
679
680 /* DCB parameters */
681 struct ieee_pfc *ixgbe_ieee_pfc;
682 struct ieee_ets *ixgbe_ieee_ets;
683 struct ixgbe_dcb_config dcb_cfg;
684 struct ixgbe_dcb_config temp_dcb_cfg;
685 u8 dcb_set_bitmap;
686 u8 dcbx_cap;
687 enum ixgbe_fc_mode last_lfc_mode;
688
689 int num_q_vectors; /* current number of q_vectors for device */
690 int max_q_vectors; /* true count of q_vectors for device */
691 struct ixgbe_ring_feature ring_feature[RING_F_ARRAY_SIZE];
692 struct msix_entry *msix_entries;
693
694 u32 test_icr;
695 struct ixgbe_ring test_tx_ring;
696 struct ixgbe_ring test_rx_ring;
697
698 /* structs defined in ixgbe_hw.h */
699 struct ixgbe_hw hw;
700 u16 msg_enable;
701 struct ixgbe_hw_stats stats;
702
703 u64 tx_busy;
704 unsigned int tx_ring_count;
705 unsigned int rx_ring_count;
706
707 u32 link_speed;
708 bool link_up;
709 unsigned long link_check_timeout;
710
711 struct timer_list service_timer;
712 struct work_struct service_task;
713
714 struct hlist_head fdir_filter_list;
715 unsigned long fdir_overflow; /* number of times ATR was backed off */
716 union ixgbe_atr_input fdir_mask;
717 int fdir_filter_count;
718 u32 fdir_pballoc;
719 u32 atr_sample_rate;
720 spinlock_t fdir_perfect_lock;
721
722 #ifdef IXGBE_FCOE
723 struct ixgbe_fcoe fcoe;
724 #endif /* IXGBE_FCOE */
725 u8 __iomem *io_addr; /* Mainly for iounmap use */
726 u32 wol;
727
728 u16 eeprom_verh;
729 u16 eeprom_verl;
730 u16 eeprom_cap;
731
732 u32 interrupt_event;
733 u32 led_reg;
734
735 struct ptp_clock *ptp_clock;
736 struct ptp_clock_info ptp_caps;
737 struct work_struct ptp_tx_work;
738 struct sk_buff *ptp_tx_skb;
739 struct hwtstamp_config tstamp_config;
740 unsigned long ptp_tx_start;
741 unsigned long last_overflow_check;
742 unsigned long last_rx_ptp_check;
743 unsigned long last_rx_timestamp;
744 spinlock_t tmreg_lock;
745 struct cyclecounter cc;
746 struct timecounter tc;
747 u32 base_incval;
748
749 /* SR-IOV */
750 DECLARE_BITMAP(active_vfs, IXGBE_MAX_VF_FUNCTIONS);
751 unsigned int num_vfs;
752 struct vf_data_storage *vfinfo;
753 int vf_rate_link_speed;
754 struct vf_macvlans vf_mvs;
755 struct vf_macvlans *mv_list;
756
757 u32 timer_event_accumulator;
758 u32 vferr_refcount;
759 struct ixgbe_mac_addr *mac_table;
760 struct kobject *info_kobj;
761 #ifdef CONFIG_IXGBE_HWMON
762 struct hwmon_buff *ixgbe_hwmon_buff;
763 #endif /* CONFIG_IXGBE_HWMON */
764 #ifdef CONFIG_DEBUG_FS
765 struct dentry *ixgbe_dbg_adapter;
766 #endif /*CONFIG_DEBUG_FS*/
767
768 u8 default_up;
769 unsigned long fwd_bitmask; /* Bitmask indicating in use pools */
770 };
771
772 struct ixgbe_fdir_filter {
773 struct hlist_node fdir_node;
774 union ixgbe_atr_input filter;
775 u16 sw_idx;
776 u16 action;
777 };
778
779 enum ixgbe_state_t {
780 __IXGBE_TESTING,
781 __IXGBE_RESETTING,
782 __IXGBE_DOWN,
783 __IXGBE_DISABLED,
784 __IXGBE_REMOVING,
785 __IXGBE_SERVICE_SCHED,
786 __IXGBE_SERVICE_INITED,
787 __IXGBE_IN_SFP_INIT,
788 __IXGBE_PTP_RUNNING,
789 __IXGBE_PTP_TX_IN_PROGRESS,
790 };
791
792 struct ixgbe_cb {
793 union { /* Union defining head/tail partner */
794 struct sk_buff *head;
795 struct sk_buff *tail;
796 };
797 dma_addr_t dma;
798 u16 append_cnt;
799 bool page_released;
800 };
801 #define IXGBE_CB(skb) ((struct ixgbe_cb *)(skb)->cb)
802
803 enum ixgbe_boards {
804 board_82598,
805 board_82599,
806 board_X540,
807 };
808
809 extern struct ixgbe_info ixgbe_82598_info;
810 extern struct ixgbe_info ixgbe_82599_info;
811 extern struct ixgbe_info ixgbe_X540_info;
812 #ifdef CONFIG_IXGBE_DCB
813 extern const struct dcbnl_rtnl_ops dcbnl_ops;
814 #endif
815
816 extern char ixgbe_driver_name[];
817 extern const char ixgbe_driver_version[];
818 #ifdef IXGBE_FCOE
819 extern char ixgbe_default_device_descr[];
820 #endif /* IXGBE_FCOE */
821
822 void ixgbe_up(struct ixgbe_adapter *adapter);
823 void ixgbe_down(struct ixgbe_adapter *adapter);
824 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter);
825 void ixgbe_reset(struct ixgbe_adapter *adapter);
826 void ixgbe_set_ethtool_ops(struct net_device *netdev);
827 int ixgbe_setup_rx_resources(struct ixgbe_ring *);
828 int ixgbe_setup_tx_resources(struct ixgbe_ring *);
829 void ixgbe_free_rx_resources(struct ixgbe_ring *);
830 void ixgbe_free_tx_resources(struct ixgbe_ring *);
831 void ixgbe_configure_rx_ring(struct ixgbe_adapter *, struct ixgbe_ring *);
832 void ixgbe_configure_tx_ring(struct ixgbe_adapter *, struct ixgbe_ring *);
833 void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter, struct ixgbe_ring *);
834 void ixgbe_update_stats(struct ixgbe_adapter *adapter);
835 int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter);
836 int ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id,
837 u16 subdevice_id);
838 #ifdef CONFIG_PCI_IOV
839 void ixgbe_full_sync_mac_table(struct ixgbe_adapter *adapter);
840 #endif
841 int ixgbe_add_mac_filter(struct ixgbe_adapter *adapter,
842 u8 *addr, u16 queue);
843 int ixgbe_del_mac_filter(struct ixgbe_adapter *adapter,
844 u8 *addr, u16 queue);
845 void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter);
846 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *, struct ixgbe_adapter *,
847 struct ixgbe_ring *);
848 void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *,
849 struct ixgbe_tx_buffer *);
850 void ixgbe_alloc_rx_buffers(struct ixgbe_ring *, u16);
851 void ixgbe_write_eitr(struct ixgbe_q_vector *);
852 int ixgbe_poll(struct napi_struct *napi, int budget);
853 int ethtool_ioctl(struct ifreq *ifr);
854 s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw);
855 s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 fdirctrl);
856 s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl);
857 s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
858 union ixgbe_atr_hash_dword input,
859 union ixgbe_atr_hash_dword common,
860 u8 queue);
861 s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw,
862 union ixgbe_atr_input *input_mask);
863 s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw,
864 union ixgbe_atr_input *input,
865 u16 soft_id, u8 queue);
866 s32 ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw *hw,
867 union ixgbe_atr_input *input,
868 u16 soft_id);
869 void ixgbe_atr_compute_perfect_hash_82599(union ixgbe_atr_input *input,
870 union ixgbe_atr_input *mask);
871 void ixgbe_set_rx_mode(struct net_device *netdev);
872 #ifdef CONFIG_IXGBE_DCB
873 void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter);
874 #endif
875 int ixgbe_setup_tc(struct net_device *dev, u8 tc);
876 void ixgbe_tx_ctxtdesc(struct ixgbe_ring *, u32, u32, u32, u32);
877 void ixgbe_do_reset(struct net_device *netdev);
878 #ifdef CONFIG_IXGBE_HWMON
879 void ixgbe_sysfs_exit(struct ixgbe_adapter *adapter);
880 int ixgbe_sysfs_init(struct ixgbe_adapter *adapter);
881 #endif /* CONFIG_IXGBE_HWMON */
882 #ifdef IXGBE_FCOE
883 void ixgbe_configure_fcoe(struct ixgbe_adapter *adapter);
884 int ixgbe_fso(struct ixgbe_ring *tx_ring, struct ixgbe_tx_buffer *first,
885 u8 *hdr_len);
886 int ixgbe_fcoe_ddp(struct ixgbe_adapter *adapter,
887 union ixgbe_adv_rx_desc *rx_desc, struct sk_buff *skb);
888 int ixgbe_fcoe_ddp_get(struct net_device *netdev, u16 xid,
889 struct scatterlist *sgl, unsigned int sgc);
890 int ixgbe_fcoe_ddp_target(struct net_device *netdev, u16 xid,
891 struct scatterlist *sgl, unsigned int sgc);
892 int ixgbe_fcoe_ddp_put(struct net_device *netdev, u16 xid);
893 int ixgbe_setup_fcoe_ddp_resources(struct ixgbe_adapter *adapter);
894 void ixgbe_free_fcoe_ddp_resources(struct ixgbe_adapter *adapter);
895 int ixgbe_fcoe_enable(struct net_device *netdev);
896 int ixgbe_fcoe_disable(struct net_device *netdev);
897 #ifdef CONFIG_IXGBE_DCB
898 u8 ixgbe_fcoe_getapp(struct ixgbe_adapter *adapter);
899 u8 ixgbe_fcoe_setapp(struct ixgbe_adapter *adapter, u8 up);
900 #endif /* CONFIG_IXGBE_DCB */
901 int ixgbe_fcoe_get_wwn(struct net_device *netdev, u64 *wwn, int type);
902 int ixgbe_fcoe_get_hbainfo(struct net_device *netdev,
903 struct netdev_fcoe_hbainfo *info);
904 u8 ixgbe_fcoe_get_tc(struct ixgbe_adapter *adapter);
905 #endif /* IXGBE_FCOE */
906 #ifdef CONFIG_DEBUG_FS
907 void ixgbe_dbg_adapter_init(struct ixgbe_adapter *adapter);
908 void ixgbe_dbg_adapter_exit(struct ixgbe_adapter *adapter);
909 void ixgbe_dbg_init(void);
910 void ixgbe_dbg_exit(void);
911 #else
ixgbe_dbg_adapter_init(struct ixgbe_adapter * adapter)912 static inline void ixgbe_dbg_adapter_init(struct ixgbe_adapter *adapter) {}
ixgbe_dbg_adapter_exit(struct ixgbe_adapter * adapter)913 static inline void ixgbe_dbg_adapter_exit(struct ixgbe_adapter *adapter) {}
ixgbe_dbg_init(void)914 static inline void ixgbe_dbg_init(void) {}
ixgbe_dbg_exit(void)915 static inline void ixgbe_dbg_exit(void) {}
916 #endif /* CONFIG_DEBUG_FS */
txring_txq(const struct ixgbe_ring * ring)917 static inline struct netdev_queue *txring_txq(const struct ixgbe_ring *ring)
918 {
919 return netdev_get_tx_queue(ring->netdev, ring->queue_index);
920 }
921
922 void ixgbe_ptp_init(struct ixgbe_adapter *adapter);
923 void ixgbe_ptp_suspend(struct ixgbe_adapter *adapter);
924 void ixgbe_ptp_stop(struct ixgbe_adapter *adapter);
925 void ixgbe_ptp_overflow_check(struct ixgbe_adapter *adapter);
926 void ixgbe_ptp_rx_hang(struct ixgbe_adapter *adapter);
927 void ixgbe_ptp_rx_hwtstamp(struct ixgbe_adapter *adapter, struct sk_buff *skb);
928 int ixgbe_ptp_set_ts_config(struct ixgbe_adapter *adapter, struct ifreq *ifr);
929 int ixgbe_ptp_get_ts_config(struct ixgbe_adapter *adapter, struct ifreq *ifr);
930 void ixgbe_ptp_start_cyclecounter(struct ixgbe_adapter *adapter);
931 void ixgbe_ptp_reset(struct ixgbe_adapter *adapter);
932 void ixgbe_ptp_check_pps_event(struct ixgbe_adapter *adapter, u32 eicr);
933 #ifdef CONFIG_PCI_IOV
934 void ixgbe_sriov_reinit(struct ixgbe_adapter *adapter);
935 #endif
936
937 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
938 struct ixgbe_adapter *adapter,
939 struct ixgbe_ring *tx_ring);
940 #endif /* _IXGBE_H_ */
941